mirror of
https://github.com/QIDITECH/klipper.git
synced 2026-01-31 07:58:42 +03:00
Upload Q1_Pro klipper
This commit is contained in:
CChen616
Binary file not shown.
@@ -1,72 +1,72 @@
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016 Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of the copyright holders nor the names of
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 0
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
|
||||
// is at least 8 digits long.
|
||||
//
|
||||
#define COMPONENT_VERSION 00010000
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 50
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.0"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2016-09-15 13:24:20"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Copyright (C) 2016 Atmel Corporation
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
*
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
*
|
||||
* * Neither the name of the copyright holders nor the names of
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 0
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION
|
||||
// is at least 8 digits long.
|
||||
//
|
||||
#define COMPONENT_VERSION 00010000
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 50
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.0"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2016-09-15 13:24:20"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
|
||||
@@ -1,64 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "samd21.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (1000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "samd21.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (1000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -1,64 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 3
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version.
|
||||
//
|
||||
#define COMPONENT_VERSION 10003
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 304
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.3"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2018-05-23 09:26:19"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 3
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version.
|
||||
//
|
||||
#define COMPONENT_VERSION 10003
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 304
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.3"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2018-05-23 09:26:19"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,272 +1,272 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for DAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_COMPONENT_
|
||||
#define _SAMD21_DAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DAC Digital Analog Converter */
|
||||
/*@{*/
|
||||
|
||||
#define DAC_U2214
|
||||
#define REV_DAC 0x110
|
||||
|
||||
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
|
||||
#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
|
||||
|
||||
#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
|
||||
#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
|
||||
#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
|
||||
#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
|
||||
#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
|
||||
#define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos)
|
||||
#define DAC_CTRLA_MASK _U_(0x07) /**< \brief (DAC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
|
||||
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
|
||||
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
|
||||
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
|
||||
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
|
||||
uint8_t :1; /*!< bit: 5 Reserved */
|
||||
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
|
||||
#define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */
|
||||
|
||||
#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
|
||||
#define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos)
|
||||
#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
|
||||
#define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos)
|
||||
#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
|
||||
#define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos)
|
||||
#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
|
||||
#define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos)
|
||||
#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
|
||||
#define DAC_CTRLB_BDWP (_U_(0x1) << DAC_CTRLB_BDWP_Pos)
|
||||
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
|
||||
#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
|
||||
#define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */
|
||||
#define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */
|
||||
#define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */
|
||||
#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_MASK _U_(0xDF) /**< \brief (DAC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
|
||||
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
|
||||
#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
|
||||
#define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos)
|
||||
#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
|
||||
#define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos)
|
||||
#define DAC_EVCTRL_MASK _U_(0x03) /**< \brief (DAC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
|
||||
#define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos)
|
||||
#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
|
||||
#define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos)
|
||||
#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define DAC_INTENCLR_SYNCRDY (_U_(0x1) << DAC_INTENCLR_SYNCRDY_Pos)
|
||||
#define DAC_INTENCLR_MASK _U_(0x07) /**< \brief (DAC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
|
||||
#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
|
||||
#define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos)
|
||||
#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
|
||||
#define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos)
|
||||
#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define DAC_INTENSET_SYNCRDY (_U_(0x1) << DAC_INTENSET_SYNCRDY_Pos)
|
||||
#define DAC_INTENSET_MASK _U_(0x07) /**< \brief (DAC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
__I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
|
||||
#define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos)
|
||||
#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
|
||||
#define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos)
|
||||
#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
|
||||
#define DAC_INTFLAG_SYNCRDY (_U_(0x1) << DAC_INTFLAG_SYNCRDY_Pos)
|
||||
#define DAC_INTFLAG_MASK _U_(0x07) /**< \brief (DAC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
|
||||
#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
|
||||
|
||||
#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
|
||||
#define DAC_STATUS_SYNCBUSY (_U_(0x1) << DAC_STATUS_SYNCBUSY_Pos)
|
||||
#define DAC_STATUS_MASK _U_(0x80) /**< \brief (DAC_STATUS) MASK Register */
|
||||
|
||||
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} DAC_DATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
|
||||
#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */
|
||||
|
||||
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
|
||||
#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
|
||||
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
|
||||
#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
|
||||
|
||||
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} DAC_DATABUF_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
|
||||
#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */
|
||||
|
||||
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
|
||||
#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
|
||||
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
|
||||
#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
|
||||
|
||||
/** \brief DAC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
|
||||
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
|
||||
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
|
||||
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
|
||||
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
|
||||
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
|
||||
} Dac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DAC_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for DAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_COMPONENT_
|
||||
#define _SAMD21_DAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR DAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_DAC Digital Analog Converter */
|
||||
/*@{*/
|
||||
|
||||
#define DAC_U2214
|
||||
#define REV_DAC 0x110
|
||||
|
||||
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */
|
||||
#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */
|
||||
|
||||
#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */
|
||||
#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos)
|
||||
#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */
|
||||
#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos)
|
||||
#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */
|
||||
#define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos)
|
||||
#define DAC_CTRLA_MASK _U_(0x07) /**< \brief (DAC_CTRLA) MASK Register */
|
||||
|
||||
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
|
||||
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
|
||||
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
|
||||
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
|
||||
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
|
||||
uint8_t :1; /*!< bit: 5 Reserved */
|
||||
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */
|
||||
#define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */
|
||||
|
||||
#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */
|
||||
#define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos)
|
||||
#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */
|
||||
#define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos)
|
||||
#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */
|
||||
#define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos)
|
||||
#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */
|
||||
#define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos)
|
||||
#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */
|
||||
#define DAC_CTRLB_BDWP (_U_(0x1) << DAC_CTRLB_BDWP_Pos)
|
||||
#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */
|
||||
#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))
|
||||
#define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */
|
||||
#define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */
|
||||
#define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */
|
||||
#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos)
|
||||
#define DAC_CTRLB_MASK _U_(0xDF) /**< \brief (DAC_CTRLB) MASK Register */
|
||||
|
||||
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
|
||||
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_EVCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */
|
||||
#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */
|
||||
|
||||
#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */
|
||||
#define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos)
|
||||
#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */
|
||||
#define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos)
|
||||
#define DAC_EVCTRL_MASK _U_(0x03) /**< \brief (DAC_EVCTRL) MASK Register */
|
||||
|
||||
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */
|
||||
#define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos)
|
||||
#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */
|
||||
#define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos)
|
||||
#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */
|
||||
#define DAC_INTENCLR_SYNCRDY (_U_(0x1) << DAC_INTENCLR_SYNCRDY_Pos)
|
||||
#define DAC_INTENCLR_MASK _U_(0x07) /**< \brief (DAC_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
|
||||
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
|
||||
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
|
||||
uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */
|
||||
#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */
|
||||
#define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos)
|
||||
#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */
|
||||
#define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos)
|
||||
#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */
|
||||
#define DAC_INTENSET_SYNCRDY (_U_(0x1) << DAC_INTENSET_SYNCRDY_Pos)
|
||||
#define DAC_INTENSET_MASK _U_(0x07) /**< \brief (DAC_INTENSET) MASK Register */
|
||||
|
||||
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
|
||||
__I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
|
||||
__I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
|
||||
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */
|
||||
#define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos)
|
||||
#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */
|
||||
#define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos)
|
||||
#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */
|
||||
#define DAC_INTFLAG_SYNCRDY (_U_(0x1) << DAC_INTFLAG_SYNCRDY_Pos)
|
||||
#define DAC_INTFLAG_MASK _U_(0x07) /**< \brief (DAC_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} DAC_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */
|
||||
#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */
|
||||
|
||||
#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */
|
||||
#define DAC_STATUS_SYNCBUSY (_U_(0x1) << DAC_STATUS_SYNCBUSY_Pos)
|
||||
#define DAC_STATUS_MASK _U_(0x80) /**< \brief (DAC_STATUS) MASK Register */
|
||||
|
||||
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} DAC_DATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */
|
||||
#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */
|
||||
|
||||
#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */
|
||||
#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos)
|
||||
#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))
|
||||
#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */
|
||||
|
||||
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} DAC_DATABUF_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */
|
||||
#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */
|
||||
|
||||
#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */
|
||||
#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos)
|
||||
#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))
|
||||
#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */
|
||||
|
||||
/** \brief DAC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
|
||||
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
|
||||
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
|
||||
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
|
||||
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
|
||||
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
|
||||
} Dac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_DAC_COMPONENT_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,298 +1,298 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for GCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_COMPONENT_
|
||||
#define _SAMD21_GCLK_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR GCLK */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_GCLK Generic Clock Generator */
|
||||
/*@{*/
|
||||
|
||||
#define GCLK_U2102
|
||||
#define REV_GCLK 0x210
|
||||
|
||||
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} GCLK_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
|
||||
#define GCLK_CTRL_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRL reset_value) Control */
|
||||
|
||||
#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
|
||||
#define GCLK_CTRL_SWRST (_U_(0x1) << GCLK_CTRL_SWRST_Pos)
|
||||
#define GCLK_CTRL_MASK _U_(0x01) /**< \brief (GCLK_CTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} GCLK_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
|
||||
#define GCLK_STATUS_RESETVALUE _U_(0x00) /**< \brief (GCLK_STATUS reset_value) Status */
|
||||
|
||||
#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
|
||||
#define GCLK_STATUS_SYNCBUSY (_U_(0x1) << GCLK_STATUS_SYNCBUSY_Pos)
|
||||
#define GCLK_STATUS_MASK _U_(0x80) /**< \brief (GCLK_STATUS) MASK Register */
|
||||
|
||||
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
|
||||
uint16_t :2; /*!< bit: 12..13 Reserved */
|
||||
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
|
||||
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} GCLK_CLKCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
|
||||
#define GCLK_CLKCTRL_RESETVALUE _U_(0x0000) /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
|
||||
|
||||
#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
|
||||
#define GCLK_CLKCTRL_ID_Msk (_U_(0x3F) << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
|
||||
#define GCLK_CLKCTRL_ID_DFLL48_Val _U_(0x0) /**< \brief (GCLK_CLKCTRL) DFLL48 */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL_Val _U_(0x1) /**< \brief (GCLK_CLKCTRL) FDPLL */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K_Val _U_(0x2) /**< \brief (GCLK_CLKCTRL) FDPLL32K */
|
||||
#define GCLK_CLKCTRL_ID_WDT_Val _U_(0x3) /**< \brief (GCLK_CLKCTRL) WDT */
|
||||
#define GCLK_CLKCTRL_ID_RTC_Val _U_(0x4) /**< \brief (GCLK_CLKCTRL) RTC */
|
||||
#define GCLK_CLKCTRL_ID_EIC_Val _U_(0x5) /**< \brief (GCLK_CLKCTRL) EIC */
|
||||
#define GCLK_CLKCTRL_ID_USB_Val _U_(0x6) /**< \brief (GCLK_CLKCTRL) USB */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_0_Val _U_(0x7) /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_1_Val _U_(0x8) /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_2_Val _U_(0x9) /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_3_Val _U_(0xA) /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4_Val _U_(0xB) /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5_Val _U_(0xC) /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6_Val _U_(0xD) /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7_Val _U_(0xE) /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8_Val _U_(0xF) /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9_Val _U_(0x10) /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10_Val _U_(0x11) /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11_Val _U_(0x12) /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val _U_(0x13) /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val _U_(0x14) /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val _U_(0x15) /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val _U_(0x16) /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val _U_(0x17) /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val _U_(0x18) /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val _U_(0x19) /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val _U_(0x1A) /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3_Val _U_(0x1B) /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5_Val _U_(0x1C) /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7_Val _U_(0x1D) /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
|
||||
#define GCLK_CLKCTRL_ID_ADC_Val _U_(0x1E) /**< \brief (GCLK_CLKCTRL) ADC */
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG_Val _U_(0x1F) /**< \brief (GCLK_CLKCTRL) AC_DIG */
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA_Val _U_(0x20) /**< \brief (GCLK_CLKCTRL) AC_ANA */
|
||||
#define GCLK_CLKCTRL_ID_DAC_Val _U_(0x21) /**< \brief (GCLK_CLKCTRL) DAC */
|
||||
#define GCLK_CLKCTRL_ID_PTC_Val _U_(0x22) /**< \brief (GCLK_CLKCTRL) PTC */
|
||||
#define GCLK_CLKCTRL_ID_I2S_0_Val _U_(0x23) /**< \brief (GCLK_CLKCTRL) I2S_0 */
|
||||
#define GCLK_CLKCTRL_ID_I2S_1_Val _U_(0x24) /**< \brief (GCLK_CLKCTRL) I2S_1 */
|
||||
#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
|
||||
#define GCLK_CLKCTRL_GEN_Msk (_U_(0xF) << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_CLKCTRL) Generic clock generator 8 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK8 (GCLK_CLKCTRL_GEN_GCLK8_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
|
||||
#define GCLK_CLKCTRL_CLKEN (_U_(0x1) << GCLK_CLKCTRL_CLKEN_Pos)
|
||||
#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
|
||||
#define GCLK_CLKCTRL_WRTLOCK (_U_(0x1) << GCLK_CLKCTRL_WRTLOCK_Pos)
|
||||
#define GCLK_CLKCTRL_MASK _U_(0xCF3F) /**< \brief (GCLK_CLKCTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
|
||||
uint32_t :3; /*!< bit: 13..15 Reserved */
|
||||
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
|
||||
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
|
||||
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
|
||||
uint32_t OE:1; /*!< bit: 19 Output Enable */
|
||||
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
|
||||
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
|
||||
uint32_t :10; /*!< bit: 22..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} GCLK_GENCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
|
||||
#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
|
||||
|
||||
#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
|
||||
#define GCLK_GENCTRL_ID_Msk (_U_(0xF) << GCLK_GENCTRL_ID_Pos)
|
||||
#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
|
||||
#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
|
||||
#define GCLK_GENCTRL_SRC_Msk (_U_(0x1F) << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
|
||||
#define GCLK_GENCTRL_SRC_XOSC_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) Generator input pad */
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
|
||||
#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_OSC32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_OSC8M_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_DFLL48M_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DFLL48M output */
|
||||
#define GCLK_GENCTRL_SRC_DPLL96M_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL96M output */
|
||||
#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
|
||||
#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
|
||||
#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
|
||||
#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
|
||||
#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
|
||||
#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
|
||||
#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
|
||||
#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
|
||||
#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
|
||||
#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
|
||||
#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
|
||||
#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
|
||||
#define GCLK_GENCTRL_MASK _U_(0x003F1F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
|
||||
uint32_t :8; /*!< bit: 24..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} GCLK_GENDIV_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
|
||||
#define GCLK_GENDIV_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
|
||||
|
||||
#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
|
||||
#define GCLK_GENDIV_ID_Msk (_U_(0xF) << GCLK_GENDIV_ID_Pos)
|
||||
#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
|
||||
#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
|
||||
#define GCLK_GENDIV_DIV_Msk (_U_(0xFFFF) << GCLK_GENDIV_DIV_Pos)
|
||||
#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
|
||||
#define GCLK_GENDIV_MASK _U_(0x00FFFF0F) /**< \brief (GCLK_GENDIV) MASK Register */
|
||||
|
||||
/** \brief GCLK hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
|
||||
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
|
||||
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
|
||||
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
|
||||
} Gclk;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_GCLK_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for GCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_COMPONENT_
|
||||
#define _SAMD21_GCLK_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR GCLK */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_GCLK Generic Clock Generator */
|
||||
/*@{*/
|
||||
|
||||
#define GCLK_U2102
|
||||
#define REV_GCLK 0x210
|
||||
|
||||
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} GCLK_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */
|
||||
#define GCLK_CTRL_RESETVALUE _U_(0x00) /**< \brief (GCLK_CTRL reset_value) Control */
|
||||
|
||||
#define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */
|
||||
#define GCLK_CTRL_SWRST (_U_(0x1) << GCLK_CTRL_SWRST_Pos)
|
||||
#define GCLK_CTRL_MASK _U_(0x01) /**< \brief (GCLK_CTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} GCLK_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */
|
||||
#define GCLK_STATUS_RESETVALUE _U_(0x00) /**< \brief (GCLK_STATUS reset_value) Status */
|
||||
|
||||
#define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */
|
||||
#define GCLK_STATUS_SYNCBUSY (_U_(0x1) << GCLK_STATUS_SYNCBUSY_Pos)
|
||||
#define GCLK_STATUS_MASK _U_(0x80) /**< \brief (GCLK_STATUS) MASK Register */
|
||||
|
||||
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
|
||||
uint16_t :2; /*!< bit: 6.. 7 Reserved */
|
||||
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
|
||||
uint16_t :2; /*!< bit: 12..13 Reserved */
|
||||
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
|
||||
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint16_t reg; /*!< Type used for register access */
|
||||
} GCLK_CLKCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */
|
||||
#define GCLK_CLKCTRL_RESETVALUE _U_(0x0000) /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */
|
||||
|
||||
#define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */
|
||||
#define GCLK_CLKCTRL_ID_Msk (_U_(0x3F) << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID(value) (GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))
|
||||
#define GCLK_CLKCTRL_ID_DFLL48_Val _U_(0x0) /**< \brief (GCLK_CLKCTRL) DFLL48 */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL_Val _U_(0x1) /**< \brief (GCLK_CLKCTRL) FDPLL */
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K_Val _U_(0x2) /**< \brief (GCLK_CLKCTRL) FDPLL32K */
|
||||
#define GCLK_CLKCTRL_ID_WDT_Val _U_(0x3) /**< \brief (GCLK_CLKCTRL) WDT */
|
||||
#define GCLK_CLKCTRL_ID_RTC_Val _U_(0x4) /**< \brief (GCLK_CLKCTRL) RTC */
|
||||
#define GCLK_CLKCTRL_ID_EIC_Val _U_(0x5) /**< \brief (GCLK_CLKCTRL) EIC */
|
||||
#define GCLK_CLKCTRL_ID_USB_Val _U_(0x6) /**< \brief (GCLK_CLKCTRL) USB */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_0_Val _U_(0x7) /**< \brief (GCLK_CLKCTRL) EVSYS_0 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_1_Val _U_(0x8) /**< \brief (GCLK_CLKCTRL) EVSYS_1 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_2_Val _U_(0x9) /**< \brief (GCLK_CLKCTRL) EVSYS_2 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_3_Val _U_(0xA) /**< \brief (GCLK_CLKCTRL) EVSYS_3 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4_Val _U_(0xB) /**< \brief (GCLK_CLKCTRL) EVSYS_4 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5_Val _U_(0xC) /**< \brief (GCLK_CLKCTRL) EVSYS_5 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6_Val _U_(0xD) /**< \brief (GCLK_CLKCTRL) EVSYS_6 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7_Val _U_(0xE) /**< \brief (GCLK_CLKCTRL) EVSYS_7 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8_Val _U_(0xF) /**< \brief (GCLK_CLKCTRL) EVSYS_8 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9_Val _U_(0x10) /**< \brief (GCLK_CLKCTRL) EVSYS_9 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10_Val _U_(0x11) /**< \brief (GCLK_CLKCTRL) EVSYS_10 */
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11_Val _U_(0x12) /**< \brief (GCLK_CLKCTRL) EVSYS_11 */
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val _U_(0x13) /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val _U_(0x14) /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val _U_(0x15) /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val _U_(0x16) /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val _U_(0x17) /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val _U_(0x18) /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val _U_(0x19) /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1_Val _U_(0x1A) /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3_Val _U_(0x1B) /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5_Val _U_(0x1C) /**< \brief (GCLK_CLKCTRL) TC4_TC5 */
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7_Val _U_(0x1D) /**< \brief (GCLK_CLKCTRL) TC6_TC7 */
|
||||
#define GCLK_CLKCTRL_ID_ADC_Val _U_(0x1E) /**< \brief (GCLK_CLKCTRL) ADC */
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG_Val _U_(0x1F) /**< \brief (GCLK_CLKCTRL) AC_DIG */
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA_Val _U_(0x20) /**< \brief (GCLK_CLKCTRL) AC_ANA */
|
||||
#define GCLK_CLKCTRL_ID_DAC_Val _U_(0x21) /**< \brief (GCLK_CLKCTRL) DAC */
|
||||
#define GCLK_CLKCTRL_ID_PTC_Val _U_(0x22) /**< \brief (GCLK_CLKCTRL) PTC */
|
||||
#define GCLK_CLKCTRL_ID_I2S_0_Val _U_(0x23) /**< \brief (GCLK_CLKCTRL) I2S_0 */
|
||||
#define GCLK_CLKCTRL_ID_I2S_1_Val _U_(0x24) /**< \brief (GCLK_CLKCTRL) I2S_1 */
|
||||
#define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */
|
||||
#define GCLK_CLKCTRL_GEN_Msk (_U_(0xF) << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN(value) (GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0_Val _U_(0x0) /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1_Val _U_(0x1) /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2_Val _U_(0x2) /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK3_Val _U_(0x3) /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK4_Val _U_(0x4) /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK5_Val _U_(0x5) /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK6_Val _U_(0x6) /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK7_Val _U_(0x7) /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK8_Val _U_(0x8) /**< \brief (GCLK_CLKCTRL) Generic clock generator 8 */
|
||||
#define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_GEN_GCLK8 (GCLK_CLKCTRL_GEN_GCLK8_Val << GCLK_CLKCTRL_GEN_Pos)
|
||||
#define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */
|
||||
#define GCLK_CLKCTRL_CLKEN (_U_(0x1) << GCLK_CLKCTRL_CLKEN_Pos)
|
||||
#define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */
|
||||
#define GCLK_CLKCTRL_WRTLOCK (_U_(0x1) << GCLK_CLKCTRL_WRTLOCK_Pos)
|
||||
#define GCLK_CLKCTRL_MASK _U_(0xCF3F) /**< \brief (GCLK_CLKCTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
|
||||
uint32_t :3; /*!< bit: 13..15 Reserved */
|
||||
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
|
||||
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
|
||||
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
|
||||
uint32_t OE:1; /*!< bit: 19 Output Enable */
|
||||
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
|
||||
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
|
||||
uint32_t :10; /*!< bit: 22..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} GCLK_GENCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
|
||||
#define GCLK_GENCTRL_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
|
||||
|
||||
#define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */
|
||||
#define GCLK_GENCTRL_ID_Msk (_U_(0xF) << GCLK_GENCTRL_ID_Pos)
|
||||
#define GCLK_GENCTRL_ID(value) (GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))
|
||||
#define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */
|
||||
#define GCLK_GENCTRL_SRC_Msk (_U_(0x1F) << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC(value) (GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))
|
||||
#define GCLK_GENCTRL_SRC_XOSC_Val _U_(0x0) /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN_Val _U_(0x1) /**< \brief (GCLK_GENCTRL) Generator input pad */
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1_Val _U_(0x2) /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
|
||||
#define GCLK_GENCTRL_SRC_OSCULP32K_Val _U_(0x3) /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_OSC32K_Val _U_(0x4) /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_XOSC32K_Val _U_(0x5) /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_OSC8M_Val _U_(0x6) /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */
|
||||
#define GCLK_GENCTRL_SRC_DFLL48M_Val _U_(0x7) /**< \brief (GCLK_GENCTRL) DFLL48M output */
|
||||
#define GCLK_GENCTRL_SRC_DPLL96M_Val _U_(0x8) /**< \brief (GCLK_GENCTRL) DPLL96M output */
|
||||
#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos)
|
||||
#define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
|
||||
#define GCLK_GENCTRL_GENEN (_U_(0x1) << GCLK_GENCTRL_GENEN_Pos)
|
||||
#define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
|
||||
#define GCLK_GENCTRL_IDC (_U_(0x1) << GCLK_GENCTRL_IDC_Pos)
|
||||
#define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */
|
||||
#define GCLK_GENCTRL_OOV (_U_(0x1) << GCLK_GENCTRL_OOV_Pos)
|
||||
#define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */
|
||||
#define GCLK_GENCTRL_OE (_U_(0x1) << GCLK_GENCTRL_OE_Pos)
|
||||
#define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */
|
||||
#define GCLK_GENCTRL_DIVSEL (_U_(0x1) << GCLK_GENCTRL_DIVSEL_Pos)
|
||||
#define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */
|
||||
#define GCLK_GENCTRL_RUNSTDBY (_U_(0x1) << GCLK_GENCTRL_RUNSTDBY_Pos)
|
||||
#define GCLK_GENCTRL_MASK _U_(0x003F1F0F) /**< \brief (GCLK_GENCTRL) MASK Register */
|
||||
|
||||
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
|
||||
uint32_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
|
||||
uint32_t :8; /*!< bit: 24..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} GCLK_GENDIV_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */
|
||||
#define GCLK_GENDIV_RESETVALUE _U_(0x00000000) /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */
|
||||
|
||||
#define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */
|
||||
#define GCLK_GENDIV_ID_Msk (_U_(0xF) << GCLK_GENDIV_ID_Pos)
|
||||
#define GCLK_GENDIV_ID(value) (GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))
|
||||
#define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */
|
||||
#define GCLK_GENDIV_DIV_Msk (_U_(0xFFFF) << GCLK_GENDIV_DIV_Pos)
|
||||
#define GCLK_GENDIV_DIV(value) (GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))
|
||||
#define GCLK_GENDIV_MASK _U_(0x00FFFF0F) /**< \brief (GCLK_GENDIV) MASK Register */
|
||||
|
||||
/** \brief GCLK hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
|
||||
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
|
||||
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
|
||||
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
|
||||
} Gclk;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_GCLK_COMPONENT_ */
|
||||
|
||||
@@ -1,104 +1,104 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for HMATRIXB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_HMATRIXB_COMPONENT_
|
||||
#define _SAMD21_HMATRIXB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR HMATRIXB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
|
||||
/*@{*/
|
||||
|
||||
#define HMATRIXB_I7638
|
||||
#define REV_HMATRIXB 0x212
|
||||
|
||||
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_PRAS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
|
||||
#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
|
||||
|
||||
#define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
|
||||
|
||||
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_PRBS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
|
||||
#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
|
||||
|
||||
#define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
|
||||
|
||||
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_SFR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
|
||||
#define HMATRIXB_SFR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
|
||||
|
||||
#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
|
||||
#define HMATRIXB_SFR_SFR_Msk (_U_(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
|
||||
#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
|
||||
#define HMATRIXB_SFR_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
|
||||
|
||||
/** \brief HmatrixbPrs hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
|
||||
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
|
||||
} HmatrixbPrs;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/** \brief HMATRIXB hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
RoReg8 Reserved1[0x80];
|
||||
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
|
||||
RoReg8 Reserved2[0x10];
|
||||
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
|
||||
} Hmatrixb;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for HMATRIXB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_HMATRIXB_COMPONENT_
|
||||
#define _SAMD21_HMATRIXB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR HMATRIXB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_HMATRIXB HSB Matrix */
|
||||
/*@{*/
|
||||
|
||||
#define HMATRIXB_I7638
|
||||
#define REV_HMATRIXB 0x212
|
||||
|
||||
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_PRAS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define HMATRIXB_PRAS_OFFSET 0x080 /**< \brief (HMATRIXB_PRAS offset) Priority A for Slave */
|
||||
#define HMATRIXB_PRAS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRAS reset_value) Priority A for Slave */
|
||||
|
||||
#define HMATRIXB_PRAS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRAS) MASK Register */
|
||||
|
||||
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_PRBS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define HMATRIXB_PRBS_OFFSET 0x084 /**< \brief (HMATRIXB_PRBS offset) Priority B for Slave */
|
||||
#define HMATRIXB_PRBS_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_PRBS reset_value) Priority B for Slave */
|
||||
|
||||
#define HMATRIXB_PRBS_MASK _U_(0x00000000) /**< \brief (HMATRIXB_PRBS) MASK Register */
|
||||
|
||||
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} HMATRIXB_SFR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define HMATRIXB_SFR_OFFSET 0x110 /**< \brief (HMATRIXB_SFR offset) Special Function */
|
||||
#define HMATRIXB_SFR_RESETVALUE _U_(0x00000000) /**< \brief (HMATRIXB_SFR reset_value) Special Function */
|
||||
|
||||
#define HMATRIXB_SFR_SFR_Pos 0 /**< \brief (HMATRIXB_SFR) Special Function Register */
|
||||
#define HMATRIXB_SFR_SFR_Msk (_U_(0xFFFFFFFF) << HMATRIXB_SFR_SFR_Pos)
|
||||
#define HMATRIXB_SFR_SFR(value) (HMATRIXB_SFR_SFR_Msk & ((value) << HMATRIXB_SFR_SFR_Pos))
|
||||
#define HMATRIXB_SFR_MASK _U_(0xFFFFFFFF) /**< \brief (HMATRIXB_SFR) MASK Register */
|
||||
|
||||
/** \brief HmatrixbPrs hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
|
||||
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
|
||||
} HmatrixbPrs;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/** \brief HMATRIXB hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
RoReg8 Reserved1[0x80];
|
||||
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
|
||||
RoReg8 Reserved2[0x10];
|
||||
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
|
||||
} Hmatrixb;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_HMATRIXB_COMPONENT_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,382 +1,382 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for MTB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_COMPONENT_
|
||||
#define _SAMD21_MTB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR MTB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
|
||||
/*@{*/
|
||||
|
||||
#define MTB_U2002
|
||||
#define REV_MTB 0x100
|
||||
|
||||
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
|
||||
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_POSITION_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
|
||||
|
||||
#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
|
||||
#define MTB_POSITION_WRAP (_U_(0x1) << MTB_POSITION_WRAP_Pos)
|
||||
#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
|
||||
#define MTB_POSITION_POINTER_Msk (_U_(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos)
|
||||
#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
|
||||
#define MTB_POSITION_MASK _U_(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */
|
||||
|
||||
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
|
||||
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
|
||||
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
|
||||
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
|
||||
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
|
||||
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
|
||||
uint32_t :21; /*!< bit: 10..30 Reserved */
|
||||
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_MASTER_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
|
||||
#define MTB_MASTER_RESETVALUE _U_(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */
|
||||
|
||||
#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
|
||||
#define MTB_MASTER_MASK_Msk (_U_(0x1F) << MTB_MASTER_MASK_Pos)
|
||||
#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
|
||||
#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
|
||||
#define MTB_MASTER_TSTARTEN (_U_(0x1) << MTB_MASTER_TSTARTEN_Pos)
|
||||
#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
|
||||
#define MTB_MASTER_TSTOPEN (_U_(0x1) << MTB_MASTER_TSTOPEN_Pos)
|
||||
#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
|
||||
#define MTB_MASTER_SFRWPRIV (_U_(0x1) << MTB_MASTER_SFRWPRIV_Pos)
|
||||
#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
|
||||
#define MTB_MASTER_RAMPRIV (_U_(0x1) << MTB_MASTER_RAMPRIV_Pos)
|
||||
#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
|
||||
#define MTB_MASTER_HALTREQ (_U_(0x1) << MTB_MASTER_HALTREQ_Pos)
|
||||
#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
|
||||
#define MTB_MASTER_EN (_U_(0x1) << MTB_MASTER_EN_Pos)
|
||||
#define MTB_MASTER_MASK_ _U_(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */
|
||||
|
||||
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
|
||||
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
|
||||
uint32_t :1; /*!< bit: 2 Reserved */
|
||||
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_FLOW_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
|
||||
#define MTB_FLOW_RESETVALUE _U_(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */
|
||||
|
||||
#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
|
||||
#define MTB_FLOW_AUTOSTOP (_U_(0x1) << MTB_FLOW_AUTOSTOP_Pos)
|
||||
#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
|
||||
#define MTB_FLOW_AUTOHALT (_U_(0x1) << MTB_FLOW_AUTOHALT_Pos)
|
||||
#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
|
||||
#define MTB_FLOW_WATERMARK_Msk (_U_(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos)
|
||||
#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
|
||||
#define MTB_FLOW_MASK _U_(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */
|
||||
|
||||
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_BASE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
|
||||
#define MTB_BASE_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */
|
||||
|
||||
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_ITCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
|
||||
#define MTB_ITCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */
|
||||
|
||||
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CLAIMSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
|
||||
#define MTB_CLAIMSET_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */
|
||||
|
||||
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CLAIMCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
|
||||
#define MTB_CLAIMCLR_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */
|
||||
|
||||
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_LOCKACCESS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
|
||||
#define MTB_LOCKACCESS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */
|
||||
|
||||
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_LOCKSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
|
||||
#define MTB_LOCKSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */
|
||||
|
||||
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_AUTHSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
|
||||
#define MTB_AUTHSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */
|
||||
|
||||
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_DEVARCH_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
|
||||
#define MTB_DEVARCH_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */
|
||||
|
||||
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_DEVID_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
|
||||
#define MTB_DEVID_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */
|
||||
|
||||
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_DEVTYPE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
|
||||
#define MTB_DEVTYPE_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */
|
||||
|
||||
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID4_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
|
||||
#define MTB_PID4_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */
|
||||
|
||||
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID5_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
|
||||
#define MTB_PID5_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */
|
||||
|
||||
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID6_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
|
||||
#define MTB_PID6_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */
|
||||
|
||||
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID7_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
|
||||
#define MTB_PID7_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */
|
||||
|
||||
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
|
||||
#define MTB_PID0_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */
|
||||
|
||||
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
|
||||
#define MTB_PID1_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */
|
||||
|
||||
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID2_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
|
||||
#define MTB_PID2_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */
|
||||
|
||||
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID3_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
|
||||
#define MTB_PID3_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */
|
||||
|
||||
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
|
||||
#define MTB_CID0_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */
|
||||
|
||||
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
|
||||
#define MTB_CID1_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */
|
||||
|
||||
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID2_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
|
||||
#define MTB_CID2_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */
|
||||
|
||||
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID3_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
|
||||
#define MTB_CID3_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */
|
||||
|
||||
/** \brief MTB hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
|
||||
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
|
||||
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
|
||||
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
|
||||
RoReg8 Reserved1[0xEF0];
|
||||
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
|
||||
RoReg8 Reserved2[0x9C];
|
||||
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
|
||||
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
|
||||
RoReg8 Reserved3[0x8];
|
||||
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
|
||||
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
|
||||
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
|
||||
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
|
||||
RoReg8 Reserved4[0x8];
|
||||
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
|
||||
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
|
||||
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
|
||||
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
|
||||
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
|
||||
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
|
||||
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
|
||||
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
|
||||
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
|
||||
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
|
||||
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
|
||||
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
|
||||
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
|
||||
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
|
||||
} Mtb;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_MTB_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for MTB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_COMPONENT_
|
||||
#define _SAMD21_MTB_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR MTB */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */
|
||||
/*@{*/
|
||||
|
||||
#define MTB_U2002
|
||||
#define REV_MTB 0x100
|
||||
|
||||
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :2; /*!< bit: 0.. 1 Reserved */
|
||||
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
|
||||
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_POSITION_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
|
||||
|
||||
#define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
|
||||
#define MTB_POSITION_WRAP (_U_(0x1) << MTB_POSITION_WRAP_Pos)
|
||||
#define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
|
||||
#define MTB_POSITION_POINTER_Msk (_U_(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos)
|
||||
#define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
|
||||
#define MTB_POSITION_MASK _U_(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */
|
||||
|
||||
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
|
||||
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
|
||||
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
|
||||
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
|
||||
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
|
||||
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
|
||||
uint32_t :21; /*!< bit: 10..30 Reserved */
|
||||
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_MASTER_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
|
||||
#define MTB_MASTER_RESETVALUE _U_(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */
|
||||
|
||||
#define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
|
||||
#define MTB_MASTER_MASK_Msk (_U_(0x1F) << MTB_MASTER_MASK_Pos)
|
||||
#define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
|
||||
#define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
|
||||
#define MTB_MASTER_TSTARTEN (_U_(0x1) << MTB_MASTER_TSTARTEN_Pos)
|
||||
#define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
|
||||
#define MTB_MASTER_TSTOPEN (_U_(0x1) << MTB_MASTER_TSTOPEN_Pos)
|
||||
#define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
|
||||
#define MTB_MASTER_SFRWPRIV (_U_(0x1) << MTB_MASTER_SFRWPRIV_Pos)
|
||||
#define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
|
||||
#define MTB_MASTER_RAMPRIV (_U_(0x1) << MTB_MASTER_RAMPRIV_Pos)
|
||||
#define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
|
||||
#define MTB_MASTER_HALTREQ (_U_(0x1) << MTB_MASTER_HALTREQ_Pos)
|
||||
#define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
|
||||
#define MTB_MASTER_EN (_U_(0x1) << MTB_MASTER_EN_Pos)
|
||||
#define MTB_MASTER_MASK_ _U_(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */
|
||||
|
||||
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
|
||||
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
|
||||
uint32_t :1; /*!< bit: 2 Reserved */
|
||||
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_FLOW_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
|
||||
#define MTB_FLOW_RESETVALUE _U_(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */
|
||||
|
||||
#define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
|
||||
#define MTB_FLOW_AUTOSTOP (_U_(0x1) << MTB_FLOW_AUTOSTOP_Pos)
|
||||
#define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
|
||||
#define MTB_FLOW_AUTOHALT (_U_(0x1) << MTB_FLOW_AUTOHALT_Pos)
|
||||
#define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
|
||||
#define MTB_FLOW_WATERMARK_Msk (_U_(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos)
|
||||
#define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
|
||||
#define MTB_FLOW_MASK _U_(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */
|
||||
|
||||
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_BASE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
|
||||
#define MTB_BASE_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */
|
||||
|
||||
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_ITCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
|
||||
#define MTB_ITCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */
|
||||
|
||||
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CLAIMSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
|
||||
#define MTB_CLAIMSET_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */
|
||||
|
||||
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CLAIMCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
|
||||
#define MTB_CLAIMCLR_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */
|
||||
|
||||
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_LOCKACCESS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
|
||||
#define MTB_LOCKACCESS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */
|
||||
|
||||
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_LOCKSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
|
||||
#define MTB_LOCKSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */
|
||||
|
||||
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_AUTHSTATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
|
||||
#define MTB_AUTHSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */
|
||||
|
||||
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_DEVARCH_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
|
||||
#define MTB_DEVARCH_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */
|
||||
|
||||
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_DEVID_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
|
||||
#define MTB_DEVID_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */
|
||||
|
||||
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_DEVTYPE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
|
||||
#define MTB_DEVTYPE_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */
|
||||
|
||||
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID4_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
|
||||
#define MTB_PID4_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */
|
||||
|
||||
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID5_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
|
||||
#define MTB_PID5_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */
|
||||
|
||||
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID6_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
|
||||
#define MTB_PID6_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */
|
||||
|
||||
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID7_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
|
||||
#define MTB_PID7_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */
|
||||
|
||||
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
|
||||
#define MTB_PID0_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */
|
||||
|
||||
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
|
||||
#define MTB_PID1_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */
|
||||
|
||||
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID2_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
|
||||
#define MTB_PID2_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */
|
||||
|
||||
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_PID3_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
|
||||
#define MTB_PID3_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */
|
||||
|
||||
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
|
||||
#define MTB_CID0_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */
|
||||
|
||||
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
|
||||
#define MTB_CID1_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */
|
||||
|
||||
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID2_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
|
||||
#define MTB_CID2_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */
|
||||
|
||||
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} MTB_CID3_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
|
||||
#define MTB_CID3_MASK _U_(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */
|
||||
|
||||
/** \brief MTB hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
|
||||
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
|
||||
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
|
||||
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
|
||||
RoReg8 Reserved1[0xEF0];
|
||||
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
|
||||
RoReg8 Reserved2[0x9C];
|
||||
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
|
||||
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
|
||||
RoReg8 Reserved3[0x8];
|
||||
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
|
||||
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
|
||||
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
|
||||
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
|
||||
RoReg8 Reserved4[0x8];
|
||||
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
|
||||
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
|
||||
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
|
||||
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
|
||||
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
|
||||
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
|
||||
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
|
||||
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
|
||||
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
|
||||
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
|
||||
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
|
||||
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
|
||||
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
|
||||
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
|
||||
} Mtb;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_MTB_COMPONENT_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,90 +1,90 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for PAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC_COMPONENT_
|
||||
#define _SAMD21_PAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PAC Peripheral Access Controller */
|
||||
/*@{*/
|
||||
|
||||
#define PAC_U2211
|
||||
#define REV_PAC 0x101
|
||||
|
||||
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PAC_WPCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
|
||||
#define PAC_WPCLR_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
|
||||
|
||||
#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
|
||||
#define PAC_WPCLR_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPCLR_WP_Pos)
|
||||
#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
|
||||
#define PAC_WPCLR_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */
|
||||
|
||||
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PAC_WPSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
|
||||
#define PAC_WPSET_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */
|
||||
|
||||
#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
|
||||
#define PAC_WPSET_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPSET_WP_Pos)
|
||||
#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
|
||||
#define PAC_WPSET_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */
|
||||
|
||||
/** \brief PAC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
|
||||
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
|
||||
} Pac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PAC_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for PAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC_COMPONENT_
|
||||
#define _SAMD21_PAC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PAC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PAC Peripheral Access Controller */
|
||||
/*@{*/
|
||||
|
||||
#define PAC_U2211
|
||||
#define REV_PAC 0x101
|
||||
|
||||
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PAC_WPCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PAC_WPCLR_OFFSET 0x0 /**< \brief (PAC_WPCLR offset) Write Protection Clear */
|
||||
#define PAC_WPCLR_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPCLR reset_value) Write Protection Clear */
|
||||
|
||||
#define PAC_WPCLR_WP_Pos 1 /**< \brief (PAC_WPCLR) Write Protection Clear */
|
||||
#define PAC_WPCLR_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPCLR_WP_Pos)
|
||||
#define PAC_WPCLR_WP(value) (PAC_WPCLR_WP_Msk & ((value) << PAC_WPCLR_WP_Pos))
|
||||
#define PAC_WPCLR_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPCLR) MASK Register */
|
||||
|
||||
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PAC_WPSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PAC_WPSET_OFFSET 0x4 /**< \brief (PAC_WPSET offset) Write Protection Set */
|
||||
#define PAC_WPSET_RESETVALUE _U_(0x00000000) /**< \brief (PAC_WPSET reset_value) Write Protection Set */
|
||||
|
||||
#define PAC_WPSET_WP_Pos 1 /**< \brief (PAC_WPSET) Write Protection Set */
|
||||
#define PAC_WPSET_WP_Msk (_U_(0x7FFFFFFF) << PAC_WPSET_WP_Pos)
|
||||
#define PAC_WPSET_WP(value) (PAC_WPSET_WP_Msk & ((value) << PAC_WPSET_WP_Pos))
|
||||
#define PAC_WPSET_MASK _U_(0xFFFFFFFE) /**< \brief (PAC_WPSET) MASK Register */
|
||||
|
||||
/** \brief PAC hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
|
||||
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
|
||||
} Pac;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PAC_COMPONENT_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,380 +1,380 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for PORT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_COMPONENT_
|
||||
#define _SAMD21_PORT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PORT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PORT Port Module */
|
||||
/*@{*/
|
||||
|
||||
#define PORT_U2210
|
||||
#define REV_PORT 0x100
|
||||
|
||||
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
|
||||
#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
|
||||
|
||||
#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
|
||||
#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
|
||||
#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
|
||||
#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIRCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
|
||||
#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
|
||||
|
||||
#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
|
||||
#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
|
||||
#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
|
||||
#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIRSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
|
||||
#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
|
||||
|
||||
#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
|
||||
#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
|
||||
#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
|
||||
#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIRTGL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
|
||||
#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
|
||||
|
||||
#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
|
||||
#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
|
||||
#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
|
||||
#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
|
||||
#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
|
||||
|
||||
#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
|
||||
#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
|
||||
#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
|
||||
#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUTCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
|
||||
#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
|
||||
|
||||
#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
|
||||
#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
|
||||
#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
|
||||
#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUTSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
|
||||
#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
|
||||
|
||||
#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
|
||||
#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
|
||||
#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
|
||||
#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUTTGL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
|
||||
#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
|
||||
|
||||
#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
|
||||
#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
|
||||
#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
|
||||
#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_IN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
|
||||
#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
|
||||
|
||||
#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
|
||||
#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
|
||||
#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
|
||||
#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
|
||||
|
||||
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
|
||||
#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
|
||||
|
||||
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
|
||||
#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
|
||||
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
|
||||
#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
|
||||
|
||||
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
|
||||
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
|
||||
uint32_t INEN:1; /*!< bit: 17 Input Enable */
|
||||
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
|
||||
uint32_t :3; /*!< bit: 19..21 Reserved */
|
||||
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
|
||||
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
|
||||
uint32_t :1; /*!< bit: 29 Reserved */
|
||||
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
|
||||
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_WRCONFIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
|
||||
#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
|
||||
|
||||
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
|
||||
#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
|
||||
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
|
||||
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
|
||||
#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
|
||||
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
|
||||
#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
|
||||
#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
|
||||
#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
|
||||
#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
|
||||
#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
|
||||
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
|
||||
#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
|
||||
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
|
||||
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
|
||||
#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
|
||||
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
|
||||
#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
|
||||
#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
|
||||
#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
|
||||
#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
|
||||
|
||||
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
|
||||
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PORT_PMUX_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
|
||||
#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
|
||||
|
||||
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
|
||||
#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
|
||||
#define PORT_PMUX_PMUXE_A_Val _U_(0x0) /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXE_B_Val _U_(0x1) /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXE_C_Val _U_(0x2) /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
#define PORT_PMUX_PMUXE_D_Val _U_(0x3) /**< \brief (PORT_PMUX) Peripheral function D selected */
|
||||
#define PORT_PMUX_PMUXE_E_Val _U_(0x4) /**< \brief (PORT_PMUX) Peripheral function E selected */
|
||||
#define PORT_PMUX_PMUXE_F_Val _U_(0x5) /**< \brief (PORT_PMUX) Peripheral function F selected */
|
||||
#define PORT_PMUX_PMUXE_G_Val _U_(0x6) /**< \brief (PORT_PMUX) Peripheral function G selected */
|
||||
#define PORT_PMUX_PMUXE_H_Val _U_(0x7) /**< \brief (PORT_PMUX) Peripheral function H selected */
|
||||
#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
|
||||
#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
|
||||
#define PORT_PMUX_PMUXO_A_Val _U_(0x0) /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXO_B_Val _U_(0x1) /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXO_C_Val _U_(0x2) /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
#define PORT_PMUX_PMUXO_D_Val _U_(0x3) /**< \brief (PORT_PMUX) Peripheral function D selected */
|
||||
#define PORT_PMUX_PMUXO_E_Val _U_(0x4) /**< \brief (PORT_PMUX) Peripheral function E selected */
|
||||
#define PORT_PMUX_PMUXO_F_Val _U_(0x5) /**< \brief (PORT_PMUX) Peripheral function F selected */
|
||||
#define PORT_PMUX_PMUXO_G_Val _U_(0x6) /**< \brief (PORT_PMUX) Peripheral function G selected */
|
||||
#define PORT_PMUX_PMUXO_H_Val _U_(0x7) /**< \brief (PORT_PMUX) Peripheral function H selected */
|
||||
#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
|
||||
|
||||
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
|
||||
uint8_t INEN:1; /*!< bit: 1 Input Enable */
|
||||
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
|
||||
uint8_t :3; /*!< bit: 3.. 5 Reserved */
|
||||
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PORT_PINCFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
|
||||
#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
|
||||
|
||||
#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
|
||||
#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
|
||||
#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
|
||||
#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
|
||||
#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
|
||||
#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
|
||||
#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
|
||||
#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
|
||||
#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
|
||||
|
||||
/** \brief PortGroup hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
|
||||
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
|
||||
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
|
||||
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
|
||||
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
|
||||
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
|
||||
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
|
||||
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
|
||||
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
|
||||
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
|
||||
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
|
||||
RoReg8 Reserved1[0x4];
|
||||
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
|
||||
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
|
||||
RoReg8 Reserved2[0x20];
|
||||
} PortGroup;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/** \brief PORT hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
|
||||
} Port;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PORT_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for PORT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_COMPONENT_
|
||||
#define _SAMD21_PORT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR PORT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_PORT Port Module */
|
||||
/*@{*/
|
||||
|
||||
#define PORT_U2210
|
||||
#define REV_PORT 0x100
|
||||
|
||||
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIR_OFFSET 0x00 /**< \brief (PORT_DIR offset) Data Direction */
|
||||
#define PORT_DIR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIR reset_value) Data Direction */
|
||||
|
||||
#define PORT_DIR_DIR_Pos 0 /**< \brief (PORT_DIR) Port Data Direction */
|
||||
#define PORT_DIR_DIR_Msk (_U_(0xFFFFFFFF) << PORT_DIR_DIR_Pos)
|
||||
#define PORT_DIR_DIR(value) (PORT_DIR_DIR_Msk & ((value) << PORT_DIR_DIR_Pos))
|
||||
#define PORT_DIR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIRCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIRCLR_OFFSET 0x04 /**< \brief (PORT_DIRCLR offset) Data Direction Clear */
|
||||
#define PORT_DIRCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRCLR reset_value) Data Direction Clear */
|
||||
|
||||
#define PORT_DIRCLR_DIRCLR_Pos 0 /**< \brief (PORT_DIRCLR) Port Data Direction Clear */
|
||||
#define PORT_DIRCLR_DIRCLR_Msk (_U_(0xFFFFFFFF) << PORT_DIRCLR_DIRCLR_Pos)
|
||||
#define PORT_DIRCLR_DIRCLR(value) (PORT_DIRCLR_DIRCLR_Msk & ((value) << PORT_DIRCLR_DIRCLR_Pos))
|
||||
#define PORT_DIRCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIRSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIRSET_OFFSET 0x08 /**< \brief (PORT_DIRSET offset) Data Direction Set */
|
||||
#define PORT_DIRSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRSET reset_value) Data Direction Set */
|
||||
|
||||
#define PORT_DIRSET_DIRSET_Pos 0 /**< \brief (PORT_DIRSET) Port Data Direction Set */
|
||||
#define PORT_DIRSET_DIRSET_Msk (_U_(0xFFFFFFFF) << PORT_DIRSET_DIRSET_Pos)
|
||||
#define PORT_DIRSET_DIRSET(value) (PORT_DIRSET_DIRSET_Msk & ((value) << PORT_DIRSET_DIRSET_Pos))
|
||||
#define PORT_DIRSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRSET) MASK Register */
|
||||
|
||||
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_DIRTGL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_DIRTGL_OFFSET 0x0C /**< \brief (PORT_DIRTGL offset) Data Direction Toggle */
|
||||
#define PORT_DIRTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_DIRTGL reset_value) Data Direction Toggle */
|
||||
|
||||
#define PORT_DIRTGL_DIRTGL_Pos 0 /**< \brief (PORT_DIRTGL) Port Data Direction Toggle */
|
||||
#define PORT_DIRTGL_DIRTGL_Msk (_U_(0xFFFFFFFF) << PORT_DIRTGL_DIRTGL_Pos)
|
||||
#define PORT_DIRTGL_DIRTGL(value) (PORT_DIRTGL_DIRTGL_Msk & ((value) << PORT_DIRTGL_DIRTGL_Pos))
|
||||
#define PORT_DIRTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_DIRTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUT_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUT_OFFSET 0x10 /**< \brief (PORT_OUT offset) Data Output Value */
|
||||
#define PORT_OUT_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUT reset_value) Data Output Value */
|
||||
|
||||
#define PORT_OUT_OUT_Pos 0 /**< \brief (PORT_OUT) Port Data Output Value */
|
||||
#define PORT_OUT_OUT_Msk (_U_(0xFFFFFFFF) << PORT_OUT_OUT_Pos)
|
||||
#define PORT_OUT_OUT(value) (PORT_OUT_OUT_Msk & ((value) << PORT_OUT_OUT_Pos))
|
||||
#define PORT_OUT_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUT) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUTCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUTCLR_OFFSET 0x14 /**< \brief (PORT_OUTCLR offset) Data Output Value Clear */
|
||||
#define PORT_OUTCLR_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTCLR reset_value) Data Output Value Clear */
|
||||
|
||||
#define PORT_OUTCLR_OUTCLR_Pos 0 /**< \brief (PORT_OUTCLR) Port Data Output Value Clear */
|
||||
#define PORT_OUTCLR_OUTCLR_Msk (_U_(0xFFFFFFFF) << PORT_OUTCLR_OUTCLR_Pos)
|
||||
#define PORT_OUTCLR_OUTCLR(value) (PORT_OUTCLR_OUTCLR_Msk & ((value) << PORT_OUTCLR_OUTCLR_Pos))
|
||||
#define PORT_OUTCLR_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTCLR) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUTSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUTSET_OFFSET 0x18 /**< \brief (PORT_OUTSET offset) Data Output Value Set */
|
||||
#define PORT_OUTSET_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTSET reset_value) Data Output Value Set */
|
||||
|
||||
#define PORT_OUTSET_OUTSET_Pos 0 /**< \brief (PORT_OUTSET) Port Data Output Value Set */
|
||||
#define PORT_OUTSET_OUTSET_Msk (_U_(0xFFFFFFFF) << PORT_OUTSET_OUTSET_Pos)
|
||||
#define PORT_OUTSET_OUTSET(value) (PORT_OUTSET_OUTSET_Msk & ((value) << PORT_OUTSET_OUTSET_Pos))
|
||||
#define PORT_OUTSET_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTSET) MASK Register */
|
||||
|
||||
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_OUTTGL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_OUTTGL_OFFSET 0x1C /**< \brief (PORT_OUTTGL offset) Data Output Value Toggle */
|
||||
#define PORT_OUTTGL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_OUTTGL reset_value) Data Output Value Toggle */
|
||||
|
||||
#define PORT_OUTTGL_OUTTGL_Pos 0 /**< \brief (PORT_OUTTGL) Port Data Output Value Toggle */
|
||||
#define PORT_OUTTGL_OUTTGL_Msk (_U_(0xFFFFFFFF) << PORT_OUTTGL_OUTTGL_Pos)
|
||||
#define PORT_OUTTGL_OUTTGL(value) (PORT_OUTTGL_OUTTGL_Msk & ((value) << PORT_OUTTGL_OUTTGL_Pos))
|
||||
#define PORT_OUTTGL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_OUTTGL) MASK Register */
|
||||
|
||||
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_IN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_IN_OFFSET 0x20 /**< \brief (PORT_IN offset) Data Input Value */
|
||||
#define PORT_IN_RESETVALUE _U_(0x00000000) /**< \brief (PORT_IN reset_value) Data Input Value */
|
||||
|
||||
#define PORT_IN_IN_Pos 0 /**< \brief (PORT_IN) Port Data Input Value */
|
||||
#define PORT_IN_IN_Msk (_U_(0xFFFFFFFF) << PORT_IN_IN_Pos)
|
||||
#define PORT_IN_IN(value) (PORT_IN_IN_Msk & ((value) << PORT_IN_IN_Pos))
|
||||
#define PORT_IN_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_IN) MASK Register */
|
||||
|
||||
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_CTRL_OFFSET 0x24 /**< \brief (PORT_CTRL offset) Control */
|
||||
#define PORT_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (PORT_CTRL reset_value) Control */
|
||||
|
||||
#define PORT_CTRL_SAMPLING_Pos 0 /**< \brief (PORT_CTRL) Input Sampling Mode */
|
||||
#define PORT_CTRL_SAMPLING_Msk (_U_(0xFFFFFFFF) << PORT_CTRL_SAMPLING_Pos)
|
||||
#define PORT_CTRL_SAMPLING(value) (PORT_CTRL_SAMPLING_Msk & ((value) << PORT_CTRL_SAMPLING_Pos))
|
||||
#define PORT_CTRL_MASK _U_(0xFFFFFFFF) /**< \brief (PORT_CTRL) MASK Register */
|
||||
|
||||
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
|
||||
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
|
||||
uint32_t INEN:1; /*!< bit: 17 Input Enable */
|
||||
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
|
||||
uint32_t :3; /*!< bit: 19..21 Reserved */
|
||||
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
|
||||
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
|
||||
uint32_t :1; /*!< bit: 29 Reserved */
|
||||
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
|
||||
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} PORT_WRCONFIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_WRCONFIG_OFFSET 0x28 /**< \brief (PORT_WRCONFIG offset) Write Configuration */
|
||||
#define PORT_WRCONFIG_RESETVALUE _U_(0x00000000) /**< \brief (PORT_WRCONFIG reset_value) Write Configuration */
|
||||
|
||||
#define PORT_WRCONFIG_PINMASK_Pos 0 /**< \brief (PORT_WRCONFIG) Pin Mask for Multiple Pin Configuration */
|
||||
#define PORT_WRCONFIG_PINMASK_Msk (_U_(0xFFFF) << PORT_WRCONFIG_PINMASK_Pos)
|
||||
#define PORT_WRCONFIG_PINMASK(value) (PORT_WRCONFIG_PINMASK_Msk & ((value) << PORT_WRCONFIG_PINMASK_Pos))
|
||||
#define PORT_WRCONFIG_PMUXEN_Pos 16 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexer Enable */
|
||||
#define PORT_WRCONFIG_PMUXEN (_U_(0x1) << PORT_WRCONFIG_PMUXEN_Pos)
|
||||
#define PORT_WRCONFIG_INEN_Pos 17 /**< \brief (PORT_WRCONFIG) Input Enable */
|
||||
#define PORT_WRCONFIG_INEN (_U_(0x1) << PORT_WRCONFIG_INEN_Pos)
|
||||
#define PORT_WRCONFIG_PULLEN_Pos 18 /**< \brief (PORT_WRCONFIG) Pull Enable */
|
||||
#define PORT_WRCONFIG_PULLEN (_U_(0x1) << PORT_WRCONFIG_PULLEN_Pos)
|
||||
#define PORT_WRCONFIG_DRVSTR_Pos 22 /**< \brief (PORT_WRCONFIG) Output Driver Strength Selection */
|
||||
#define PORT_WRCONFIG_DRVSTR (_U_(0x1) << PORT_WRCONFIG_DRVSTR_Pos)
|
||||
#define PORT_WRCONFIG_PMUX_Pos 24 /**< \brief (PORT_WRCONFIG) Peripheral Multiplexing */
|
||||
#define PORT_WRCONFIG_PMUX_Msk (_U_(0xF) << PORT_WRCONFIG_PMUX_Pos)
|
||||
#define PORT_WRCONFIG_PMUX(value) (PORT_WRCONFIG_PMUX_Msk & ((value) << PORT_WRCONFIG_PMUX_Pos))
|
||||
#define PORT_WRCONFIG_WRPMUX_Pos 28 /**< \brief (PORT_WRCONFIG) Write PMUX */
|
||||
#define PORT_WRCONFIG_WRPMUX (_U_(0x1) << PORT_WRCONFIG_WRPMUX_Pos)
|
||||
#define PORT_WRCONFIG_WRPINCFG_Pos 30 /**< \brief (PORT_WRCONFIG) Write PINCFG */
|
||||
#define PORT_WRCONFIG_WRPINCFG (_U_(0x1) << PORT_WRCONFIG_WRPINCFG_Pos)
|
||||
#define PORT_WRCONFIG_HWSEL_Pos 31 /**< \brief (PORT_WRCONFIG) Half-Word Select */
|
||||
#define PORT_WRCONFIG_HWSEL (_U_(0x1) << PORT_WRCONFIG_HWSEL_Pos)
|
||||
#define PORT_WRCONFIG_MASK _U_(0xDF47FFFF) /**< \brief (PORT_WRCONFIG) MASK Register */
|
||||
|
||||
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
|
||||
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PORT_PMUX_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_PMUX_OFFSET 0x30 /**< \brief (PORT_PMUX offset) Peripheral Multiplexing n */
|
||||
#define PORT_PMUX_RESETVALUE _U_(0x00) /**< \brief (PORT_PMUX reset_value) Peripheral Multiplexing n */
|
||||
|
||||
#define PORT_PMUX_PMUXE_Pos 0 /**< \brief (PORT_PMUX) Peripheral Multiplexing Even */
|
||||
#define PORT_PMUX_PMUXE_Msk (_U_(0xF) << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE(value) (PORT_PMUX_PMUXE_Msk & ((value) << PORT_PMUX_PMUXE_Pos))
|
||||
#define PORT_PMUX_PMUXE_A_Val _U_(0x0) /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXE_B_Val _U_(0x1) /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXE_C_Val _U_(0x2) /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
#define PORT_PMUX_PMUXE_D_Val _U_(0x3) /**< \brief (PORT_PMUX) Peripheral function D selected */
|
||||
#define PORT_PMUX_PMUXE_E_Val _U_(0x4) /**< \brief (PORT_PMUX) Peripheral function E selected */
|
||||
#define PORT_PMUX_PMUXE_F_Val _U_(0x5) /**< \brief (PORT_PMUX) Peripheral function F selected */
|
||||
#define PORT_PMUX_PMUXE_G_Val _U_(0x6) /**< \brief (PORT_PMUX) Peripheral function G selected */
|
||||
#define PORT_PMUX_PMUXE_H_Val _U_(0x7) /**< \brief (PORT_PMUX) Peripheral function H selected */
|
||||
#define PORT_PMUX_PMUXE_A (PORT_PMUX_PMUXE_A_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_B (PORT_PMUX_PMUXE_B_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_C (PORT_PMUX_PMUXE_C_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_D (PORT_PMUX_PMUXE_D_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_E (PORT_PMUX_PMUXE_E_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_F (PORT_PMUX_PMUXE_F_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_G (PORT_PMUX_PMUXE_G_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXE_H (PORT_PMUX_PMUXE_H_Val << PORT_PMUX_PMUXE_Pos)
|
||||
#define PORT_PMUX_PMUXO_Pos 4 /**< \brief (PORT_PMUX) Peripheral Multiplexing Odd */
|
||||
#define PORT_PMUX_PMUXO_Msk (_U_(0xF) << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO(value) (PORT_PMUX_PMUXO_Msk & ((value) << PORT_PMUX_PMUXO_Pos))
|
||||
#define PORT_PMUX_PMUXO_A_Val _U_(0x0) /**< \brief (PORT_PMUX) Peripheral function A selected */
|
||||
#define PORT_PMUX_PMUXO_B_Val _U_(0x1) /**< \brief (PORT_PMUX) Peripheral function B selected */
|
||||
#define PORT_PMUX_PMUXO_C_Val _U_(0x2) /**< \brief (PORT_PMUX) Peripheral function C selected */
|
||||
#define PORT_PMUX_PMUXO_D_Val _U_(0x3) /**< \brief (PORT_PMUX) Peripheral function D selected */
|
||||
#define PORT_PMUX_PMUXO_E_Val _U_(0x4) /**< \brief (PORT_PMUX) Peripheral function E selected */
|
||||
#define PORT_PMUX_PMUXO_F_Val _U_(0x5) /**< \brief (PORT_PMUX) Peripheral function F selected */
|
||||
#define PORT_PMUX_PMUXO_G_Val _U_(0x6) /**< \brief (PORT_PMUX) Peripheral function G selected */
|
||||
#define PORT_PMUX_PMUXO_H_Val _U_(0x7) /**< \brief (PORT_PMUX) Peripheral function H selected */
|
||||
#define PORT_PMUX_PMUXO_A (PORT_PMUX_PMUXO_A_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_B (PORT_PMUX_PMUXO_B_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_C (PORT_PMUX_PMUXO_C_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_D (PORT_PMUX_PMUXO_D_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_E (PORT_PMUX_PMUXO_E_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_F (PORT_PMUX_PMUXO_F_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_G (PORT_PMUX_PMUXO_G_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_PMUXO_H (PORT_PMUX_PMUXO_H_Val << PORT_PMUX_PMUXO_Pos)
|
||||
#define PORT_PMUX_MASK _U_(0xFF) /**< \brief (PORT_PMUX) MASK Register */
|
||||
|
||||
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
|
||||
uint8_t INEN:1; /*!< bit: 1 Input Enable */
|
||||
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
|
||||
uint8_t :3; /*!< bit: 3.. 5 Reserved */
|
||||
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} PORT_PINCFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define PORT_PINCFG_OFFSET 0x40 /**< \brief (PORT_PINCFG offset) Pin Configuration n */
|
||||
#define PORT_PINCFG_RESETVALUE _U_(0x00) /**< \brief (PORT_PINCFG reset_value) Pin Configuration n */
|
||||
|
||||
#define PORT_PINCFG_PMUXEN_Pos 0 /**< \brief (PORT_PINCFG) Peripheral Multiplexer Enable */
|
||||
#define PORT_PINCFG_PMUXEN (_U_(0x1) << PORT_PINCFG_PMUXEN_Pos)
|
||||
#define PORT_PINCFG_INEN_Pos 1 /**< \brief (PORT_PINCFG) Input Enable */
|
||||
#define PORT_PINCFG_INEN (_U_(0x1) << PORT_PINCFG_INEN_Pos)
|
||||
#define PORT_PINCFG_PULLEN_Pos 2 /**< \brief (PORT_PINCFG) Pull Enable */
|
||||
#define PORT_PINCFG_PULLEN (_U_(0x1) << PORT_PINCFG_PULLEN_Pos)
|
||||
#define PORT_PINCFG_DRVSTR_Pos 6 /**< \brief (PORT_PINCFG) Output Driver Strength Selection */
|
||||
#define PORT_PINCFG_DRVSTR (_U_(0x1) << PORT_PINCFG_DRVSTR_Pos)
|
||||
#define PORT_PINCFG_MASK _U_(0x47) /**< \brief (PORT_PINCFG) MASK Register */
|
||||
|
||||
/** \brief PortGroup hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
|
||||
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
|
||||
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
|
||||
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
|
||||
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
|
||||
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
|
||||
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
|
||||
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
|
||||
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
|
||||
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
|
||||
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
|
||||
RoReg8 Reserved1[0x4];
|
||||
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
|
||||
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
|
||||
RoReg8 Reserved2[0x20];
|
||||
} PortGroup;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/** \brief PORT hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
|
||||
} Port;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_PORT_COMPONENT_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,289 +1,289 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for WDT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_COMPONENT_
|
||||
#define _SAMD21_WDT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR WDT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_WDT Watchdog Timer */
|
||||
/*@{*/
|
||||
|
||||
#define WDT_U2203
|
||||
#define REV_WDT 0x200
|
||||
|
||||
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :1; /*!< bit: 0 Reserved */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
|
||||
uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
|
||||
#define WDT_CTRL_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRL reset_value) Control */
|
||||
|
||||
#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
|
||||
#define WDT_CTRL_ENABLE (_U_(0x1) << WDT_CTRL_ENABLE_Pos)
|
||||
#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
|
||||
#define WDT_CTRL_WEN (_U_(0x1) << WDT_CTRL_WEN_Pos)
|
||||
#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
|
||||
#define WDT_CTRL_ALWAYSON (_U_(0x1) << WDT_CTRL_ALWAYSON_Pos)
|
||||
#define WDT_CTRL_MASK _U_(0x86) /**< \brief (WDT_CTRL) MASK Register */
|
||||
|
||||
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
|
||||
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_CONFIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
|
||||
#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
|
||||
|
||||
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
|
||||
#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
|
||||
#define WDT_CONFIG_PER_8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_PER_16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_PER_32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
#define WDT_CONFIG_PER_64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
|
||||
#define WDT_CONFIG_PER_128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
|
||||
#define WDT_CONFIG_PER_256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
|
||||
#define WDT_CONFIG_PER_512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
|
||||
#define WDT_CONFIG_PER_1K_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
|
||||
#define WDT_CONFIG_PER_2K_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
|
||||
#define WDT_CONFIG_PER_4K_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
|
||||
#define WDT_CONFIG_PER_8K_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
|
||||
#define WDT_CONFIG_PER_16K_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
|
||||
#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
|
||||
#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
|
||||
#define WDT_CONFIG_WINDOW_8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_1K_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_2K_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_4K_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_8K_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_16K_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
|
||||
|
||||
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_EWCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
|
||||
#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
|
||||
|
||||
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
|
||||
#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
|
||||
#define WDT_EWCTRL_EWOFFSET_8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_1K_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_2K_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_4K_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_8K_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_16K_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
|
||||
|
||||
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
|
||||
#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
|
||||
#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
|
||||
#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
|
||||
#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
|
||||
#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
|
||||
|
||||
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t EW:1; /*!< bit: 0 Early Warning */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
|
||||
#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
|
||||
#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
|
||||
#define WDT_STATUS_RESETVALUE _U_(0x00) /**< \brief (WDT_STATUS reset_value) Status */
|
||||
|
||||
#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
|
||||
#define WDT_STATUS_SYNCBUSY (_U_(0x1) << WDT_STATUS_SYNCBUSY_Pos)
|
||||
#define WDT_STATUS_MASK _U_(0x80) /**< \brief (WDT_STATUS) MASK Register */
|
||||
|
||||
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_CLEAR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
|
||||
#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
|
||||
|
||||
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
|
||||
#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
|
||||
#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
|
||||
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
|
||||
|
||||
/** \brief WDT hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
|
||||
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
|
||||
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
|
||||
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
|
||||
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
|
||||
} Wdt;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_WDT_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for WDT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_COMPONENT_
|
||||
#define _SAMD21_WDT_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR WDT */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD21_WDT Watchdog Timer */
|
||||
/*@{*/
|
||||
|
||||
#define WDT_U2203
|
||||
#define REV_WDT 0x200
|
||||
|
||||
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :1; /*!< bit: 0 Reserved */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
|
||||
uint8_t :4; /*!< bit: 3.. 6 Reserved */
|
||||
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
|
||||
#define WDT_CTRL_RESETVALUE _U_(0x00) /**< \brief (WDT_CTRL reset_value) Control */
|
||||
|
||||
#define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
|
||||
#define WDT_CTRL_ENABLE (_U_(0x1) << WDT_CTRL_ENABLE_Pos)
|
||||
#define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
|
||||
#define WDT_CTRL_WEN (_U_(0x1) << WDT_CTRL_WEN_Pos)
|
||||
#define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
|
||||
#define WDT_CTRL_ALWAYSON (_U_(0x1) << WDT_CTRL_ALWAYSON_Pos)
|
||||
#define WDT_CTRL_MASK _U_(0x86) /**< \brief (WDT_CTRL) MASK Register */
|
||||
|
||||
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
|
||||
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_CONFIG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
|
||||
#define WDT_CONFIG_RESETVALUE _U_(0xBB) /**< \brief (WDT_CONFIG reset_value) Configuration */
|
||||
|
||||
#define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
|
||||
#define WDT_CONFIG_PER_Msk (_U_(0xF) << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
|
||||
#define WDT_CONFIG_PER_8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_PER_16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_PER_32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
#define WDT_CONFIG_PER_64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
|
||||
#define WDT_CONFIG_PER_128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
|
||||
#define WDT_CONFIG_PER_256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
|
||||
#define WDT_CONFIG_PER_512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
|
||||
#define WDT_CONFIG_PER_1K_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
|
||||
#define WDT_CONFIG_PER_2K_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
|
||||
#define WDT_CONFIG_PER_4K_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
|
||||
#define WDT_CONFIG_PER_8K_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
|
||||
#define WDT_CONFIG_PER_16K_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
|
||||
#define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
|
||||
#define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
|
||||
#define WDT_CONFIG_WINDOW_Msk (_U_(0xF) << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
|
||||
#define WDT_CONFIG_WINDOW_8_Val _U_(0x0) /**< \brief (WDT_CONFIG) 8 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_16_Val _U_(0x1) /**< \brief (WDT_CONFIG) 16 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_32_Val _U_(0x2) /**< \brief (WDT_CONFIG) 32 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_64_Val _U_(0x3) /**< \brief (WDT_CONFIG) 64 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_128_Val _U_(0x4) /**< \brief (WDT_CONFIG) 128 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_256_Val _U_(0x5) /**< \brief (WDT_CONFIG) 256 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_512_Val _U_(0x6) /**< \brief (WDT_CONFIG) 512 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_1K_Val _U_(0x7) /**< \brief (WDT_CONFIG) 1024 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_2K_Val _U_(0x8) /**< \brief (WDT_CONFIG) 2048 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_4K_Val _U_(0x9) /**< \brief (WDT_CONFIG) 4096 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_8K_Val _U_(0xA) /**< \brief (WDT_CONFIG) 8192 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_16K_Val _U_(0xB) /**< \brief (WDT_CONFIG) 16384 clock cycles */
|
||||
#define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos)
|
||||
#define WDT_CONFIG_MASK _U_(0xFF) /**< \brief (WDT_CONFIG) MASK Register */
|
||||
|
||||
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_EWCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
|
||||
#define WDT_EWCTRL_RESETVALUE _U_(0x0B) /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
|
||||
|
||||
#define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
|
||||
#define WDT_EWCTRL_EWOFFSET_Msk (_U_(0xF) << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
|
||||
#define WDT_EWCTRL_EWOFFSET_8_Val _U_(0x0) /**< \brief (WDT_EWCTRL) 8 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_16_Val _U_(0x1) /**< \brief (WDT_EWCTRL) 16 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_32_Val _U_(0x2) /**< \brief (WDT_EWCTRL) 32 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_64_Val _U_(0x3) /**< \brief (WDT_EWCTRL) 64 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_128_Val _U_(0x4) /**< \brief (WDT_EWCTRL) 128 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_256_Val _U_(0x5) /**< \brief (WDT_EWCTRL) 256 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_512_Val _U_(0x6) /**< \brief (WDT_EWCTRL) 512 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_1K_Val _U_(0x7) /**< \brief (WDT_EWCTRL) 1024 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_2K_Val _U_(0x8) /**< \brief (WDT_EWCTRL) 2048 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_4K_Val _U_(0x9) /**< \brief (WDT_EWCTRL) 4096 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_8K_Val _U_(0xA) /**< \brief (WDT_EWCTRL) 8192 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_16K_Val _U_(0xB) /**< \brief (WDT_EWCTRL) 16384 clock cycles */
|
||||
#define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos)
|
||||
#define WDT_EWCTRL_MASK _U_(0x0F) /**< \brief (WDT_EWCTRL) MASK Register */
|
||||
|
||||
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define WDT_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
|
||||
#define WDT_INTENCLR_EW (_U_(0x1) << WDT_INTENCLR_EW_Pos)
|
||||
#define WDT_INTENCLR_MASK _U_(0x01) /**< \brief (WDT_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
|
||||
#define WDT_INTENSET_RESETVALUE _U_(0x00) /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
|
||||
#define WDT_INTENSET_EW (_U_(0x1) << WDT_INTENSET_EW_Pos)
|
||||
#define WDT_INTENSET_MASK _U_(0x01) /**< \brief (WDT_INTENSET) MASK Register */
|
||||
|
||||
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t EW:1; /*!< bit: 0 Early Warning */
|
||||
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
|
||||
#define WDT_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
|
||||
|
||||
#define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
|
||||
#define WDT_INTFLAG_EW (_U_(0x1) << WDT_INTFLAG_EW_Pos)
|
||||
#define WDT_INTFLAG_MASK _U_(0x01) /**< \brief (WDT_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t :7; /*!< bit: 0.. 6 Reserved */
|
||||
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_STATUS_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
|
||||
#define WDT_STATUS_RESETVALUE _U_(0x00) /**< \brief (WDT_STATUS reset_value) Status */
|
||||
|
||||
#define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
|
||||
#define WDT_STATUS_SYNCBUSY (_U_(0x1) << WDT_STATUS_SYNCBUSY_Pos)
|
||||
#define WDT_STATUS_MASK _U_(0x80) /**< \brief (WDT_STATUS) MASK Register */
|
||||
|
||||
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} WDT_CLEAR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
|
||||
#define WDT_CLEAR_RESETVALUE _U_(0x00) /**< \brief (WDT_CLEAR reset_value) Clear */
|
||||
|
||||
#define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
|
||||
#define WDT_CLEAR_CLEAR_Msk (_U_(0xFF) << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
|
||||
#define WDT_CLEAR_CLEAR_KEY_Val _U_(0xA5) /**< \brief (WDT_CLEAR) Clear Key */
|
||||
#define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
|
||||
#define WDT_CLEAR_MASK _U_(0xFF) /**< \brief (WDT_CLEAR) MASK Register */
|
||||
|
||||
/** \brief WDT hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
|
||||
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
|
||||
RoReg8 Reserved1[0x1];
|
||||
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
|
||||
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
|
||||
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
|
||||
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
|
||||
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
|
||||
} Wdt;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD21_WDT_COMPONENT_ */
|
||||
|
||||
@@ -1,73 +1,73 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for AC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC_INSTANCE_
|
||||
#define _SAMD21_AC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for AC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_AC_CTRLA (0x42004400) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (0x42004401) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (0x42004402) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (0x42004404) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (0x42004405) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (0x42004408) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (0x42004409) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (0x4200440A) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (0x4200440C) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (0x42004410) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (0x42004414) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (0x42004420) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (0x42004421) /**< \brief (AC) Scaler 1 */
|
||||
#else
|
||||
#define REG_AC_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for AC peripheral ========== */
|
||||
#define AC_CMP_NUM 2 // Number of comparators
|
||||
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
|
||||
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
|
||||
#define AC_NUM_CMP 2
|
||||
#define AC_PAIRS 1 // Number of pairs of comparators
|
||||
|
||||
#endif /* _SAMD21_AC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for AC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_AC_INSTANCE_
|
||||
#define _SAMD21_AC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for AC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_AC_CTRLA (0x42004400) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (0x42004401) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (0x42004402) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (0x42004404) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (0x42004405) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (0x42004406) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (0x42004408) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (0x42004409) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (0x4200440A) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (0x4200440C) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (0x42004410) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (0x42004414) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (0x42004420) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (0x42004421) /**< \brief (AC) Scaler 1 */
|
||||
#else
|
||||
#define REG_AC_CTRLA (*(RwReg8 *)0x42004400UL) /**< \brief (AC) Control A */
|
||||
#define REG_AC_CTRLB (*(WoReg8 *)0x42004401UL) /**< \brief (AC) Control B */
|
||||
#define REG_AC_EVCTRL (*(RwReg16*)0x42004402UL) /**< \brief (AC) Event Control */
|
||||
#define REG_AC_INTENCLR (*(RwReg8 *)0x42004404UL) /**< \brief (AC) Interrupt Enable Clear */
|
||||
#define REG_AC_INTENSET (*(RwReg8 *)0x42004405UL) /**< \brief (AC) Interrupt Enable Set */
|
||||
#define REG_AC_INTFLAG (*(RwReg8 *)0x42004406UL) /**< \brief (AC) Interrupt Flag Status and Clear */
|
||||
#define REG_AC_STATUSA (*(RoReg8 *)0x42004408UL) /**< \brief (AC) Status A */
|
||||
#define REG_AC_STATUSB (*(RoReg8 *)0x42004409UL) /**< \brief (AC) Status B */
|
||||
#define REG_AC_STATUSC (*(RoReg8 *)0x4200440AUL) /**< \brief (AC) Status C */
|
||||
#define REG_AC_WINCTRL (*(RwReg8 *)0x4200440CUL) /**< \brief (AC) Window Control */
|
||||
#define REG_AC_COMPCTRL0 (*(RwReg *)0x42004410UL) /**< \brief (AC) Comparator Control 0 */
|
||||
#define REG_AC_COMPCTRL1 (*(RwReg *)0x42004414UL) /**< \brief (AC) Comparator Control 1 */
|
||||
#define REG_AC_SCALER0 (*(RwReg8 *)0x42004420UL) /**< \brief (AC) Scaler 0 */
|
||||
#define REG_AC_SCALER1 (*(RwReg8 *)0x42004421UL) /**< \brief (AC) Scaler 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for AC peripheral ========== */
|
||||
#define AC_CMP_NUM 2 // Number of comparators
|
||||
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
|
||||
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
|
||||
#define AC_NUM_CMP 2
|
||||
#define AC_PAIRS 1 // Number of pairs of comparators
|
||||
|
||||
#endif /* _SAMD21_AC_INSTANCE_ */
|
||||
|
||||
@@ -1,85 +1,85 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for ADC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_INSTANCE_
|
||||
#define _SAMD21_ADC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_ADC_CTRLA (0x42004000) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (0x42004001) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (0x42004002) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (0x42004003) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (0x42004004) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (0x42004008) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (0x4200400C) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (0x42004010) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (0x42004014) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (0x42004016) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (0x42004017) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (0x42004018) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (0x42004019) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (0x4200401A) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (0x4200401C) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (0x42004020) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (0x42004024) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (0x42004026) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (0x42004028) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (0x4200402A) /**< \brief (ADC) Debug Control */
|
||||
#else
|
||||
#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000UL) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001UL) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002UL) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003UL) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (*(RwReg16*)0x42004004UL) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008UL) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CUL) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010UL) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014UL) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016UL) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017UL) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018UL) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (*(RoReg8 *)0x42004019UL) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (*(RoReg16*)0x4200401AUL) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (*(RwReg16*)0x4200401CUL) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (*(RwReg16*)0x42004020UL) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024UL) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026UL) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (*(RwReg16*)0x42004028UL) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AUL) /**< \brief (ADC) Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for ADC peripheral ========== */
|
||||
#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger
|
||||
#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
|
||||
#define ADC_GCLK_ID 30 // Index of Generic Clock
|
||||
#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield
|
||||
#define ADC_RESULT_MSB 15 // Size of Result
|
||||
|
||||
#endif /* _SAMD21_ADC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for ADC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_ADC_INSTANCE_
|
||||
#define _SAMD21_ADC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for ADC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_ADC_CTRLA (0x42004000) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (0x42004001) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (0x42004002) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (0x42004003) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (0x42004004) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (0x42004008) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (0x4200400C) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (0x42004010) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (0x42004014) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (0x42004016) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (0x42004017) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (0x42004018) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (0x42004019) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (0x4200401A) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (0x4200401C) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (0x42004020) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (0x42004024) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (0x42004026) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (0x42004028) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (0x4200402A) /**< \brief (ADC) Debug Control */
|
||||
#else
|
||||
#define REG_ADC_CTRLA (*(RwReg8 *)0x42004000UL) /**< \brief (ADC) Control A */
|
||||
#define REG_ADC_REFCTRL (*(RwReg8 *)0x42004001UL) /**< \brief (ADC) Reference Control */
|
||||
#define REG_ADC_AVGCTRL (*(RwReg8 *)0x42004002UL) /**< \brief (ADC) Average Control */
|
||||
#define REG_ADC_SAMPCTRL (*(RwReg8 *)0x42004003UL) /**< \brief (ADC) Sampling Time Control */
|
||||
#define REG_ADC_CTRLB (*(RwReg16*)0x42004004UL) /**< \brief (ADC) Control B */
|
||||
#define REG_ADC_WINCTRL (*(RwReg8 *)0x42004008UL) /**< \brief (ADC) Window Monitor Control */
|
||||
#define REG_ADC_SWTRIG (*(RwReg8 *)0x4200400CUL) /**< \brief (ADC) Software Trigger */
|
||||
#define REG_ADC_INPUTCTRL (*(RwReg *)0x42004010UL) /**< \brief (ADC) Input Control */
|
||||
#define REG_ADC_EVCTRL (*(RwReg8 *)0x42004014UL) /**< \brief (ADC) Event Control */
|
||||
#define REG_ADC_INTENCLR (*(RwReg8 *)0x42004016UL) /**< \brief (ADC) Interrupt Enable Clear */
|
||||
#define REG_ADC_INTENSET (*(RwReg8 *)0x42004017UL) /**< \brief (ADC) Interrupt Enable Set */
|
||||
#define REG_ADC_INTFLAG (*(RwReg8 *)0x42004018UL) /**< \brief (ADC) Interrupt Flag Status and Clear */
|
||||
#define REG_ADC_STATUS (*(RoReg8 *)0x42004019UL) /**< \brief (ADC) Status */
|
||||
#define REG_ADC_RESULT (*(RoReg16*)0x4200401AUL) /**< \brief (ADC) Result */
|
||||
#define REG_ADC_WINLT (*(RwReg16*)0x4200401CUL) /**< \brief (ADC) Window Monitor Lower Threshold */
|
||||
#define REG_ADC_WINUT (*(RwReg16*)0x42004020UL) /**< \brief (ADC) Window Monitor Upper Threshold */
|
||||
#define REG_ADC_GAINCORR (*(RwReg16*)0x42004024UL) /**< \brief (ADC) Gain Correction */
|
||||
#define REG_ADC_OFFSETCORR (*(RwReg16*)0x42004026UL) /**< \brief (ADC) Offset Correction */
|
||||
#define REG_ADC_CALIB (*(RwReg16*)0x42004028UL) /**< \brief (ADC) Calibration */
|
||||
#define REG_ADC_DBGCTRL (*(RwReg8 *)0x4200402AUL) /**< \brief (ADC) Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for ADC peripheral ========== */
|
||||
#define ADC_DMAC_ID_RESRDY 39 // Index of DMA RESRDY trigger
|
||||
#define ADC_EXTCHANNEL_MSB 19 // Number of external channels
|
||||
#define ADC_GCLK_ID 30 // Index of Generic Clock
|
||||
#define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield
|
||||
#define ADC_RESULT_MSB 15 // Size of Result
|
||||
|
||||
#endif /* _SAMD21_ADC_INSTANCE_ */
|
||||
|
||||
@@ -1,60 +1,60 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_INSTANCE_
|
||||
#define _SAMD21_DAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DAC_CTRLA (0x42004800) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (0x42004801) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (0x42004802) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (0x42004804) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (0x42004805) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (0x42004806) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (0x42004807) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (0x42004808) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (0x4200480C) /**< \brief (DAC) Data Buffer */
|
||||
#else
|
||||
#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (*(RoReg8 *)0x42004807UL) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (*(RwReg16*)0x42004808UL) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CUL) /**< \brief (DAC) Data Buffer */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DAC peripheral ========== */
|
||||
#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger
|
||||
#define DAC_GCLK_ID 33 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_DAC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DAC_INSTANCE_
|
||||
#define _SAMD21_DAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DAC_CTRLA (0x42004800) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (0x42004801) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (0x42004802) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (0x42004804) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (0x42004805) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (0x42004806) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (0x42004807) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (0x42004808) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (0x4200480C) /**< \brief (DAC) Data Buffer */
|
||||
#else
|
||||
#define REG_DAC_CTRLA (*(RwReg8 *)0x42004800UL) /**< \brief (DAC) Control A */
|
||||
#define REG_DAC_CTRLB (*(RwReg8 *)0x42004801UL) /**< \brief (DAC) Control B */
|
||||
#define REG_DAC_EVCTRL (*(RwReg8 *)0x42004802UL) /**< \brief (DAC) Event Control */
|
||||
#define REG_DAC_INTENCLR (*(RwReg8 *)0x42004804UL) /**< \brief (DAC) Interrupt Enable Clear */
|
||||
#define REG_DAC_INTENSET (*(RwReg8 *)0x42004805UL) /**< \brief (DAC) Interrupt Enable Set */
|
||||
#define REG_DAC_INTFLAG (*(RwReg8 *)0x42004806UL) /**< \brief (DAC) Interrupt Flag Status and Clear */
|
||||
#define REG_DAC_STATUS (*(RoReg8 *)0x42004807UL) /**< \brief (DAC) Status */
|
||||
#define REG_DAC_DATA (*(RwReg16*)0x42004808UL) /**< \brief (DAC) Data */
|
||||
#define REG_DAC_DATABUF (*(RwReg16*)0x4200480CUL) /**< \brief (DAC) Data Buffer */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DAC peripheral ========== */
|
||||
#define DAC_DMAC_ID_EMPTY 40 // Index of DMAC EMPTY trigger
|
||||
#define DAC_GCLK_ID 33 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_DAC_INSTANCE_ */
|
||||
|
||||
@@ -1,95 +1,95 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DMAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DMAC_INSTANCE_
|
||||
#define _SAMD21_DMAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DMAC_CTRL (0x41004800) /**< \brief (DMAC) Control */
|
||||
#define REG_DMAC_CRCCTRL (0x41004802) /**< \brief (DMAC) CRC Control */
|
||||
#define REG_DMAC_CRCDATAIN (0x41004804) /**< \brief (DMAC) CRC Data Input */
|
||||
#define REG_DMAC_CRCCHKSUM (0x41004808) /**< \brief (DMAC) CRC Checksum */
|
||||
#define REG_DMAC_CRCSTATUS (0x4100480C) /**< \brief (DMAC) CRC Status */
|
||||
#define REG_DMAC_DBGCTRL (0x4100480D) /**< \brief (DMAC) Debug Control */
|
||||
#define REG_DMAC_QOSCTRL (0x4100480E) /**< \brief (DMAC) QOS Control */
|
||||
#define REG_DMAC_SWTRIGCTRL (0x41004810) /**< \brief (DMAC) Software Trigger Control */
|
||||
#define REG_DMAC_PRICTRL0 (0x41004814) /**< \brief (DMAC) Priority Control 0 */
|
||||
#define REG_DMAC_INTPEND (0x41004820) /**< \brief (DMAC) Interrupt Pending */
|
||||
#define REG_DMAC_INTSTATUS (0x41004824) /**< \brief (DMAC) Interrupt Status */
|
||||
#define REG_DMAC_BUSYCH (0x41004828) /**< \brief (DMAC) Busy Channels */
|
||||
#define REG_DMAC_PENDCH (0x4100482C) /**< \brief (DMAC) Pending Channels */
|
||||
#define REG_DMAC_ACTIVE (0x41004830) /**< \brief (DMAC) Active Channel and Levels */
|
||||
#define REG_DMAC_BASEADDR (0x41004834) /**< \brief (DMAC) Descriptor Memory Section Base Address */
|
||||
#define REG_DMAC_WRBADDR (0x41004838) /**< \brief (DMAC) Write-Back Memory Section Base Address */
|
||||
#define REG_DMAC_CHID (0x4100483F) /**< \brief (DMAC) Channel ID */
|
||||
#define REG_DMAC_CHCTRLA (0x41004840) /**< \brief (DMAC) Channel Control A */
|
||||
#define REG_DMAC_CHCTRLB (0x41004844) /**< \brief (DMAC) Channel Control B */
|
||||
#define REG_DMAC_CHINTENCLR (0x4100484C) /**< \brief (DMAC) Channel Interrupt Enable Clear */
|
||||
#define REG_DMAC_CHINTENSET (0x4100484D) /**< \brief (DMAC) Channel Interrupt Enable Set */
|
||||
#define REG_DMAC_CHINTFLAG (0x4100484E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
|
||||
#define REG_DMAC_CHSTATUS (0x4100484F) /**< \brief (DMAC) Channel Status */
|
||||
#else
|
||||
#define REG_DMAC_CTRL (*(RwReg16*)0x41004800UL) /**< \brief (DMAC) Control */
|
||||
#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802UL) /**< \brief (DMAC) CRC Control */
|
||||
#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804UL) /**< \brief (DMAC) CRC Data Input */
|
||||
#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808UL) /**< \brief (DMAC) CRC Checksum */
|
||||
#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CUL) /**< \brief (DMAC) CRC Status */
|
||||
#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DUL) /**< \brief (DMAC) Debug Control */
|
||||
#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EUL) /**< \brief (DMAC) QOS Control */
|
||||
#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810UL) /**< \brief (DMAC) Software Trigger Control */
|
||||
#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814UL) /**< \brief (DMAC) Priority Control 0 */
|
||||
#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820UL) /**< \brief (DMAC) Interrupt Pending */
|
||||
#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824UL) /**< \brief (DMAC) Interrupt Status */
|
||||
#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828UL) /**< \brief (DMAC) Busy Channels */
|
||||
#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CUL) /**< \brief (DMAC) Pending Channels */
|
||||
#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830UL) /**< \brief (DMAC) Active Channel and Levels */
|
||||
#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
|
||||
#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
|
||||
#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FUL) /**< \brief (DMAC) Channel ID */
|
||||
#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840UL) /**< \brief (DMAC) Channel Control A */
|
||||
#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844UL) /**< \brief (DMAC) Channel Control B */
|
||||
#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */
|
||||
#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */
|
||||
#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
|
||||
#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FUL) /**< \brief (DMAC) Channel Status */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DMAC peripheral ========== */
|
||||
#define DMAC_CH_BITS 4 // Number of bits to select channel
|
||||
#define DMAC_CH_NUM 12 // Number of channels
|
||||
#define DMAC_CLK_AHB_ID 5 // AHB clock index
|
||||
#define DMAC_EVIN_NUM 4 // Number of input events
|
||||
#define DMAC_EVOUT_NUM 4 // Number of output events
|
||||
#define DMAC_LVL_BITS 2 // Number of bit to select level priority
|
||||
#define DMAC_LVL_NUM 4 // Enable priority level number
|
||||
#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
|
||||
#define DMAC_TRIG_NUM 45 // Number of peripheral triggers
|
||||
|
||||
#endif /* _SAMD21_DMAC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DMAC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DMAC_INSTANCE_
|
||||
#define _SAMD21_DMAC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DMAC_CTRL (0x41004800) /**< \brief (DMAC) Control */
|
||||
#define REG_DMAC_CRCCTRL (0x41004802) /**< \brief (DMAC) CRC Control */
|
||||
#define REG_DMAC_CRCDATAIN (0x41004804) /**< \brief (DMAC) CRC Data Input */
|
||||
#define REG_DMAC_CRCCHKSUM (0x41004808) /**< \brief (DMAC) CRC Checksum */
|
||||
#define REG_DMAC_CRCSTATUS (0x4100480C) /**< \brief (DMAC) CRC Status */
|
||||
#define REG_DMAC_DBGCTRL (0x4100480D) /**< \brief (DMAC) Debug Control */
|
||||
#define REG_DMAC_QOSCTRL (0x4100480E) /**< \brief (DMAC) QOS Control */
|
||||
#define REG_DMAC_SWTRIGCTRL (0x41004810) /**< \brief (DMAC) Software Trigger Control */
|
||||
#define REG_DMAC_PRICTRL0 (0x41004814) /**< \brief (DMAC) Priority Control 0 */
|
||||
#define REG_DMAC_INTPEND (0x41004820) /**< \brief (DMAC) Interrupt Pending */
|
||||
#define REG_DMAC_INTSTATUS (0x41004824) /**< \brief (DMAC) Interrupt Status */
|
||||
#define REG_DMAC_BUSYCH (0x41004828) /**< \brief (DMAC) Busy Channels */
|
||||
#define REG_DMAC_PENDCH (0x4100482C) /**< \brief (DMAC) Pending Channels */
|
||||
#define REG_DMAC_ACTIVE (0x41004830) /**< \brief (DMAC) Active Channel and Levels */
|
||||
#define REG_DMAC_BASEADDR (0x41004834) /**< \brief (DMAC) Descriptor Memory Section Base Address */
|
||||
#define REG_DMAC_WRBADDR (0x41004838) /**< \brief (DMAC) Write-Back Memory Section Base Address */
|
||||
#define REG_DMAC_CHID (0x4100483F) /**< \brief (DMAC) Channel ID */
|
||||
#define REG_DMAC_CHCTRLA (0x41004840) /**< \brief (DMAC) Channel Control A */
|
||||
#define REG_DMAC_CHCTRLB (0x41004844) /**< \brief (DMAC) Channel Control B */
|
||||
#define REG_DMAC_CHINTENCLR (0x4100484C) /**< \brief (DMAC) Channel Interrupt Enable Clear */
|
||||
#define REG_DMAC_CHINTENSET (0x4100484D) /**< \brief (DMAC) Channel Interrupt Enable Set */
|
||||
#define REG_DMAC_CHINTFLAG (0x4100484E) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
|
||||
#define REG_DMAC_CHSTATUS (0x4100484F) /**< \brief (DMAC) Channel Status */
|
||||
#else
|
||||
#define REG_DMAC_CTRL (*(RwReg16*)0x41004800UL) /**< \brief (DMAC) Control */
|
||||
#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802UL) /**< \brief (DMAC) CRC Control */
|
||||
#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804UL) /**< \brief (DMAC) CRC Data Input */
|
||||
#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808UL) /**< \brief (DMAC) CRC Checksum */
|
||||
#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CUL) /**< \brief (DMAC) CRC Status */
|
||||
#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DUL) /**< \brief (DMAC) Debug Control */
|
||||
#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EUL) /**< \brief (DMAC) QOS Control */
|
||||
#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810UL) /**< \brief (DMAC) Software Trigger Control */
|
||||
#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814UL) /**< \brief (DMAC) Priority Control 0 */
|
||||
#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820UL) /**< \brief (DMAC) Interrupt Pending */
|
||||
#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824UL) /**< \brief (DMAC) Interrupt Status */
|
||||
#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828UL) /**< \brief (DMAC) Busy Channels */
|
||||
#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CUL) /**< \brief (DMAC) Pending Channels */
|
||||
#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830UL) /**< \brief (DMAC) Active Channel and Levels */
|
||||
#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834UL) /**< \brief (DMAC) Descriptor Memory Section Base Address */
|
||||
#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838UL) /**< \brief (DMAC) Write-Back Memory Section Base Address */
|
||||
#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FUL) /**< \brief (DMAC) Channel ID */
|
||||
#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840UL) /**< \brief (DMAC) Channel Control A */
|
||||
#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844UL) /**< \brief (DMAC) Channel Control B */
|
||||
#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CUL) /**< \brief (DMAC) Channel Interrupt Enable Clear */
|
||||
#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DUL) /**< \brief (DMAC) Channel Interrupt Enable Set */
|
||||
#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EUL) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
|
||||
#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FUL) /**< \brief (DMAC) Channel Status */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DMAC peripheral ========== */
|
||||
#define DMAC_CH_BITS 4 // Number of bits to select channel
|
||||
#define DMAC_CH_NUM 12 // Number of channels
|
||||
#define DMAC_CLK_AHB_ID 5 // AHB clock index
|
||||
#define DMAC_EVIN_NUM 4 // Number of input events
|
||||
#define DMAC_EVOUT_NUM 4 // Number of output events
|
||||
#define DMAC_LVL_BITS 2 // Number of bit to select level priority
|
||||
#define DMAC_LVL_NUM 4 // Enable priority level number
|
||||
#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
|
||||
#define DMAC_TRIG_NUM 45 // Number of peripheral triggers
|
||||
|
||||
#endif /* _SAMD21_DMAC_INSTANCE_ */
|
||||
|
||||
@@ -1,85 +1,85 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DSU
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_INSTANCE_
|
||||
#define _SAMD21_DSU_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DSU peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
|
||||
#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
|
||||
#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
|
||||
#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
|
||||
#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
|
||||
#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
|
||||
#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
|
||||
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_ENTRY (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
|
||||
#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
|
||||
#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
|
||||
#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
|
||||
#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
|
||||
#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
|
||||
#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
|
||||
#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
|
||||
#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
|
||||
#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
|
||||
#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
|
||||
#else
|
||||
#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
|
||||
#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
|
||||
#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
|
||||
#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
|
||||
#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
|
||||
#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
|
||||
#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
|
||||
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_ENTRY (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
|
||||
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
|
||||
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
|
||||
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
|
||||
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
|
||||
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
|
||||
#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
|
||||
#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
|
||||
#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
|
||||
#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
|
||||
#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DSU peripheral ========== */
|
||||
#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register
|
||||
|
||||
#endif /* _SAMD21_DSU_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DSU
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_DSU_INSTANCE_
|
||||
#define _SAMD21_DSU_INSTANCE_
|
||||
|
||||
/* ========== Register definition for DSU peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */
|
||||
#define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */
|
||||
#define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */
|
||||
#define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */
|
||||
#define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */
|
||||
#define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */
|
||||
#define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */
|
||||
#define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_ENTRY (0x41003000) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (0x41003008) /**< \brief (DSU) CoreSight ROM Table End */
|
||||
#define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) CoreSight ROM Table Memory Type */
|
||||
#define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */
|
||||
#define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */
|
||||
#define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */
|
||||
#define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */
|
||||
#define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */
|
||||
#define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */
|
||||
#define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */
|
||||
#define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */
|
||||
#define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */
|
||||
#else
|
||||
#define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */
|
||||
#define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */
|
||||
#define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */
|
||||
#define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */
|
||||
#define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */
|
||||
#define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */
|
||||
#define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */
|
||||
#define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */
|
||||
#define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */
|
||||
#define REG_DSU_ENTRY (*(RoReg *)0x41003000UL) /**< \brief (DSU) CoreSight ROM Table Entry 0 */
|
||||
#define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) CoreSight ROM Table Entry 1 */
|
||||
#define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) CoreSight ROM Table End */
|
||||
#define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) CoreSight ROM Table Memory Type */
|
||||
#define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */
|
||||
#define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */
|
||||
#define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */
|
||||
#define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */
|
||||
#define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */
|
||||
#define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */
|
||||
#define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */
|
||||
#define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */
|
||||
#define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for DSU peripheral ========== */
|
||||
#define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register
|
||||
|
||||
#endif /* _SAMD21_DSU_INSTANCE_ */
|
||||
|
||||
@@ -1,64 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for EIC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_INSTANCE_
|
||||
#define _SAMD21_EIC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EIC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_EIC_CTRL (0x40001800) /**< \brief (EIC) Control */
|
||||
#define REG_EIC_STATUS (0x40001801) /**< \brief (EIC) Status */
|
||||
#define REG_EIC_NMICTRL (0x40001802) /**< \brief (EIC) Non-Maskable Interrupt Control */
|
||||
#define REG_EIC_NMIFLAG (0x40001803) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_EVCTRL (0x40001804) /**< \brief (EIC) Event Control */
|
||||
#define REG_EIC_INTENCLR (0x40001808) /**< \brief (EIC) Interrupt Enable Clear */
|
||||
#define REG_EIC_INTENSET (0x4000180C) /**< \brief (EIC) Interrupt Enable Set */
|
||||
#define REG_EIC_INTFLAG (0x40001810) /**< \brief (EIC) Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_WAKEUP (0x40001814) /**< \brief (EIC) Wake-Up Enable */
|
||||
#define REG_EIC_CONFIG0 (0x40001818) /**< \brief (EIC) Configuration 0 */
|
||||
#define REG_EIC_CONFIG1 (0x4000181C) /**< \brief (EIC) Configuration 1 */
|
||||
#else
|
||||
#define REG_EIC_CTRL (*(RwReg8 *)0x40001800UL) /**< \brief (EIC) Control */
|
||||
#define REG_EIC_STATUS (*(RoReg8 *)0x40001801UL) /**< \brief (EIC) Status */
|
||||
#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
|
||||
#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_EVCTRL (*(RwReg *)0x40001804UL) /**< \brief (EIC) Event Control */
|
||||
#define REG_EIC_INTENCLR (*(RwReg *)0x40001808UL) /**< \brief (EIC) Interrupt Enable Clear */
|
||||
#define REG_EIC_INTENSET (*(RwReg *)0x4000180CUL) /**< \brief (EIC) Interrupt Enable Set */
|
||||
#define REG_EIC_INTFLAG (*(RwReg *)0x40001810UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_WAKEUP (*(RwReg *)0x40001814UL) /**< \brief (EIC) Wake-Up Enable */
|
||||
#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818UL) /**< \brief (EIC) Configuration 0 */
|
||||
#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CUL) /**< \brief (EIC) Configuration 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EIC peripheral ========== */
|
||||
#define EIC_CONFIG_NUM 2 // Number of CONFIG registers
|
||||
#define EIC_GCLK_ID 5 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_EIC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for EIC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EIC_INSTANCE_
|
||||
#define _SAMD21_EIC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EIC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_EIC_CTRL (0x40001800) /**< \brief (EIC) Control */
|
||||
#define REG_EIC_STATUS (0x40001801) /**< \brief (EIC) Status */
|
||||
#define REG_EIC_NMICTRL (0x40001802) /**< \brief (EIC) Non-Maskable Interrupt Control */
|
||||
#define REG_EIC_NMIFLAG (0x40001803) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_EVCTRL (0x40001804) /**< \brief (EIC) Event Control */
|
||||
#define REG_EIC_INTENCLR (0x40001808) /**< \brief (EIC) Interrupt Enable Clear */
|
||||
#define REG_EIC_INTENSET (0x4000180C) /**< \brief (EIC) Interrupt Enable Set */
|
||||
#define REG_EIC_INTFLAG (0x40001810) /**< \brief (EIC) Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_WAKEUP (0x40001814) /**< \brief (EIC) Wake-Up Enable */
|
||||
#define REG_EIC_CONFIG0 (0x40001818) /**< \brief (EIC) Configuration 0 */
|
||||
#define REG_EIC_CONFIG1 (0x4000181C) /**< \brief (EIC) Configuration 1 */
|
||||
#else
|
||||
#define REG_EIC_CTRL (*(RwReg8 *)0x40001800UL) /**< \brief (EIC) Control */
|
||||
#define REG_EIC_STATUS (*(RoReg8 *)0x40001801UL) /**< \brief (EIC) Status */
|
||||
#define REG_EIC_NMICTRL (*(RwReg8 *)0x40001802UL) /**< \brief (EIC) Non-Maskable Interrupt Control */
|
||||
#define REG_EIC_NMIFLAG (*(RwReg8 *)0x40001803UL) /**< \brief (EIC) Non-Maskable Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_EVCTRL (*(RwReg *)0x40001804UL) /**< \brief (EIC) Event Control */
|
||||
#define REG_EIC_INTENCLR (*(RwReg *)0x40001808UL) /**< \brief (EIC) Interrupt Enable Clear */
|
||||
#define REG_EIC_INTENSET (*(RwReg *)0x4000180CUL) /**< \brief (EIC) Interrupt Enable Set */
|
||||
#define REG_EIC_INTFLAG (*(RwReg *)0x40001810UL) /**< \brief (EIC) Interrupt Flag Status and Clear */
|
||||
#define REG_EIC_WAKEUP (*(RwReg *)0x40001814UL) /**< \brief (EIC) Wake-Up Enable */
|
||||
#define REG_EIC_CONFIG0 (*(RwReg *)0x40001818UL) /**< \brief (EIC) Configuration 0 */
|
||||
#define REG_EIC_CONFIG1 (*(RwReg *)0x4000181CUL) /**< \brief (EIC) Configuration 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EIC peripheral ========== */
|
||||
#define EIC_CONFIG_NUM 2 // Number of CONFIG registers
|
||||
#define EIC_GCLK_ID 5 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_EIC_INSTANCE_ */
|
||||
|
||||
@@ -1,180 +1,180 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_INSTANCE_
|
||||
#define _SAMD21_EVSYS_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EVSYS peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_EVSYS_CTRL (0x42000400) /**< \brief (EVSYS) Control */
|
||||
#define REG_EVSYS_CHANNEL (0x42000404) /**< \brief (EVSYS) Channel */
|
||||
#define REG_EVSYS_USER (0x42000408) /**< \brief (EVSYS) User Multiplexer */
|
||||
#define REG_EVSYS_CHSTATUS (0x4200040C) /**< \brief (EVSYS) Channel Status */
|
||||
#define REG_EVSYS_INTENCLR (0x42000410) /**< \brief (EVSYS) Interrupt Enable Clear */
|
||||
#define REG_EVSYS_INTENSET (0x42000414) /**< \brief (EVSYS) Interrupt Enable Set */
|
||||
#define REG_EVSYS_INTFLAG (0x42000418) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
|
||||
#else
|
||||
#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400UL) /**< \brief (EVSYS) Control */
|
||||
#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404UL) /**< \brief (EVSYS) Channel */
|
||||
#define REG_EVSYS_USER (*(RwReg16*)0x42000408UL) /**< \brief (EVSYS) User Multiplexer */
|
||||
#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CUL) /**< \brief (EVSYS) Channel Status */
|
||||
#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410UL) /**< \brief (EVSYS) Interrupt Enable Clear */
|
||||
#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414UL) /**< \brief (EVSYS) Interrupt Enable Set */
|
||||
#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EVSYS peripheral ========== */
|
||||
#define EVSYS_CHANNELS 12 // Number of Channels
|
||||
#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel
|
||||
#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1
|
||||
#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
|
||||
#define EVSYS_GCLK_ID_0 7
|
||||
#define EVSYS_GCLK_ID_1 8
|
||||
#define EVSYS_GCLK_ID_2 9
|
||||
#define EVSYS_GCLK_ID_3 10
|
||||
#define EVSYS_GCLK_ID_4 11
|
||||
#define EVSYS_GCLK_ID_5 12
|
||||
#define EVSYS_GCLK_ID_6 13
|
||||
#define EVSYS_GCLK_ID_7 14
|
||||
#define EVSYS_GCLK_ID_8 15
|
||||
#define EVSYS_GCLK_ID_9 16
|
||||
#define EVSYS_GCLK_ID_10 17
|
||||
#define EVSYS_GCLK_ID_11 18
|
||||
#define EVSYS_GCLK_ID_LSB 7
|
||||
#define EVSYS_GCLK_ID_MSB 18
|
||||
#define EVSYS_GCLK_ID_SIZE 12
|
||||
#define EVSYS_GENERATORS 73 // Total Number of Event Generators
|
||||
#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
|
||||
#define EVSYS_USERS 29 // Total Number of Event Users
|
||||
#define EVSYS_USERS_BITS 5 // Number of bits to select Event User
|
||||
|
||||
// GENERATORS
|
||||
#define EVSYS_ID_GEN_RTC_CMP_0 1
|
||||
#define EVSYS_ID_GEN_RTC_CMP_1 2
|
||||
#define EVSYS_ID_GEN_RTC_OVF 3
|
||||
#define EVSYS_ID_GEN_RTC_PER_0 4
|
||||
#define EVSYS_ID_GEN_RTC_PER_1 5
|
||||
#define EVSYS_ID_GEN_RTC_PER_2 6
|
||||
#define EVSYS_ID_GEN_RTC_PER_3 7
|
||||
#define EVSYS_ID_GEN_RTC_PER_4 8
|
||||
#define EVSYS_ID_GEN_RTC_PER_5 9
|
||||
#define EVSYS_ID_GEN_RTC_PER_6 10
|
||||
#define EVSYS_ID_GEN_RTC_PER_7 11
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_0 12
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_1 13
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_2 14
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_3 15
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_4 16
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_5 17
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_6 18
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_7 19
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_8 20
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_9 21
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_10 22
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_11 23
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_12 24
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_13 25
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_14 26
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_15 27
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_16 28
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_17 29
|
||||
#define EVSYS_ID_GEN_DMAC_CH_0 30
|
||||
#define EVSYS_ID_GEN_DMAC_CH_1 31
|
||||
#define EVSYS_ID_GEN_DMAC_CH_2 32
|
||||
#define EVSYS_ID_GEN_DMAC_CH_3 33
|
||||
#define EVSYS_ID_GEN_TCC0_OVF 34
|
||||
#define EVSYS_ID_GEN_TCC0_TRG 35
|
||||
#define EVSYS_ID_GEN_TCC0_CNT 36
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_0 37
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_1 38
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_2 39
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_3 40
|
||||
#define EVSYS_ID_GEN_TCC1_OVF 41
|
||||
#define EVSYS_ID_GEN_TCC1_TRG 42
|
||||
#define EVSYS_ID_GEN_TCC1_CNT 43
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_0 44
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_1 45
|
||||
#define EVSYS_ID_GEN_TCC2_OVF 46
|
||||
#define EVSYS_ID_GEN_TCC2_TRG 47
|
||||
#define EVSYS_ID_GEN_TCC2_CNT 48
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_0 49
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_1 50
|
||||
#define EVSYS_ID_GEN_TC3_OVF 51
|
||||
#define EVSYS_ID_GEN_TC3_MCX_0 52
|
||||
#define EVSYS_ID_GEN_TC3_MCX_1 53
|
||||
#define EVSYS_ID_GEN_TC4_OVF 54
|
||||
#define EVSYS_ID_GEN_TC4_MCX_0 55
|
||||
#define EVSYS_ID_GEN_TC4_MCX_1 56
|
||||
#define EVSYS_ID_GEN_TC5_OVF 57
|
||||
#define EVSYS_ID_GEN_TC5_MCX_0 58
|
||||
#define EVSYS_ID_GEN_TC5_MCX_1 59
|
||||
#define EVSYS_ID_GEN_TC6_OVF 60
|
||||
#define EVSYS_ID_GEN_TC6_MCX_0 61
|
||||
#define EVSYS_ID_GEN_TC6_MCX_1 62
|
||||
#define EVSYS_ID_GEN_TC7_OVF 63
|
||||
#define EVSYS_ID_GEN_TC7_MCX_0 64
|
||||
#define EVSYS_ID_GEN_TC7_MCX_1 65
|
||||
#define EVSYS_ID_GEN_ADC_RESRDY 66
|
||||
#define EVSYS_ID_GEN_ADC_WINMON 67
|
||||
#define EVSYS_ID_GEN_AC_COMP_0 68
|
||||
#define EVSYS_ID_GEN_AC_COMP_1 69
|
||||
#define EVSYS_ID_GEN_AC_WIN_0 70
|
||||
#define EVSYS_ID_GEN_DAC_EMPTY 71
|
||||
|
||||
// USERS
|
||||
#define EVSYS_ID_USER_DMAC_CH_0 0
|
||||
#define EVSYS_ID_USER_DMAC_CH_1 1
|
||||
#define EVSYS_ID_USER_DMAC_CH_2 2
|
||||
#define EVSYS_ID_USER_DMAC_CH_3 3
|
||||
#define EVSYS_ID_USER_TCC0_EV_0 4
|
||||
#define EVSYS_ID_USER_TCC0_EV_1 5
|
||||
#define EVSYS_ID_USER_TCC0_MC_0 6
|
||||
#define EVSYS_ID_USER_TCC0_MC_1 7
|
||||
#define EVSYS_ID_USER_TCC0_MC_2 8
|
||||
#define EVSYS_ID_USER_TCC0_MC_3 9
|
||||
#define EVSYS_ID_USER_TCC1_EV_0 10
|
||||
#define EVSYS_ID_USER_TCC1_EV_1 11
|
||||
#define EVSYS_ID_USER_TCC1_MC_0 12
|
||||
#define EVSYS_ID_USER_TCC1_MC_1 13
|
||||
#define EVSYS_ID_USER_TCC2_EV_0 14
|
||||
#define EVSYS_ID_USER_TCC2_EV_1 15
|
||||
#define EVSYS_ID_USER_TCC2_MC_0 16
|
||||
#define EVSYS_ID_USER_TCC2_MC_1 17
|
||||
#define EVSYS_ID_USER_TC3_EVU 18
|
||||
#define EVSYS_ID_USER_TC4_EVU 19
|
||||
#define EVSYS_ID_USER_TC5_EVU 20
|
||||
#define EVSYS_ID_USER_TC6_EVU 21
|
||||
#define EVSYS_ID_USER_TC7_EVU 22
|
||||
#define EVSYS_ID_USER_ADC_START 23
|
||||
#define EVSYS_ID_USER_ADC_SYNC 24
|
||||
#define EVSYS_ID_USER_AC_SOC_0 25
|
||||
#define EVSYS_ID_USER_AC_SOC_1 26
|
||||
#define EVSYS_ID_USER_DAC_START 27
|
||||
|
||||
#endif /* _SAMD21_EVSYS_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for EVSYS
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_EVSYS_INSTANCE_
|
||||
#define _SAMD21_EVSYS_INSTANCE_
|
||||
|
||||
/* ========== Register definition for EVSYS peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_EVSYS_CTRL (0x42000400) /**< \brief (EVSYS) Control */
|
||||
#define REG_EVSYS_CHANNEL (0x42000404) /**< \brief (EVSYS) Channel */
|
||||
#define REG_EVSYS_USER (0x42000408) /**< \brief (EVSYS) User Multiplexer */
|
||||
#define REG_EVSYS_CHSTATUS (0x4200040C) /**< \brief (EVSYS) Channel Status */
|
||||
#define REG_EVSYS_INTENCLR (0x42000410) /**< \brief (EVSYS) Interrupt Enable Clear */
|
||||
#define REG_EVSYS_INTENSET (0x42000414) /**< \brief (EVSYS) Interrupt Enable Set */
|
||||
#define REG_EVSYS_INTFLAG (0x42000418) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
|
||||
#else
|
||||
#define REG_EVSYS_CTRL (*(WoReg8 *)0x42000400UL) /**< \brief (EVSYS) Control */
|
||||
#define REG_EVSYS_CHANNEL (*(RwReg *)0x42000404UL) /**< \brief (EVSYS) Channel */
|
||||
#define REG_EVSYS_USER (*(RwReg16*)0x42000408UL) /**< \brief (EVSYS) User Multiplexer */
|
||||
#define REG_EVSYS_CHSTATUS (*(RoReg *)0x4200040CUL) /**< \brief (EVSYS) Channel Status */
|
||||
#define REG_EVSYS_INTENCLR (*(RwReg *)0x42000410UL) /**< \brief (EVSYS) Interrupt Enable Clear */
|
||||
#define REG_EVSYS_INTENSET (*(RwReg *)0x42000414UL) /**< \brief (EVSYS) Interrupt Enable Set */
|
||||
#define REG_EVSYS_INTFLAG (*(RwReg *)0x42000418UL) /**< \brief (EVSYS) Interrupt Flag Status and Clear */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for EVSYS peripheral ========== */
|
||||
#define EVSYS_CHANNELS 12 // Number of Channels
|
||||
#define EVSYS_CHANNELS_BITS 4 // Number of bits to select Channel
|
||||
#define EVSYS_CHANNELS_MSB 11 // Number of Channels - 1
|
||||
#define EVSYS_EXTEVT_NUM 0 // Number of External Event Generators
|
||||
#define EVSYS_GCLK_ID_0 7
|
||||
#define EVSYS_GCLK_ID_1 8
|
||||
#define EVSYS_GCLK_ID_2 9
|
||||
#define EVSYS_GCLK_ID_3 10
|
||||
#define EVSYS_GCLK_ID_4 11
|
||||
#define EVSYS_GCLK_ID_5 12
|
||||
#define EVSYS_GCLK_ID_6 13
|
||||
#define EVSYS_GCLK_ID_7 14
|
||||
#define EVSYS_GCLK_ID_8 15
|
||||
#define EVSYS_GCLK_ID_9 16
|
||||
#define EVSYS_GCLK_ID_10 17
|
||||
#define EVSYS_GCLK_ID_11 18
|
||||
#define EVSYS_GCLK_ID_LSB 7
|
||||
#define EVSYS_GCLK_ID_MSB 18
|
||||
#define EVSYS_GCLK_ID_SIZE 12
|
||||
#define EVSYS_GENERATORS 73 // Total Number of Event Generators
|
||||
#define EVSYS_GENERATORS_BITS 7 // Number of bits to select Event Generator
|
||||
#define EVSYS_USERS 29 // Total Number of Event Users
|
||||
#define EVSYS_USERS_BITS 5 // Number of bits to select Event User
|
||||
|
||||
// GENERATORS
|
||||
#define EVSYS_ID_GEN_RTC_CMP_0 1
|
||||
#define EVSYS_ID_GEN_RTC_CMP_1 2
|
||||
#define EVSYS_ID_GEN_RTC_OVF 3
|
||||
#define EVSYS_ID_GEN_RTC_PER_0 4
|
||||
#define EVSYS_ID_GEN_RTC_PER_1 5
|
||||
#define EVSYS_ID_GEN_RTC_PER_2 6
|
||||
#define EVSYS_ID_GEN_RTC_PER_3 7
|
||||
#define EVSYS_ID_GEN_RTC_PER_4 8
|
||||
#define EVSYS_ID_GEN_RTC_PER_5 9
|
||||
#define EVSYS_ID_GEN_RTC_PER_6 10
|
||||
#define EVSYS_ID_GEN_RTC_PER_7 11
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_0 12
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_1 13
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_2 14
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_3 15
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_4 16
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_5 17
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_6 18
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_7 19
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_8 20
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_9 21
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_10 22
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_11 23
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_12 24
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_13 25
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_14 26
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_15 27
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_16 28
|
||||
#define EVSYS_ID_GEN_EIC_EXTINT_17 29
|
||||
#define EVSYS_ID_GEN_DMAC_CH_0 30
|
||||
#define EVSYS_ID_GEN_DMAC_CH_1 31
|
||||
#define EVSYS_ID_GEN_DMAC_CH_2 32
|
||||
#define EVSYS_ID_GEN_DMAC_CH_3 33
|
||||
#define EVSYS_ID_GEN_TCC0_OVF 34
|
||||
#define EVSYS_ID_GEN_TCC0_TRG 35
|
||||
#define EVSYS_ID_GEN_TCC0_CNT 36
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_0 37
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_1 38
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_2 39
|
||||
#define EVSYS_ID_GEN_TCC0_MCX_3 40
|
||||
#define EVSYS_ID_GEN_TCC1_OVF 41
|
||||
#define EVSYS_ID_GEN_TCC1_TRG 42
|
||||
#define EVSYS_ID_GEN_TCC1_CNT 43
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_0 44
|
||||
#define EVSYS_ID_GEN_TCC1_MCX_1 45
|
||||
#define EVSYS_ID_GEN_TCC2_OVF 46
|
||||
#define EVSYS_ID_GEN_TCC2_TRG 47
|
||||
#define EVSYS_ID_GEN_TCC2_CNT 48
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_0 49
|
||||
#define EVSYS_ID_GEN_TCC2_MCX_1 50
|
||||
#define EVSYS_ID_GEN_TC3_OVF 51
|
||||
#define EVSYS_ID_GEN_TC3_MCX_0 52
|
||||
#define EVSYS_ID_GEN_TC3_MCX_1 53
|
||||
#define EVSYS_ID_GEN_TC4_OVF 54
|
||||
#define EVSYS_ID_GEN_TC4_MCX_0 55
|
||||
#define EVSYS_ID_GEN_TC4_MCX_1 56
|
||||
#define EVSYS_ID_GEN_TC5_OVF 57
|
||||
#define EVSYS_ID_GEN_TC5_MCX_0 58
|
||||
#define EVSYS_ID_GEN_TC5_MCX_1 59
|
||||
#define EVSYS_ID_GEN_TC6_OVF 60
|
||||
#define EVSYS_ID_GEN_TC6_MCX_0 61
|
||||
#define EVSYS_ID_GEN_TC6_MCX_1 62
|
||||
#define EVSYS_ID_GEN_TC7_OVF 63
|
||||
#define EVSYS_ID_GEN_TC7_MCX_0 64
|
||||
#define EVSYS_ID_GEN_TC7_MCX_1 65
|
||||
#define EVSYS_ID_GEN_ADC_RESRDY 66
|
||||
#define EVSYS_ID_GEN_ADC_WINMON 67
|
||||
#define EVSYS_ID_GEN_AC_COMP_0 68
|
||||
#define EVSYS_ID_GEN_AC_COMP_1 69
|
||||
#define EVSYS_ID_GEN_AC_WIN_0 70
|
||||
#define EVSYS_ID_GEN_DAC_EMPTY 71
|
||||
|
||||
// USERS
|
||||
#define EVSYS_ID_USER_DMAC_CH_0 0
|
||||
#define EVSYS_ID_USER_DMAC_CH_1 1
|
||||
#define EVSYS_ID_USER_DMAC_CH_2 2
|
||||
#define EVSYS_ID_USER_DMAC_CH_3 3
|
||||
#define EVSYS_ID_USER_TCC0_EV_0 4
|
||||
#define EVSYS_ID_USER_TCC0_EV_1 5
|
||||
#define EVSYS_ID_USER_TCC0_MC_0 6
|
||||
#define EVSYS_ID_USER_TCC0_MC_1 7
|
||||
#define EVSYS_ID_USER_TCC0_MC_2 8
|
||||
#define EVSYS_ID_USER_TCC0_MC_3 9
|
||||
#define EVSYS_ID_USER_TCC1_EV_0 10
|
||||
#define EVSYS_ID_USER_TCC1_EV_1 11
|
||||
#define EVSYS_ID_USER_TCC1_MC_0 12
|
||||
#define EVSYS_ID_USER_TCC1_MC_1 13
|
||||
#define EVSYS_ID_USER_TCC2_EV_0 14
|
||||
#define EVSYS_ID_USER_TCC2_EV_1 15
|
||||
#define EVSYS_ID_USER_TCC2_MC_0 16
|
||||
#define EVSYS_ID_USER_TCC2_MC_1 17
|
||||
#define EVSYS_ID_USER_TC3_EVU 18
|
||||
#define EVSYS_ID_USER_TC4_EVU 19
|
||||
#define EVSYS_ID_USER_TC5_EVU 20
|
||||
#define EVSYS_ID_USER_TC6_EVU 21
|
||||
#define EVSYS_ID_USER_TC7_EVU 22
|
||||
#define EVSYS_ID_USER_ADC_START 23
|
||||
#define EVSYS_ID_USER_ADC_SYNC 24
|
||||
#define EVSYS_ID_USER_AC_SOC_0 25
|
||||
#define EVSYS_ID_USER_AC_SOC_1 26
|
||||
#define EVSYS_ID_USER_DAC_START 27
|
||||
|
||||
#endif /* _SAMD21_EVSYS_INSTANCE_ */
|
||||
|
||||
@@ -1,65 +1,65 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for GCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_INSTANCE_
|
||||
#define _SAMD21_GCLK_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GCLK peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */
|
||||
#define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */
|
||||
#define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */
|
||||
#define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */
|
||||
#define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */
|
||||
#else
|
||||
#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */
|
||||
#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */
|
||||
#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */
|
||||
#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */
|
||||
#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for GCLK peripheral ========== */
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
|
||||
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
|
||||
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
|
||||
#define GCLK_NUM 37 // Number of Generic Clock Users
|
||||
#define GCLK_SOURCE_DFLL48M 7
|
||||
#define GCLK_SOURCE_DPLL96M 8
|
||||
#define GCLK_SOURCE_GCLKGEN1 2
|
||||
#define GCLK_SOURCE_GCLKIN 1
|
||||
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
|
||||
#define GCLK_SOURCE_OSCULP32K 3
|
||||
#define GCLK_SOURCE_OSC8M 6
|
||||
#define GCLK_SOURCE_OSC32K 4
|
||||
#define GCLK_SOURCE_XOSC 0
|
||||
#define GCLK_SOURCE_XOSC32K 5
|
||||
|
||||
#endif /* _SAMD21_GCLK_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for GCLK
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_GCLK_INSTANCE_
|
||||
#define _SAMD21_GCLK_INSTANCE_
|
||||
|
||||
/* ========== Register definition for GCLK peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_GCLK_CTRL (0x40000C00) /**< \brief (GCLK) Control */
|
||||
#define REG_GCLK_STATUS (0x40000C01) /**< \brief (GCLK) Status */
|
||||
#define REG_GCLK_CLKCTRL (0x40000C02) /**< \brief (GCLK) Generic Clock Control */
|
||||
#define REG_GCLK_GENCTRL (0x40000C04) /**< \brief (GCLK) Generic Clock Generator Control */
|
||||
#define REG_GCLK_GENDIV (0x40000C08) /**< \brief (GCLK) Generic Clock Generator Division */
|
||||
#else
|
||||
#define REG_GCLK_CTRL (*(RwReg8 *)0x40000C00UL) /**< \brief (GCLK) Control */
|
||||
#define REG_GCLK_STATUS (*(RoReg8 *)0x40000C01UL) /**< \brief (GCLK) Status */
|
||||
#define REG_GCLK_CLKCTRL (*(RwReg16*)0x40000C02UL) /**< \brief (GCLK) Generic Clock Control */
|
||||
#define REG_GCLK_GENCTRL (*(RwReg *)0x40000C04UL) /**< \brief (GCLK) Generic Clock Generator Control */
|
||||
#define REG_GCLK_GENDIV (*(RwReg *)0x40000C08UL) /**< \brief (GCLK) Generic Clock Generator Division */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for GCLK peripheral ========== */
|
||||
#define GCLK_GENDIV_BITS 16
|
||||
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
|
||||
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
|
||||
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1
|
||||
#define GCLK_NUM 37 // Number of Generic Clock Users
|
||||
#define GCLK_SOURCE_DFLL48M 7
|
||||
#define GCLK_SOURCE_DPLL96M 8
|
||||
#define GCLK_SOURCE_GCLKGEN1 2
|
||||
#define GCLK_SOURCE_GCLKIN 1
|
||||
#define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources
|
||||
#define GCLK_SOURCE_OSCULP32K 3
|
||||
#define GCLK_SOURCE_OSC8M 6
|
||||
#define GCLK_SOURCE_OSC32K 4
|
||||
#define GCLK_SOURCE_XOSC 0
|
||||
#define GCLK_SOURCE_XOSC32K 5
|
||||
|
||||
#endif /* _SAMD21_GCLK_INSTANCE_ */
|
||||
|
||||
@@ -1,80 +1,80 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for I2S
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_I2S_INSTANCE_
|
||||
#define _SAMD21_I2S_INSTANCE_
|
||||
|
||||
/* ========== Register definition for I2S peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_I2S_CTRLA (0x42005000) /**< \brief (I2S) Control A */
|
||||
#define REG_I2S_CLKCTRL0 (0x42005004) /**< \brief (I2S) Clock Unit 0 Control */
|
||||
#define REG_I2S_CLKCTRL1 (0x42005008) /**< \brief (I2S) Clock Unit 1 Control */
|
||||
#define REG_I2S_INTENCLR (0x4200500C) /**< \brief (I2S) Interrupt Enable Clear */
|
||||
#define REG_I2S_INTENSET (0x42005010) /**< \brief (I2S) Interrupt Enable Set */
|
||||
#define REG_I2S_INTFLAG (0x42005014) /**< \brief (I2S) Interrupt Flag Status and Clear */
|
||||
#define REG_I2S_SYNCBUSY (0x42005018) /**< \brief (I2S) Synchronization Status */
|
||||
#define REG_I2S_SERCTRL0 (0x42005020) /**< \brief (I2S) Serializer 0 Control */
|
||||
#define REG_I2S_SERCTRL1 (0x42005024) /**< \brief (I2S) Serializer 1 Control */
|
||||
#define REG_I2S_DATA0 (0x42005030) /**< \brief (I2S) Data 0 */
|
||||
#define REG_I2S_DATA1 (0x42005034) /**< \brief (I2S) Data 1 */
|
||||
#else
|
||||
#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000UL) /**< \brief (I2S) Control A */
|
||||
#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004UL) /**< \brief (I2S) Clock Unit 0 Control */
|
||||
#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008UL) /**< \brief (I2S) Clock Unit 1 Control */
|
||||
#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CUL) /**< \brief (I2S) Interrupt Enable Clear */
|
||||
#define REG_I2S_INTENSET (*(RwReg16*)0x42005010UL) /**< \brief (I2S) Interrupt Enable Set */
|
||||
#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
|
||||
#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018UL) /**< \brief (I2S) Synchronization Status */
|
||||
#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020UL) /**< \brief (I2S) Serializer 0 Control */
|
||||
#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024UL) /**< \brief (I2S) Serializer 1 Control */
|
||||
#define REG_I2S_DATA0 (*(RwReg *)0x42005030UL) /**< \brief (I2S) Data 0 */
|
||||
#define REG_I2S_DATA1 (*(RwReg *)0x42005034UL) /**< \brief (I2S) Data 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for I2S peripheral ========== */
|
||||
#define I2S_CLK_NUM 2 // Number of clock units
|
||||
#define I2S_DMAC_ID_RX_0 41
|
||||
#define I2S_DMAC_ID_RX_1 42
|
||||
#define I2S_DMAC_ID_RX_LSB 41
|
||||
#define I2S_DMAC_ID_RX_MSB 42
|
||||
#define I2S_DMAC_ID_RX_SIZE 2
|
||||
#define I2S_DMAC_ID_TX_0 43
|
||||
#define I2S_DMAC_ID_TX_1 44
|
||||
#define I2S_DMAC_ID_TX_LSB 43
|
||||
#define I2S_DMAC_ID_TX_MSB 44
|
||||
#define I2S_DMAC_ID_TX_SIZE 2
|
||||
#define I2S_GCLK_ID_0 35
|
||||
#define I2S_GCLK_ID_1 36
|
||||
#define I2S_GCLK_ID_LSB 35
|
||||
#define I2S_GCLK_ID_MSB 36
|
||||
#define I2S_GCLK_ID_SIZE 2
|
||||
#define I2S_MAX_SLOTS 8 // Max number of data slots in frame
|
||||
#define I2S_SER_NUM 2 // Number of serializers
|
||||
|
||||
#endif /* _SAMD21_I2S_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for I2S
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_I2S_INSTANCE_
|
||||
#define _SAMD21_I2S_INSTANCE_
|
||||
|
||||
/* ========== Register definition for I2S peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_I2S_CTRLA (0x42005000) /**< \brief (I2S) Control A */
|
||||
#define REG_I2S_CLKCTRL0 (0x42005004) /**< \brief (I2S) Clock Unit 0 Control */
|
||||
#define REG_I2S_CLKCTRL1 (0x42005008) /**< \brief (I2S) Clock Unit 1 Control */
|
||||
#define REG_I2S_INTENCLR (0x4200500C) /**< \brief (I2S) Interrupt Enable Clear */
|
||||
#define REG_I2S_INTENSET (0x42005010) /**< \brief (I2S) Interrupt Enable Set */
|
||||
#define REG_I2S_INTFLAG (0x42005014) /**< \brief (I2S) Interrupt Flag Status and Clear */
|
||||
#define REG_I2S_SYNCBUSY (0x42005018) /**< \brief (I2S) Synchronization Status */
|
||||
#define REG_I2S_SERCTRL0 (0x42005020) /**< \brief (I2S) Serializer 0 Control */
|
||||
#define REG_I2S_SERCTRL1 (0x42005024) /**< \brief (I2S) Serializer 1 Control */
|
||||
#define REG_I2S_DATA0 (0x42005030) /**< \brief (I2S) Data 0 */
|
||||
#define REG_I2S_DATA1 (0x42005034) /**< \brief (I2S) Data 1 */
|
||||
#else
|
||||
#define REG_I2S_CTRLA (*(RwReg8 *)0x42005000UL) /**< \brief (I2S) Control A */
|
||||
#define REG_I2S_CLKCTRL0 (*(RwReg *)0x42005004UL) /**< \brief (I2S) Clock Unit 0 Control */
|
||||
#define REG_I2S_CLKCTRL1 (*(RwReg *)0x42005008UL) /**< \brief (I2S) Clock Unit 1 Control */
|
||||
#define REG_I2S_INTENCLR (*(RwReg16*)0x4200500CUL) /**< \brief (I2S) Interrupt Enable Clear */
|
||||
#define REG_I2S_INTENSET (*(RwReg16*)0x42005010UL) /**< \brief (I2S) Interrupt Enable Set */
|
||||
#define REG_I2S_INTFLAG (*(RwReg16*)0x42005014UL) /**< \brief (I2S) Interrupt Flag Status and Clear */
|
||||
#define REG_I2S_SYNCBUSY (*(RoReg16*)0x42005018UL) /**< \brief (I2S) Synchronization Status */
|
||||
#define REG_I2S_SERCTRL0 (*(RwReg *)0x42005020UL) /**< \brief (I2S) Serializer 0 Control */
|
||||
#define REG_I2S_SERCTRL1 (*(RwReg *)0x42005024UL) /**< \brief (I2S) Serializer 1 Control */
|
||||
#define REG_I2S_DATA0 (*(RwReg *)0x42005030UL) /**< \brief (I2S) Data 0 */
|
||||
#define REG_I2S_DATA1 (*(RwReg *)0x42005034UL) /**< \brief (I2S) Data 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for I2S peripheral ========== */
|
||||
#define I2S_CLK_NUM 2 // Number of clock units
|
||||
#define I2S_DMAC_ID_RX_0 41
|
||||
#define I2S_DMAC_ID_RX_1 42
|
||||
#define I2S_DMAC_ID_RX_LSB 41
|
||||
#define I2S_DMAC_ID_RX_MSB 42
|
||||
#define I2S_DMAC_ID_RX_SIZE 2
|
||||
#define I2S_DMAC_ID_TX_0 43
|
||||
#define I2S_DMAC_ID_TX_1 44
|
||||
#define I2S_DMAC_ID_TX_LSB 43
|
||||
#define I2S_DMAC_ID_TX_MSB 44
|
||||
#define I2S_DMAC_ID_TX_SIZE 2
|
||||
#define I2S_GCLK_ID_0 35
|
||||
#define I2S_GCLK_ID_1 36
|
||||
#define I2S_GCLK_ID_LSB 35
|
||||
#define I2S_GCLK_ID_MSB 36
|
||||
#define I2S_GCLK_ID_SIZE 2
|
||||
#define I2S_MAX_SLOTS 8 // Max number of data slots in frame
|
||||
#define I2S_SER_NUM 2 // Number of serializers
|
||||
|
||||
#endif /* _SAMD21_I2S_INSTANCE_ */
|
||||
|
||||
@@ -1,89 +1,89 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for MTB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_INSTANCE_
|
||||
#define _SAMD21_MTB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MTB peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_MTB_POSITION (0x41006000) /**< \brief (MTB) MTB Position */
|
||||
#define REG_MTB_MASTER (0x41006004) /**< \brief (MTB) MTB Master */
|
||||
#define REG_MTB_FLOW (0x41006008) /**< \brief (MTB) MTB Flow */
|
||||
#define REG_MTB_BASE (0x4100600C) /**< \brief (MTB) MTB Base */
|
||||
#define REG_MTB_ITCTRL (0x41006F00) /**< \brief (MTB) MTB Integration Mode Control */
|
||||
#define REG_MTB_CLAIMSET (0x41006FA0) /**< \brief (MTB) MTB Claim Set */
|
||||
#define REG_MTB_CLAIMCLR (0x41006FA4) /**< \brief (MTB) MTB Claim Clear */
|
||||
#define REG_MTB_LOCKACCESS (0x41006FB0) /**< \brief (MTB) MTB Lock Access */
|
||||
#define REG_MTB_LOCKSTATUS (0x41006FB4) /**< \brief (MTB) MTB Lock Status */
|
||||
#define REG_MTB_AUTHSTATUS (0x41006FB8) /**< \brief (MTB) MTB Authentication Status */
|
||||
#define REG_MTB_DEVARCH (0x41006FBC) /**< \brief (MTB) MTB Device Architecture */
|
||||
#define REG_MTB_DEVID (0x41006FC8) /**< \brief (MTB) MTB Device Configuration */
|
||||
#define REG_MTB_DEVTYPE (0x41006FCC) /**< \brief (MTB) MTB Device Type */
|
||||
#define REG_MTB_PID4 (0x41006FD0) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID5 (0x41006FD4) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID6 (0x41006FD8) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID7 (0x41006FDC) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID0 (0x41006FE0) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID1 (0x41006FE4) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID2 (0x41006FE8) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID3 (0x41006FEC) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID0 (0x41006FF0) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID1 (0x41006FF4) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID2 (0x41006FF8) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID3 (0x41006FFC) /**< \brief (MTB) CoreSight */
|
||||
#else
|
||||
#define REG_MTB_POSITION (*(RwReg *)0x41006000UL) /**< \brief (MTB) MTB Position */
|
||||
#define REG_MTB_MASTER (*(RwReg *)0x41006004UL) /**< \brief (MTB) MTB Master */
|
||||
#define REG_MTB_FLOW (*(RwReg *)0x41006008UL) /**< \brief (MTB) MTB Flow */
|
||||
#define REG_MTB_BASE (*(RoReg *)0x4100600CUL) /**< \brief (MTB) MTB Base */
|
||||
#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00UL) /**< \brief (MTB) MTB Integration Mode Control */
|
||||
#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0UL) /**< \brief (MTB) MTB Claim Set */
|
||||
#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4UL) /**< \brief (MTB) MTB Claim Clear */
|
||||
#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0UL) /**< \brief (MTB) MTB Lock Access */
|
||||
#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */
|
||||
#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication Status */
|
||||
#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architecture */
|
||||
#define REG_MTB_DEVID (*(RoReg *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configuration */
|
||||
#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */
|
||||
#define REG_MTB_PID4 (*(RoReg *)0x41006FD0UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID5 (*(RoReg *)0x41006FD4UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID6 (*(RoReg *)0x41006FD8UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID7 (*(RoReg *)0x41006FDCUL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID0 (*(RoReg *)0x41006FE0UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID1 (*(RoReg *)0x41006FE4UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID2 (*(RoReg *)0x41006FE8UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID3 (*(RoReg *)0x41006FECUL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID0 (*(RoReg *)0x41006FF0UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID1 (*(RoReg *)0x41006FF4UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID2 (*(RoReg *)0x41006FF8UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID3 (*(RoReg *)0x41006FFCUL) /**< \brief (MTB) CoreSight */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
|
||||
#endif /* _SAMD21_MTB_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for MTB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_MTB_INSTANCE_
|
||||
#define _SAMD21_MTB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for MTB peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_MTB_POSITION (0x41006000) /**< \brief (MTB) MTB Position */
|
||||
#define REG_MTB_MASTER (0x41006004) /**< \brief (MTB) MTB Master */
|
||||
#define REG_MTB_FLOW (0x41006008) /**< \brief (MTB) MTB Flow */
|
||||
#define REG_MTB_BASE (0x4100600C) /**< \brief (MTB) MTB Base */
|
||||
#define REG_MTB_ITCTRL (0x41006F00) /**< \brief (MTB) MTB Integration Mode Control */
|
||||
#define REG_MTB_CLAIMSET (0x41006FA0) /**< \brief (MTB) MTB Claim Set */
|
||||
#define REG_MTB_CLAIMCLR (0x41006FA4) /**< \brief (MTB) MTB Claim Clear */
|
||||
#define REG_MTB_LOCKACCESS (0x41006FB0) /**< \brief (MTB) MTB Lock Access */
|
||||
#define REG_MTB_LOCKSTATUS (0x41006FB4) /**< \brief (MTB) MTB Lock Status */
|
||||
#define REG_MTB_AUTHSTATUS (0x41006FB8) /**< \brief (MTB) MTB Authentication Status */
|
||||
#define REG_MTB_DEVARCH (0x41006FBC) /**< \brief (MTB) MTB Device Architecture */
|
||||
#define REG_MTB_DEVID (0x41006FC8) /**< \brief (MTB) MTB Device Configuration */
|
||||
#define REG_MTB_DEVTYPE (0x41006FCC) /**< \brief (MTB) MTB Device Type */
|
||||
#define REG_MTB_PID4 (0x41006FD0) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID5 (0x41006FD4) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID6 (0x41006FD8) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID7 (0x41006FDC) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID0 (0x41006FE0) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID1 (0x41006FE4) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID2 (0x41006FE8) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID3 (0x41006FEC) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID0 (0x41006FF0) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID1 (0x41006FF4) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID2 (0x41006FF8) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID3 (0x41006FFC) /**< \brief (MTB) CoreSight */
|
||||
#else
|
||||
#define REG_MTB_POSITION (*(RwReg *)0x41006000UL) /**< \brief (MTB) MTB Position */
|
||||
#define REG_MTB_MASTER (*(RwReg *)0x41006004UL) /**< \brief (MTB) MTB Master */
|
||||
#define REG_MTB_FLOW (*(RwReg *)0x41006008UL) /**< \brief (MTB) MTB Flow */
|
||||
#define REG_MTB_BASE (*(RoReg *)0x4100600CUL) /**< \brief (MTB) MTB Base */
|
||||
#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00UL) /**< \brief (MTB) MTB Integration Mode Control */
|
||||
#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0UL) /**< \brief (MTB) MTB Claim Set */
|
||||
#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4UL) /**< \brief (MTB) MTB Claim Clear */
|
||||
#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0UL) /**< \brief (MTB) MTB Lock Access */
|
||||
#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4UL) /**< \brief (MTB) MTB Lock Status */
|
||||
#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8UL) /**< \brief (MTB) MTB Authentication Status */
|
||||
#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCUL) /**< \brief (MTB) MTB Device Architecture */
|
||||
#define REG_MTB_DEVID (*(RoReg *)0x41006FC8UL) /**< \brief (MTB) MTB Device Configuration */
|
||||
#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCUL) /**< \brief (MTB) MTB Device Type */
|
||||
#define REG_MTB_PID4 (*(RoReg *)0x41006FD0UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID5 (*(RoReg *)0x41006FD4UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID6 (*(RoReg *)0x41006FD8UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID7 (*(RoReg *)0x41006FDCUL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID0 (*(RoReg *)0x41006FE0UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID1 (*(RoReg *)0x41006FE4UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID2 (*(RoReg *)0x41006FE8UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_PID3 (*(RoReg *)0x41006FECUL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID0 (*(RoReg *)0x41006FF0UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID1 (*(RoReg *)0x41006FF4UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID2 (*(RoReg *)0x41006FF8UL) /**< \brief (MTB) CoreSight */
|
||||
#define REG_MTB_CID3 (*(RoReg *)0x41006FFCUL) /**< \brief (MTB) CoreSight */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
|
||||
#endif /* _SAMD21_MTB_INSTANCE_ */
|
||||
|
||||
@@ -1,77 +1,77 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_NVMCTRL_INSTANCE_
|
||||
#define _SAMD21_NVMCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for NVMCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
|
||||
#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
|
||||
#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
|
||||
#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
|
||||
#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */
|
||||
#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */
|
||||
#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */
|
||||
#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */
|
||||
#else
|
||||
#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
|
||||
#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */
|
||||
#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
|
||||
#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
|
||||
#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */
|
||||
#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */
|
||||
#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */
|
||||
#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for NVMCTRL peripheral ========== */
|
||||
#define NVMCTRL_AUX0_ADDRESS 0x00804000
|
||||
#define NVMCTRL_AUX1_ADDRESS 0x00806000
|
||||
#define NVMCTRL_AUX2_ADDRESS 0x00808000
|
||||
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
|
||||
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
|
||||
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
|
||||
#define NVMCTRL_FLASH_SIZE 262144
|
||||
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
#define NVMCTRL_PMSB 3
|
||||
#define NVMCTRL_PSZ_BITS 6
|
||||
#define NVMCTRL_ROW_PAGES 4
|
||||
#define NVMCTRL_ROW_SIZE 256
|
||||
#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
|
||||
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
|
||||
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
|
||||
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
|
||||
|
||||
#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for NVMCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_NVMCTRL_INSTANCE_
|
||||
#define _SAMD21_NVMCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for NVMCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_NVMCTRL_CTRLA (0x41004000) /**< \brief (NVMCTRL) Control A */
|
||||
#define REG_NVMCTRL_CTRLB (0x41004004) /**< \brief (NVMCTRL) Control B */
|
||||
#define REG_NVMCTRL_PARAM (0x41004008) /**< \brief (NVMCTRL) NVM Parameter */
|
||||
#define REG_NVMCTRL_INTENCLR (0x4100400C) /**< \brief (NVMCTRL) Interrupt Enable Clear */
|
||||
#define REG_NVMCTRL_INTENSET (0x41004010) /**< \brief (NVMCTRL) Interrupt Enable Set */
|
||||
#define REG_NVMCTRL_INTFLAG (0x41004014) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_NVMCTRL_STATUS (0x41004018) /**< \brief (NVMCTRL) Status */
|
||||
#define REG_NVMCTRL_ADDR (0x4100401C) /**< \brief (NVMCTRL) Address */
|
||||
#define REG_NVMCTRL_LOCK (0x41004020) /**< \brief (NVMCTRL) Lock Section */
|
||||
#else
|
||||
#define REG_NVMCTRL_CTRLA (*(RwReg16*)0x41004000UL) /**< \brief (NVMCTRL) Control A */
|
||||
#define REG_NVMCTRL_CTRLB (*(RwReg *)0x41004004UL) /**< \brief (NVMCTRL) Control B */
|
||||
#define REG_NVMCTRL_PARAM (*(RwReg *)0x41004008UL) /**< \brief (NVMCTRL) NVM Parameter */
|
||||
#define REG_NVMCTRL_INTENCLR (*(RwReg8 *)0x4100400CUL) /**< \brief (NVMCTRL) Interrupt Enable Clear */
|
||||
#define REG_NVMCTRL_INTENSET (*(RwReg8 *)0x41004010UL) /**< \brief (NVMCTRL) Interrupt Enable Set */
|
||||
#define REG_NVMCTRL_INTFLAG (*(RwReg8 *)0x41004014UL) /**< \brief (NVMCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_NVMCTRL_STATUS (*(RwReg16*)0x41004018UL) /**< \brief (NVMCTRL) Status */
|
||||
#define REG_NVMCTRL_ADDR (*(RwReg *)0x4100401CUL) /**< \brief (NVMCTRL) Address */
|
||||
#define REG_NVMCTRL_LOCK (*(RwReg16*)0x41004020UL) /**< \brief (NVMCTRL) Lock Section */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for NVMCTRL peripheral ========== */
|
||||
#define NVMCTRL_AUX0_ADDRESS 0x00804000
|
||||
#define NVMCTRL_AUX1_ADDRESS 0x00806000
|
||||
#define NVMCTRL_AUX2_ADDRESS 0x00808000
|
||||
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
|
||||
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
|
||||
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
|
||||
#define NVMCTRL_FLASH_SIZE 262144
|
||||
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
|
||||
#define NVMCTRL_PAGE_HW 32
|
||||
#define NVMCTRL_PAGE_SIZE 64
|
||||
#define NVMCTRL_PAGE_W 16
|
||||
#define NVMCTRL_PMSB 3
|
||||
#define NVMCTRL_PSZ_BITS 6
|
||||
#define NVMCTRL_ROW_PAGES 4
|
||||
#define NVMCTRL_ROW_SIZE 256
|
||||
#define NVMCTRL_TEMP_LOG_ADDRESS 0x00806030
|
||||
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
|
||||
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
|
||||
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF
|
||||
|
||||
#endif /* _SAMD21_NVMCTRL_INSTANCE_ */
|
||||
|
||||
@@ -1,45 +1,45 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PAC0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC0_INSTANCE_
|
||||
#define _SAMD21_PAC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PAC0_WPCLR (0x40000000) /**< \brief (PAC0) Write Protection Clear */
|
||||
#define REG_PAC0_WPSET (0x40000004) /**< \brief (PAC0) Write Protection Set */
|
||||
#else
|
||||
#define REG_PAC0_WPCLR (*(RwReg *)0x40000000UL) /**< \brief (PAC0) Write Protection Clear */
|
||||
#define REG_PAC0_WPSET (*(RwReg *)0x40000004UL) /**< \brief (PAC0) Write Protection Set */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC0 peripheral ========== */
|
||||
#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC0_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PAC0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC0_INSTANCE_
|
||||
#define _SAMD21_PAC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PAC0_WPCLR (0x40000000) /**< \brief (PAC0) Write Protection Clear */
|
||||
#define REG_PAC0_WPSET (0x40000004) /**< \brief (PAC0) Write Protection Set */
|
||||
#else
|
||||
#define REG_PAC0_WPCLR (*(RwReg *)0x40000000UL) /**< \brief (PAC0) Write Protection Clear */
|
||||
#define REG_PAC0_WPSET (*(RwReg *)0x40000004UL) /**< \brief (PAC0) Write Protection Set */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC0 peripheral ========== */
|
||||
#define PAC0_WPROT_DEFAULT_VAL 0x00000000 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC0_INSTANCE_ */
|
||||
|
||||
@@ -1,45 +1,45 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PAC1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC1_INSTANCE_
|
||||
#define _SAMD21_PAC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PAC1_WPCLR (0x41000000) /**< \brief (PAC1) Write Protection Clear */
|
||||
#define REG_PAC1_WPSET (0x41000004) /**< \brief (PAC1) Write Protection Set */
|
||||
#else
|
||||
#define REG_PAC1_WPCLR (*(RwReg *)0x41000000UL) /**< \brief (PAC1) Write Protection Clear */
|
||||
#define REG_PAC1_WPSET (*(RwReg *)0x41000004UL) /**< \brief (PAC1) Write Protection Set */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC1 peripheral ========== */
|
||||
#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC1_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PAC1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC1_INSTANCE_
|
||||
#define _SAMD21_PAC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PAC1_WPCLR (0x41000000) /**< \brief (PAC1) Write Protection Clear */
|
||||
#define REG_PAC1_WPSET (0x41000004) /**< \brief (PAC1) Write Protection Set */
|
||||
#else
|
||||
#define REG_PAC1_WPCLR (*(RwReg *)0x41000000UL) /**< \brief (PAC1) Write Protection Clear */
|
||||
#define REG_PAC1_WPSET (*(RwReg *)0x41000004UL) /**< \brief (PAC1) Write Protection Set */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC1 peripheral ========== */
|
||||
#define PAC1_WPROT_DEFAULT_VAL 0x00000002 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC1_INSTANCE_ */
|
||||
|
||||
@@ -1,45 +1,45 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PAC2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC2_INSTANCE_
|
||||
#define _SAMD21_PAC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PAC2_WPCLR (0x42000000) /**< \brief (PAC2) Write Protection Clear */
|
||||
#define REG_PAC2_WPSET (0x42000004) /**< \brief (PAC2) Write Protection Set */
|
||||
#else
|
||||
#define REG_PAC2_WPCLR (*(RwReg *)0x42000000UL) /**< \brief (PAC2) Write Protection Clear */
|
||||
#define REG_PAC2_WPSET (*(RwReg *)0x42000004UL) /**< \brief (PAC2) Write Protection Set */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC2 peripheral ========== */
|
||||
#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC2_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PAC2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PAC2_INSTANCE_
|
||||
#define _SAMD21_PAC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PAC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PAC2_WPCLR (0x42000000) /**< \brief (PAC2) Write Protection Clear */
|
||||
#define REG_PAC2_WPSET (0x42000004) /**< \brief (PAC2) Write Protection Set */
|
||||
#else
|
||||
#define REG_PAC2_WPCLR (*(RwReg *)0x42000000UL) /**< \brief (PAC2) Write Protection Clear */
|
||||
#define REG_PAC2_WPSET (*(RwReg *)0x42000004UL) /**< \brief (PAC2) Write Protection Set */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PAC2 peripheral ========== */
|
||||
#define PAC2_WPROT_DEFAULT_VAL 0x00800000 // PAC protection mask at reset
|
||||
|
||||
#endif /* _SAMD21_PAC2_INSTANCE_ */
|
||||
|
||||
@@ -1,73 +1,73 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PM_INSTANCE_
|
||||
#define _SAMD21_PM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PM peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PM_CTRL (0x40000400) /**< \brief (PM) Control */
|
||||
#define REG_PM_SLEEP (0x40000401) /**< \brief (PM) Sleep Mode */
|
||||
#define REG_PM_CPUSEL (0x40000408) /**< \brief (PM) CPU Clock Select */
|
||||
#define REG_PM_APBASEL (0x40000409) /**< \brief (PM) APBA Clock Select */
|
||||
#define REG_PM_APBBSEL (0x4000040A) /**< \brief (PM) APBB Clock Select */
|
||||
#define REG_PM_APBCSEL (0x4000040B) /**< \brief (PM) APBC Clock Select */
|
||||
#define REG_PM_AHBMASK (0x40000414) /**< \brief (PM) AHB Mask */
|
||||
#define REG_PM_APBAMASK (0x40000418) /**< \brief (PM) APBA Mask */
|
||||
#define REG_PM_APBBMASK (0x4000041C) /**< \brief (PM) APBB Mask */
|
||||
#define REG_PM_APBCMASK (0x40000420) /**< \brief (PM) APBC Mask */
|
||||
#define REG_PM_INTENCLR (0x40000434) /**< \brief (PM) Interrupt Enable Clear */
|
||||
#define REG_PM_INTENSET (0x40000435) /**< \brief (PM) Interrupt Enable Set */
|
||||
#define REG_PM_INTFLAG (0x40000436) /**< \brief (PM) Interrupt Flag Status and Clear */
|
||||
#define REG_PM_RCAUSE (0x40000438) /**< \brief (PM) Reset Cause */
|
||||
#else
|
||||
#define REG_PM_CTRL (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control */
|
||||
#define REG_PM_SLEEP (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Mode */
|
||||
#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408UL) /**< \brief (PM) CPU Clock Select */
|
||||
#define REG_PM_APBASEL (*(RwReg8 *)0x40000409UL) /**< \brief (PM) APBA Clock Select */
|
||||
#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) APBB Clock Select */
|
||||
#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BUL) /**< \brief (PM) APBC Clock Select */
|
||||
#define REG_PM_AHBMASK (*(RwReg *)0x40000414UL) /**< \brief (PM) AHB Mask */
|
||||
#define REG_PM_APBAMASK (*(RwReg *)0x40000418UL) /**< \brief (PM) APBA Mask */
|
||||
#define REG_PM_APBBMASK (*(RwReg *)0x4000041CUL) /**< \brief (PM) APBB Mask */
|
||||
#define REG_PM_APBCMASK (*(RwReg *)0x40000420UL) /**< \brief (PM) APBC Mask */
|
||||
#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434UL) /**< \brief (PM) Interrupt Enable Clear */
|
||||
#define REG_PM_INTENSET (*(RwReg8 *)0x40000435UL) /**< \brief (PM) Interrupt Enable Set */
|
||||
#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436UL) /**< \brief (PM) Interrupt Flag Status and Clear */
|
||||
#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438UL) /**< \brief (PM) Reset Cause */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PM peripheral ========== */
|
||||
#define PM_CTRL_MCSEL_DFLL48M 3
|
||||
#define PM_CTRL_MCSEL_GCLK 0
|
||||
#define PM_CTRL_MCSEL_OSC8M 1
|
||||
#define PM_CTRL_MCSEL_XOSC 2
|
||||
#define PM_PM_CLK_APB_NUM 2
|
||||
|
||||
#endif /* _SAMD21_PM_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PM
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PM_INSTANCE_
|
||||
#define _SAMD21_PM_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PM peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PM_CTRL (0x40000400) /**< \brief (PM) Control */
|
||||
#define REG_PM_SLEEP (0x40000401) /**< \brief (PM) Sleep Mode */
|
||||
#define REG_PM_CPUSEL (0x40000408) /**< \brief (PM) CPU Clock Select */
|
||||
#define REG_PM_APBASEL (0x40000409) /**< \brief (PM) APBA Clock Select */
|
||||
#define REG_PM_APBBSEL (0x4000040A) /**< \brief (PM) APBB Clock Select */
|
||||
#define REG_PM_APBCSEL (0x4000040B) /**< \brief (PM) APBC Clock Select */
|
||||
#define REG_PM_AHBMASK (0x40000414) /**< \brief (PM) AHB Mask */
|
||||
#define REG_PM_APBAMASK (0x40000418) /**< \brief (PM) APBA Mask */
|
||||
#define REG_PM_APBBMASK (0x4000041C) /**< \brief (PM) APBB Mask */
|
||||
#define REG_PM_APBCMASK (0x40000420) /**< \brief (PM) APBC Mask */
|
||||
#define REG_PM_INTENCLR (0x40000434) /**< \brief (PM) Interrupt Enable Clear */
|
||||
#define REG_PM_INTENSET (0x40000435) /**< \brief (PM) Interrupt Enable Set */
|
||||
#define REG_PM_INTFLAG (0x40000436) /**< \brief (PM) Interrupt Flag Status and Clear */
|
||||
#define REG_PM_RCAUSE (0x40000438) /**< \brief (PM) Reset Cause */
|
||||
#else
|
||||
#define REG_PM_CTRL (*(RwReg8 *)0x40000400UL) /**< \brief (PM) Control */
|
||||
#define REG_PM_SLEEP (*(RwReg8 *)0x40000401UL) /**< \brief (PM) Sleep Mode */
|
||||
#define REG_PM_CPUSEL (*(RwReg8 *)0x40000408UL) /**< \brief (PM) CPU Clock Select */
|
||||
#define REG_PM_APBASEL (*(RwReg8 *)0x40000409UL) /**< \brief (PM) APBA Clock Select */
|
||||
#define REG_PM_APBBSEL (*(RwReg8 *)0x4000040AUL) /**< \brief (PM) APBB Clock Select */
|
||||
#define REG_PM_APBCSEL (*(RwReg8 *)0x4000040BUL) /**< \brief (PM) APBC Clock Select */
|
||||
#define REG_PM_AHBMASK (*(RwReg *)0x40000414UL) /**< \brief (PM) AHB Mask */
|
||||
#define REG_PM_APBAMASK (*(RwReg *)0x40000418UL) /**< \brief (PM) APBA Mask */
|
||||
#define REG_PM_APBBMASK (*(RwReg *)0x4000041CUL) /**< \brief (PM) APBB Mask */
|
||||
#define REG_PM_APBCMASK (*(RwReg *)0x40000420UL) /**< \brief (PM) APBC Mask */
|
||||
#define REG_PM_INTENCLR (*(RwReg8 *)0x40000434UL) /**< \brief (PM) Interrupt Enable Clear */
|
||||
#define REG_PM_INTENSET (*(RwReg8 *)0x40000435UL) /**< \brief (PM) Interrupt Enable Set */
|
||||
#define REG_PM_INTFLAG (*(RwReg8 *)0x40000436UL) /**< \brief (PM) Interrupt Flag Status and Clear */
|
||||
#define REG_PM_RCAUSE (*(RoReg8 *)0x40000438UL) /**< \brief (PM) Reset Cause */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PM peripheral ========== */
|
||||
#define PM_CTRL_MCSEL_DFLL48M 3
|
||||
#define PM_CTRL_MCSEL_GCLK 0
|
||||
#define PM_CTRL_MCSEL_OSC8M 1
|
||||
#define PM_CTRL_MCSEL_XOSC 2
|
||||
#define PM_PM_CLK_APB_NUM 2
|
||||
|
||||
#endif /* _SAMD21_PM_INSTANCE_ */
|
||||
|
||||
@@ -1,122 +1,122 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PORT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_INSTANCE_
|
||||
#define _SAMD21_PORT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PORT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PORT_DIR0 (0x41004400) /**< \brief (PORT) Data Direction 0 */
|
||||
#define REG_PORT_DIRCLR0 (0x41004404) /**< \brief (PORT) Data Direction Clear 0 */
|
||||
#define REG_PORT_DIRSET0 (0x41004408) /**< \brief (PORT) Data Direction Set 0 */
|
||||
#define REG_PORT_DIRTGL0 (0x4100440C) /**< \brief (PORT) Data Direction Toggle 0 */
|
||||
#define REG_PORT_OUT0 (0x41004410) /**< \brief (PORT) Data Output Value 0 */
|
||||
#define REG_PORT_OUTCLR0 (0x41004414) /**< \brief (PORT) Data Output Value Clear 0 */
|
||||
#define REG_PORT_OUTSET0 (0x41004418) /**< \brief (PORT) Data Output Value Set 0 */
|
||||
#define REG_PORT_OUTTGL0 (0x4100441C) /**< \brief (PORT) Data Output Value Toggle 0 */
|
||||
#define REG_PORT_IN0 (0x41004420) /**< \brief (PORT) Data Input Value 0 */
|
||||
#define REG_PORT_CTRL0 (0x41004424) /**< \brief (PORT) Control 0 */
|
||||
#define REG_PORT_WRCONFIG0 (0x41004428) /**< \brief (PORT) Write Configuration 0 */
|
||||
#define REG_PORT_PMUX0 (0x41004430) /**< \brief (PORT) Peripheral Multiplexing 0 */
|
||||
#define REG_PORT_PINCFG0 (0x41004440) /**< \brief (PORT) Pin Configuration 0 */
|
||||
#define REG_PORT_DIR1 (0x41004480) /**< \brief (PORT) Data Direction 1 */
|
||||
#define REG_PORT_DIRCLR1 (0x41004484) /**< \brief (PORT) Data Direction Clear 1 */
|
||||
#define REG_PORT_DIRSET1 (0x41004488) /**< \brief (PORT) Data Direction Set 1 */
|
||||
#define REG_PORT_DIRTGL1 (0x4100448C) /**< \brief (PORT) Data Direction Toggle 1 */
|
||||
#define REG_PORT_OUT1 (0x41004490) /**< \brief (PORT) Data Output Value 1 */
|
||||
#define REG_PORT_OUTCLR1 (0x41004494) /**< \brief (PORT) Data Output Value Clear 1 */
|
||||
#define REG_PORT_OUTSET1 (0x41004498) /**< \brief (PORT) Data Output Value Set 1 */
|
||||
#define REG_PORT_OUTTGL1 (0x4100449C) /**< \brief (PORT) Data Output Value Toggle 1 */
|
||||
#define REG_PORT_IN1 (0x410044A0) /**< \brief (PORT) Data Input Value 1 */
|
||||
#define REG_PORT_CTRL1 (0x410044A4) /**< \brief (PORT) Control 1 */
|
||||
#define REG_PORT_WRCONFIG1 (0x410044A8) /**< \brief (PORT) Write Configuration 1 */
|
||||
#define REG_PORT_PMUX1 (0x410044B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
|
||||
#define REG_PORT_PINCFG1 (0x410044C0) /**< \brief (PORT) Pin Configuration 1 */
|
||||
#else
|
||||
#define REG_PORT_DIR0 (*(RwReg *)0x41004400UL) /**< \brief (PORT) Data Direction 0 */
|
||||
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404UL) /**< \brief (PORT) Data Direction Clear 0 */
|
||||
#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408UL) /**< \brief (PORT) Data Direction Set 0 */
|
||||
#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CUL) /**< \brief (PORT) Data Direction Toggle 0 */
|
||||
#define REG_PORT_OUT0 (*(RwReg *)0x41004410UL) /**< \brief (PORT) Data Output Value 0 */
|
||||
#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414UL) /**< \brief (PORT) Data Output Value Clear 0 */
|
||||
#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418UL) /**< \brief (PORT) Data Output Value Set 0 */
|
||||
#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
|
||||
#define REG_PORT_IN0 (*(RoReg *)0x41004420UL) /**< \brief (PORT) Data Input Value 0 */
|
||||
#define REG_PORT_CTRL0 (*(RwReg *)0x41004424UL) /**< \brief (PORT) Control 0 */
|
||||
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428UL) /**< \brief (PORT) Write Configuration 0 */
|
||||
#define REG_PORT_PMUX0 (*(RwReg8 *)0x41004430UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
|
||||
#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41004440UL) /**< \brief (PORT) Pin Configuration 0 */
|
||||
#define REG_PORT_DIR1 (*(RwReg *)0x41004480UL) /**< \brief (PORT) Data Direction 1 */
|
||||
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484UL) /**< \brief (PORT) Data Direction Clear 1 */
|
||||
#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488UL) /**< \brief (PORT) Data Direction Set 1 */
|
||||
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CUL) /**< \brief (PORT) Data Direction Toggle 1 */
|
||||
#define REG_PORT_OUT1 (*(RwReg *)0x41004490UL) /**< \brief (PORT) Data Output Value 1 */
|
||||
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494UL) /**< \brief (PORT) Data Output Value Clear 1 */
|
||||
#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498UL) /**< \brief (PORT) Data Output Value Set 1 */
|
||||
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
|
||||
#define REG_PORT_IN1 (*(RoReg *)0x410044A0UL) /**< \brief (PORT) Data Input Value 1 */
|
||||
#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4UL) /**< \brief (PORT) Control 1 */
|
||||
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8UL) /**< \brief (PORT) Write Configuration 1 */
|
||||
#define REG_PORT_PMUX1 (*(RwReg8 *)0x410044B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
|
||||
#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410044C0UL) /**< \brief (PORT) Pin Configuration 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PORT peripheral ========== */
|
||||
#define PORT_BITS 84 // Number of PORT pins
|
||||
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
|
||||
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
|
||||
#define PORT_DRVSTR 1 // DRVSTR supported
|
||||
#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
|
||||
#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
|
||||
#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
|
||||
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
|
||||
#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
|
||||
#define PORT_ODRAIN 0 // ODRAIN supported
|
||||
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
|
||||
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
|
||||
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
|
||||
#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
|
||||
#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
|
||||
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
|
||||
#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
|
||||
#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
|
||||
#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
|
||||
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
|
||||
#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
|
||||
#define PORT_SLEWLIM 0 // SLEWLIM supported
|
||||
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
|
||||
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
|
||||
|
||||
#endif /* _SAMD21_PORT_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PORT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PORT_INSTANCE_
|
||||
#define _SAMD21_PORT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for PORT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_PORT_DIR0 (0x41004400) /**< \brief (PORT) Data Direction 0 */
|
||||
#define REG_PORT_DIRCLR0 (0x41004404) /**< \brief (PORT) Data Direction Clear 0 */
|
||||
#define REG_PORT_DIRSET0 (0x41004408) /**< \brief (PORT) Data Direction Set 0 */
|
||||
#define REG_PORT_DIRTGL0 (0x4100440C) /**< \brief (PORT) Data Direction Toggle 0 */
|
||||
#define REG_PORT_OUT0 (0x41004410) /**< \brief (PORT) Data Output Value 0 */
|
||||
#define REG_PORT_OUTCLR0 (0x41004414) /**< \brief (PORT) Data Output Value Clear 0 */
|
||||
#define REG_PORT_OUTSET0 (0x41004418) /**< \brief (PORT) Data Output Value Set 0 */
|
||||
#define REG_PORT_OUTTGL0 (0x4100441C) /**< \brief (PORT) Data Output Value Toggle 0 */
|
||||
#define REG_PORT_IN0 (0x41004420) /**< \brief (PORT) Data Input Value 0 */
|
||||
#define REG_PORT_CTRL0 (0x41004424) /**< \brief (PORT) Control 0 */
|
||||
#define REG_PORT_WRCONFIG0 (0x41004428) /**< \brief (PORT) Write Configuration 0 */
|
||||
#define REG_PORT_PMUX0 (0x41004430) /**< \brief (PORT) Peripheral Multiplexing 0 */
|
||||
#define REG_PORT_PINCFG0 (0x41004440) /**< \brief (PORT) Pin Configuration 0 */
|
||||
#define REG_PORT_DIR1 (0x41004480) /**< \brief (PORT) Data Direction 1 */
|
||||
#define REG_PORT_DIRCLR1 (0x41004484) /**< \brief (PORT) Data Direction Clear 1 */
|
||||
#define REG_PORT_DIRSET1 (0x41004488) /**< \brief (PORT) Data Direction Set 1 */
|
||||
#define REG_PORT_DIRTGL1 (0x4100448C) /**< \brief (PORT) Data Direction Toggle 1 */
|
||||
#define REG_PORT_OUT1 (0x41004490) /**< \brief (PORT) Data Output Value 1 */
|
||||
#define REG_PORT_OUTCLR1 (0x41004494) /**< \brief (PORT) Data Output Value Clear 1 */
|
||||
#define REG_PORT_OUTSET1 (0x41004498) /**< \brief (PORT) Data Output Value Set 1 */
|
||||
#define REG_PORT_OUTTGL1 (0x4100449C) /**< \brief (PORT) Data Output Value Toggle 1 */
|
||||
#define REG_PORT_IN1 (0x410044A0) /**< \brief (PORT) Data Input Value 1 */
|
||||
#define REG_PORT_CTRL1 (0x410044A4) /**< \brief (PORT) Control 1 */
|
||||
#define REG_PORT_WRCONFIG1 (0x410044A8) /**< \brief (PORT) Write Configuration 1 */
|
||||
#define REG_PORT_PMUX1 (0x410044B0) /**< \brief (PORT) Peripheral Multiplexing 1 */
|
||||
#define REG_PORT_PINCFG1 (0x410044C0) /**< \brief (PORT) Pin Configuration 1 */
|
||||
#else
|
||||
#define REG_PORT_DIR0 (*(RwReg *)0x41004400UL) /**< \brief (PORT) Data Direction 0 */
|
||||
#define REG_PORT_DIRCLR0 (*(RwReg *)0x41004404UL) /**< \brief (PORT) Data Direction Clear 0 */
|
||||
#define REG_PORT_DIRSET0 (*(RwReg *)0x41004408UL) /**< \brief (PORT) Data Direction Set 0 */
|
||||
#define REG_PORT_DIRTGL0 (*(RwReg *)0x4100440CUL) /**< \brief (PORT) Data Direction Toggle 0 */
|
||||
#define REG_PORT_OUT0 (*(RwReg *)0x41004410UL) /**< \brief (PORT) Data Output Value 0 */
|
||||
#define REG_PORT_OUTCLR0 (*(RwReg *)0x41004414UL) /**< \brief (PORT) Data Output Value Clear 0 */
|
||||
#define REG_PORT_OUTSET0 (*(RwReg *)0x41004418UL) /**< \brief (PORT) Data Output Value Set 0 */
|
||||
#define REG_PORT_OUTTGL0 (*(RwReg *)0x4100441CUL) /**< \brief (PORT) Data Output Value Toggle 0 */
|
||||
#define REG_PORT_IN0 (*(RoReg *)0x41004420UL) /**< \brief (PORT) Data Input Value 0 */
|
||||
#define REG_PORT_CTRL0 (*(RwReg *)0x41004424UL) /**< \brief (PORT) Control 0 */
|
||||
#define REG_PORT_WRCONFIG0 (*(WoReg *)0x41004428UL) /**< \brief (PORT) Write Configuration 0 */
|
||||
#define REG_PORT_PMUX0 (*(RwReg8 *)0x41004430UL) /**< \brief (PORT) Peripheral Multiplexing 0 */
|
||||
#define REG_PORT_PINCFG0 (*(RwReg8 *)0x41004440UL) /**< \brief (PORT) Pin Configuration 0 */
|
||||
#define REG_PORT_DIR1 (*(RwReg *)0x41004480UL) /**< \brief (PORT) Data Direction 1 */
|
||||
#define REG_PORT_DIRCLR1 (*(RwReg *)0x41004484UL) /**< \brief (PORT) Data Direction Clear 1 */
|
||||
#define REG_PORT_DIRSET1 (*(RwReg *)0x41004488UL) /**< \brief (PORT) Data Direction Set 1 */
|
||||
#define REG_PORT_DIRTGL1 (*(RwReg *)0x4100448CUL) /**< \brief (PORT) Data Direction Toggle 1 */
|
||||
#define REG_PORT_OUT1 (*(RwReg *)0x41004490UL) /**< \brief (PORT) Data Output Value 1 */
|
||||
#define REG_PORT_OUTCLR1 (*(RwReg *)0x41004494UL) /**< \brief (PORT) Data Output Value Clear 1 */
|
||||
#define REG_PORT_OUTSET1 (*(RwReg *)0x41004498UL) /**< \brief (PORT) Data Output Value Set 1 */
|
||||
#define REG_PORT_OUTTGL1 (*(RwReg *)0x4100449CUL) /**< \brief (PORT) Data Output Value Toggle 1 */
|
||||
#define REG_PORT_IN1 (*(RoReg *)0x410044A0UL) /**< \brief (PORT) Data Input Value 1 */
|
||||
#define REG_PORT_CTRL1 (*(RwReg *)0x410044A4UL) /**< \brief (PORT) Control 1 */
|
||||
#define REG_PORT_WRCONFIG1 (*(WoReg *)0x410044A8UL) /**< \brief (PORT) Write Configuration 1 */
|
||||
#define REG_PORT_PMUX1 (*(RwReg8 *)0x410044B0UL) /**< \brief (PORT) Peripheral Multiplexing 1 */
|
||||
#define REG_PORT_PINCFG1 (*(RwReg8 *)0x410044C0UL) /**< \brief (PORT) Pin Configuration 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for PORT peripheral ========== */
|
||||
#define PORT_BITS 84 // Number of PORT pins
|
||||
#define PORT_DIR_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for DIR of all pins
|
||||
#define PORT_DIR_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DIR of all pins
|
||||
#define PORT_DRVSTR 1 // DRVSTR supported
|
||||
#define PORT_DRVSTR_DEFAULT_VAL { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Default value for DRVSTR of all pins
|
||||
#define PORT_DRVSTR_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for DRVSTR of all pins
|
||||
#define PORT_EVENT_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 }
|
||||
#define PORT_INEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for INEN of all pins
|
||||
#define PORT_INEN_IMPLEMENTED { 0xD8FFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for INEN of all pins
|
||||
#define PORT_ODRAIN 0 // ODRAIN supported
|
||||
#define PORT_ODRAIN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for ODRAIN of all pins
|
||||
#define PORT_ODRAIN_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for ODRAIN of all pins
|
||||
#define PORT_OUT_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for OUT of all pins
|
||||
#define PORT_OUT_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for OUT of all pins
|
||||
#define PORT_PIN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for all PORT pins
|
||||
#define PORT_PMUXBIT0_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT0_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000D0000 } // Implementation mask for PMUX[0] of all pins
|
||||
#define PORT_PMUXBIT1_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT1_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x00000000 } // Implementation mask for PMUX[1] of all pins
|
||||
#define PORT_PMUXBIT2_DEFAULT_VAL { 0x40000000, 0x00000000, 0x00000000 } // Default value for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT2_IMPLEMENTED { 0xDBFFFFF3, 0xC0C3FF0F, 0x000D0000 } // Implementation mask for PMUX[2] of all pins
|
||||
#define PORT_PMUXBIT3_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PMUX[3] of all pins
|
||||
#define PORT_PMUXBIT3_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for PMUX[3] of all pins
|
||||
#define PORT_PMUXEN_DEFAULT_VAL { 0x64000000, 0x3F3C0000, 0x00000000 } // Default value for PMUXEN of all pins
|
||||
#define PORT_PMUXEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000F7FFE } // Implementation mask for PMUXEN of all pins
|
||||
#define PORT_PULLEN_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for PULLEN of all pins
|
||||
#define PORT_PULLEN_IMPLEMENTED { 0xDBFFFFFF, 0xC0C3FFFF, 0x000FFFFF } // Implementation mask for PULLEN of all pins
|
||||
#define PORT_SLEWLIM 0 // SLEWLIM supported
|
||||
#define PORT_SLEWLIM_DEFAULT_VAL { 0x00000000, 0x00000000, 0x00000000 } // Default value for SLEWLIM of all pins
|
||||
#define PORT_SLEWLIM_IMPLEMENTED { 0x00000000, 0x00000000, 0x00000000 } // Implementation mask for SLEWLIM of all pins
|
||||
|
||||
#endif /* _SAMD21_PORT_INSTANCE_ */
|
||||
|
||||
@@ -1,36 +1,36 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PTC_INSTANCE_
|
||||
#define _SAMD21_PTC_INSTANCE_
|
||||
|
||||
/* ========== Instance parameters for PTC peripheral ========== */
|
||||
#define PTC_GCLK_ID 34 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_PTC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_PTC_INSTANCE_
|
||||
#define _SAMD21_PTC_INSTANCE_
|
||||
|
||||
/* ========== Instance parameters for PTC peripheral ========== */
|
||||
#define PTC_GCLK_ID 34 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_PTC_INSTANCE_ */
|
||||
|
||||
@@ -1,103 +1,103 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for RTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_RTC_INSTANCE_
|
||||
#define _SAMD21_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_RTC_READREQ (0x40001402) /**< \brief (RTC) Read Request */
|
||||
#define REG_RTC_STATUS (0x4000140A) /**< \brief (RTC) Status */
|
||||
#define REG_RTC_DBGCTRL (0x4000140B) /**< \brief (RTC) Debug Control */
|
||||
#define REG_RTC_FREQCORR (0x4000140C) /**< \brief (RTC) Frequency Correction */
|
||||
#define REG_RTC_MODE0_CTRL (0x40001400) /**< \brief (RTC) MODE0 Control */
|
||||
#define REG_RTC_MODE0_EVCTRL (0x40001404) /**< \brief (RTC) MODE0 Event Control */
|
||||
#define REG_RTC_MODE0_INTENCLR (0x40001406) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE0_INTENSET (0x40001407) /**< \brief (RTC) MODE0 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE0_INTFLAG (0x40001408) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE0_COUNT (0x40001410) /**< \brief (RTC) MODE0 Counter Value */
|
||||
#define REG_RTC_MODE0_COMP0 (0x40001418) /**< \brief (RTC) MODE0 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_CTRL (0x40001400) /**< \brief (RTC) MODE1 Control */
|
||||
#define REG_RTC_MODE1_EVCTRL (0x40001404) /**< \brief (RTC) MODE1 Event Control */
|
||||
#define REG_RTC_MODE1_INTENCLR (0x40001406) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE1_INTENSET (0x40001407) /**< \brief (RTC) MODE1 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE1_INTFLAG (0x40001408) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE1_COUNT (0x40001410) /**< \brief (RTC) MODE1 Counter Value */
|
||||
#define REG_RTC_MODE1_PER (0x40001414) /**< \brief (RTC) MODE1 Counter Period */
|
||||
#define REG_RTC_MODE1_COMP0 (0x40001418) /**< \brief (RTC) MODE1 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_COMP1 (0x4000141A) /**< \brief (RTC) MODE1 Compare 1 Value */
|
||||
#define REG_RTC_MODE2_CTRL (0x40001400) /**< \brief (RTC) MODE2 Control */
|
||||
#define REG_RTC_MODE2_EVCTRL (0x40001404) /**< \brief (RTC) MODE2 Event Control */
|
||||
#define REG_RTC_MODE2_INTENCLR (0x40001406) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE2_INTENSET (0x40001407) /**< \brief (RTC) MODE2 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE2_INTFLAG (0x40001408) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE2_CLOCK (0x40001410) /**< \brief (RTC) MODE2 Clock Value */
|
||||
#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
|
||||
#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141C) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
|
||||
#else
|
||||
#define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */
|
||||
#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AUL) /**< \brief (RTC) Status */
|
||||
#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BUL) /**< \brief (RTC) Debug Control */
|
||||
#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CUL) /**< \brief (RTC) Frequency Correction */
|
||||
#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */
|
||||
#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control */
|
||||
#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE0 Counter Value */
|
||||
#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE0 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */
|
||||
#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control */
|
||||
#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value */
|
||||
#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period */
|
||||
#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Value */
|
||||
#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */
|
||||
#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE2 Event Control */
|
||||
#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE2 Clock Value */
|
||||
#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
|
||||
#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x4000141CUL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for RTC peripheral ========== */
|
||||
#define RTC_ALARM_NUM 1 // Number of Alarms
|
||||
#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
|
||||
#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
|
||||
#define RTC_GCLK_ID 4 // Index of Generic Clock
|
||||
#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete)
|
||||
#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
|
||||
#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
|
||||
|
||||
#endif /* _SAMD21_RTC_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for RTC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_RTC_INSTANCE_
|
||||
#define _SAMD21_RTC_INSTANCE_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_RTC_READREQ (0x40001402) /**< \brief (RTC) Read Request */
|
||||
#define REG_RTC_STATUS (0x4000140A) /**< \brief (RTC) Status */
|
||||
#define REG_RTC_DBGCTRL (0x4000140B) /**< \brief (RTC) Debug Control */
|
||||
#define REG_RTC_FREQCORR (0x4000140C) /**< \brief (RTC) Frequency Correction */
|
||||
#define REG_RTC_MODE0_CTRL (0x40001400) /**< \brief (RTC) MODE0 Control */
|
||||
#define REG_RTC_MODE0_EVCTRL (0x40001404) /**< \brief (RTC) MODE0 Event Control */
|
||||
#define REG_RTC_MODE0_INTENCLR (0x40001406) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE0_INTENSET (0x40001407) /**< \brief (RTC) MODE0 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE0_INTFLAG (0x40001408) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE0_COUNT (0x40001410) /**< \brief (RTC) MODE0 Counter Value */
|
||||
#define REG_RTC_MODE0_COMP0 (0x40001418) /**< \brief (RTC) MODE0 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_CTRL (0x40001400) /**< \brief (RTC) MODE1 Control */
|
||||
#define REG_RTC_MODE1_EVCTRL (0x40001404) /**< \brief (RTC) MODE1 Event Control */
|
||||
#define REG_RTC_MODE1_INTENCLR (0x40001406) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE1_INTENSET (0x40001407) /**< \brief (RTC) MODE1 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE1_INTFLAG (0x40001408) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE1_COUNT (0x40001410) /**< \brief (RTC) MODE1 Counter Value */
|
||||
#define REG_RTC_MODE1_PER (0x40001414) /**< \brief (RTC) MODE1 Counter Period */
|
||||
#define REG_RTC_MODE1_COMP0 (0x40001418) /**< \brief (RTC) MODE1 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_COMP1 (0x4000141A) /**< \brief (RTC) MODE1 Compare 1 Value */
|
||||
#define REG_RTC_MODE2_CTRL (0x40001400) /**< \brief (RTC) MODE2 Control */
|
||||
#define REG_RTC_MODE2_EVCTRL (0x40001404) /**< \brief (RTC) MODE2 Event Control */
|
||||
#define REG_RTC_MODE2_INTENCLR (0x40001406) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE2_INTENSET (0x40001407) /**< \brief (RTC) MODE2 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE2_INTFLAG (0x40001408) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE2_CLOCK (0x40001410) /**< \brief (RTC) MODE2 Clock Value */
|
||||
#define REG_RTC_MODE2_ALARM_ALARM0 (0x40001418) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
|
||||
#define REG_RTC_MODE2_ALARM_MASK0 (0x4000141C) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
|
||||
#else
|
||||
#define REG_RTC_READREQ (*(RwReg16*)0x40001402UL) /**< \brief (RTC) Read Request */
|
||||
#define REG_RTC_STATUS (*(RwReg8 *)0x4000140AUL) /**< \brief (RTC) Status */
|
||||
#define REG_RTC_DBGCTRL (*(RwReg8 *)0x4000140BUL) /**< \brief (RTC) Debug Control */
|
||||
#define REG_RTC_FREQCORR (*(RwReg8 *)0x4000140CUL) /**< \brief (RTC) Frequency Correction */
|
||||
#define REG_RTC_MODE0_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE0 Control */
|
||||
#define REG_RTC_MODE0_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE0 Event Control */
|
||||
#define REG_RTC_MODE0_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE0 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE0_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE0 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE0_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE0 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE0_COUNT (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE0 Counter Value */
|
||||
#define REG_RTC_MODE0_COMP0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE0 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE1 Control */
|
||||
#define REG_RTC_MODE1_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE1 Event Control */
|
||||
#define REG_RTC_MODE1_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE1 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE1_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE1 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE1_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE1 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE1_COUNT (*(RwReg16*)0x40001410UL) /**< \brief (RTC) MODE1 Counter Value */
|
||||
#define REG_RTC_MODE1_PER (*(RwReg16*)0x40001414UL) /**< \brief (RTC) MODE1 Counter Period */
|
||||
#define REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40001418UL) /**< \brief (RTC) MODE1 Compare 0 Value */
|
||||
#define REG_RTC_MODE1_COMP1 (*(RwReg16*)0x4000141AUL) /**< \brief (RTC) MODE1 Compare 1 Value */
|
||||
#define REG_RTC_MODE2_CTRL (*(RwReg16*)0x40001400UL) /**< \brief (RTC) MODE2 Control */
|
||||
#define REG_RTC_MODE2_EVCTRL (*(RwReg16*)0x40001404UL) /**< \brief (RTC) MODE2 Event Control */
|
||||
#define REG_RTC_MODE2_INTENCLR (*(RwReg8 *)0x40001406UL) /**< \brief (RTC) MODE2 Interrupt Enable Clear */
|
||||
#define REG_RTC_MODE2_INTENSET (*(RwReg8 *)0x40001407UL) /**< \brief (RTC) MODE2 Interrupt Enable Set */
|
||||
#define REG_RTC_MODE2_INTFLAG (*(RwReg8 *)0x40001408UL) /**< \brief (RTC) MODE2 Interrupt Flag Status and Clear */
|
||||
#define REG_RTC_MODE2_CLOCK (*(RwReg *)0x40001410UL) /**< \brief (RTC) MODE2 Clock Value */
|
||||
#define REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40001418UL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Value */
|
||||
#define REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x4000141CUL) /**< \brief (RTC) MODE2_ALARM Alarm 0 Mask */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for RTC peripheral ========== */
|
||||
#define RTC_ALARM_NUM 1 // Number of Alarms
|
||||
#define RTC_COMP16_NUM 2 // Number of 16-bit Comparators
|
||||
#define RTC_COMP32_NUM 1 // Number of 32-bit Comparators
|
||||
#define RTC_GCLK_ID 4 // Index of Generic Clock
|
||||
#define RTC_NUM_OF_ALARMS 1 // Number of Alarms (obsolete)
|
||||
#define RTC_NUM_OF_COMP16 2 // Number of 16-bit Comparators (obsolete)
|
||||
#define RTC_NUM_OF_COMP32 1 // Number of 32-bit Comparators (obsolete)
|
||||
|
||||
#endif /* _SAMD21_RTC_INSTANCE_ */
|
||||
|
||||
@@ -1,151 +1,151 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SBMATRIX
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SBMATRIX_INSTANCE_
|
||||
#define _SAMD21_SBMATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SBMATRIX peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SBMATRIX_PRAS0 (0x41007080) /**< \brief (SBMATRIX) Priority A for Slave 0 */
|
||||
#define REG_SBMATRIX_PRBS0 (0x41007084) /**< \brief (SBMATRIX) Priority B for Slave 0 */
|
||||
#define REG_SBMATRIX_PRAS1 (0x41007088) /**< \brief (SBMATRIX) Priority A for Slave 1 */
|
||||
#define REG_SBMATRIX_PRBS1 (0x4100708C) /**< \brief (SBMATRIX) Priority B for Slave 1 */
|
||||
#define REG_SBMATRIX_PRAS2 (0x41007090) /**< \brief (SBMATRIX) Priority A for Slave 2 */
|
||||
#define REG_SBMATRIX_PRBS2 (0x41007094) /**< \brief (SBMATRIX) Priority B for Slave 2 */
|
||||
#define REG_SBMATRIX_PRAS3 (0x41007098) /**< \brief (SBMATRIX) Priority A for Slave 3 */
|
||||
#define REG_SBMATRIX_PRBS3 (0x4100709C) /**< \brief (SBMATRIX) Priority B for Slave 3 */
|
||||
#define REG_SBMATRIX_PRAS4 (0x410070A0) /**< \brief (SBMATRIX) Priority A for Slave 4 */
|
||||
#define REG_SBMATRIX_PRBS4 (0x410070A4) /**< \brief (SBMATRIX) Priority B for Slave 4 */
|
||||
#define REG_SBMATRIX_PRAS5 (0x410070A8) /**< \brief (SBMATRIX) Priority A for Slave 5 */
|
||||
#define REG_SBMATRIX_PRBS5 (0x410070AC) /**< \brief (SBMATRIX) Priority B for Slave 5 */
|
||||
#define REG_SBMATRIX_PRAS6 (0x410070B0) /**< \brief (SBMATRIX) Priority A for Slave 6 */
|
||||
#define REG_SBMATRIX_PRBS6 (0x410070B4) /**< \brief (SBMATRIX) Priority B for Slave 6 */
|
||||
#define REG_SBMATRIX_PRAS7 (0x410070B8) /**< \brief (SBMATRIX) Priority A for Slave 7 */
|
||||
#define REG_SBMATRIX_PRBS7 (0x410070BC) /**< \brief (SBMATRIX) Priority B for Slave 7 */
|
||||
#define REG_SBMATRIX_PRAS8 (0x410070C0) /**< \brief (SBMATRIX) Priority A for Slave 8 */
|
||||
#define REG_SBMATRIX_PRBS8 (0x410070C4) /**< \brief (SBMATRIX) Priority B for Slave 8 */
|
||||
#define REG_SBMATRIX_PRAS9 (0x410070C8) /**< \brief (SBMATRIX) Priority A for Slave 9 */
|
||||
#define REG_SBMATRIX_PRBS9 (0x410070CC) /**< \brief (SBMATRIX) Priority B for Slave 9 */
|
||||
#define REG_SBMATRIX_PRAS10 (0x410070D0) /**< \brief (SBMATRIX) Priority A for Slave 10 */
|
||||
#define REG_SBMATRIX_PRBS10 (0x410070D4) /**< \brief (SBMATRIX) Priority B for Slave 10 */
|
||||
#define REG_SBMATRIX_PRAS11 (0x410070D8) /**< \brief (SBMATRIX) Priority A for Slave 11 */
|
||||
#define REG_SBMATRIX_PRBS11 (0x410070DC) /**< \brief (SBMATRIX) Priority B for Slave 11 */
|
||||
#define REG_SBMATRIX_PRAS12 (0x410070E0) /**< \brief (SBMATRIX) Priority A for Slave 12 */
|
||||
#define REG_SBMATRIX_PRBS12 (0x410070E4) /**< \brief (SBMATRIX) Priority B for Slave 12 */
|
||||
#define REG_SBMATRIX_PRAS13 (0x410070E8) /**< \brief (SBMATRIX) Priority A for Slave 13 */
|
||||
#define REG_SBMATRIX_PRBS13 (0x410070EC) /**< \brief (SBMATRIX) Priority B for Slave 13 */
|
||||
#define REG_SBMATRIX_PRAS14 (0x410070F0) /**< \brief (SBMATRIX) Priority A for Slave 14 */
|
||||
#define REG_SBMATRIX_PRBS14 (0x410070F4) /**< \brief (SBMATRIX) Priority B for Slave 14 */
|
||||
#define REG_SBMATRIX_PRAS15 (0x410070F8) /**< \brief (SBMATRIX) Priority A for Slave 15 */
|
||||
#define REG_SBMATRIX_PRBS15 (0x410070FC) /**< \brief (SBMATRIX) Priority B for Slave 15 */
|
||||
#define REG_SBMATRIX_SFR0 (0x41007110) /**< \brief (SBMATRIX) Special Function 0 */
|
||||
#define REG_SBMATRIX_SFR1 (0x41007114) /**< \brief (SBMATRIX) Special Function 1 */
|
||||
#define REG_SBMATRIX_SFR2 (0x41007118) /**< \brief (SBMATRIX) Special Function 2 */
|
||||
#define REG_SBMATRIX_SFR3 (0x4100711C) /**< \brief (SBMATRIX) Special Function 3 */
|
||||
#define REG_SBMATRIX_SFR4 (0x41007120) /**< \brief (SBMATRIX) Special Function 4 */
|
||||
#define REG_SBMATRIX_SFR5 (0x41007124) /**< \brief (SBMATRIX) Special Function 5 */
|
||||
#define REG_SBMATRIX_SFR6 (0x41007128) /**< \brief (SBMATRIX) Special Function 6 */
|
||||
#define REG_SBMATRIX_SFR7 (0x4100712C) /**< \brief (SBMATRIX) Special Function 7 */
|
||||
#define REG_SBMATRIX_SFR8 (0x41007130) /**< \brief (SBMATRIX) Special Function 8 */
|
||||
#define REG_SBMATRIX_SFR9 (0x41007134) /**< \brief (SBMATRIX) Special Function 9 */
|
||||
#define REG_SBMATRIX_SFR10 (0x41007138) /**< \brief (SBMATRIX) Special Function 10 */
|
||||
#define REG_SBMATRIX_SFR11 (0x4100713C) /**< \brief (SBMATRIX) Special Function 11 */
|
||||
#define REG_SBMATRIX_SFR12 (0x41007140) /**< \brief (SBMATRIX) Special Function 12 */
|
||||
#define REG_SBMATRIX_SFR13 (0x41007144) /**< \brief (SBMATRIX) Special Function 13 */
|
||||
#define REG_SBMATRIX_SFR14 (0x41007148) /**< \brief (SBMATRIX) Special Function 14 */
|
||||
#define REG_SBMATRIX_SFR15 (0x4100714C) /**< \brief (SBMATRIX) Special Function 15 */
|
||||
#else
|
||||
#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080UL) /**< \brief (SBMATRIX) Priority A for Slave 0 */
|
||||
#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084UL) /**< \brief (SBMATRIX) Priority B for Slave 0 */
|
||||
#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088UL) /**< \brief (SBMATRIX) Priority A for Slave 1 */
|
||||
#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CUL) /**< \brief (SBMATRIX) Priority B for Slave 1 */
|
||||
#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090UL) /**< \brief (SBMATRIX) Priority A for Slave 2 */
|
||||
#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094UL) /**< \brief (SBMATRIX) Priority B for Slave 2 */
|
||||
#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098UL) /**< \brief (SBMATRIX) Priority A for Slave 3 */
|
||||
#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CUL) /**< \brief (SBMATRIX) Priority B for Slave 3 */
|
||||
#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0UL) /**< \brief (SBMATRIX) Priority A for Slave 4 */
|
||||
#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4UL) /**< \brief (SBMATRIX) Priority B for Slave 4 */
|
||||
#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8UL) /**< \brief (SBMATRIX) Priority A for Slave 5 */
|
||||
#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACUL) /**< \brief (SBMATRIX) Priority B for Slave 5 */
|
||||
#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0UL) /**< \brief (SBMATRIX) Priority A for Slave 6 */
|
||||
#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4UL) /**< \brief (SBMATRIX) Priority B for Slave 6 */
|
||||
#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8UL) /**< \brief (SBMATRIX) Priority A for Slave 7 */
|
||||
#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCUL) /**< \brief (SBMATRIX) Priority B for Slave 7 */
|
||||
#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0UL) /**< \brief (SBMATRIX) Priority A for Slave 8 */
|
||||
#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4UL) /**< \brief (SBMATRIX) Priority B for Slave 8 */
|
||||
#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8UL) /**< \brief (SBMATRIX) Priority A for Slave 9 */
|
||||
#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCUL) /**< \brief (SBMATRIX) Priority B for Slave 9 */
|
||||
#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0UL) /**< \brief (SBMATRIX) Priority A for Slave 10 */
|
||||
#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4UL) /**< \brief (SBMATRIX) Priority B for Slave 10 */
|
||||
#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8UL) /**< \brief (SBMATRIX) Priority A for Slave 11 */
|
||||
#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCUL) /**< \brief (SBMATRIX) Priority B for Slave 11 */
|
||||
#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0UL) /**< \brief (SBMATRIX) Priority A for Slave 12 */
|
||||
#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4UL) /**< \brief (SBMATRIX) Priority B for Slave 12 */
|
||||
#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8UL) /**< \brief (SBMATRIX) Priority A for Slave 13 */
|
||||
#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECUL) /**< \brief (SBMATRIX) Priority B for Slave 13 */
|
||||
#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0UL) /**< \brief (SBMATRIX) Priority A for Slave 14 */
|
||||
#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4UL) /**< \brief (SBMATRIX) Priority B for Slave 14 */
|
||||
#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8UL) /**< \brief (SBMATRIX) Priority A for Slave 15 */
|
||||
#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCUL) /**< \brief (SBMATRIX) Priority B for Slave 15 */
|
||||
#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110UL) /**< \brief (SBMATRIX) Special Function 0 */
|
||||
#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114UL) /**< \brief (SBMATRIX) Special Function 1 */
|
||||
#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118UL) /**< \brief (SBMATRIX) Special Function 2 */
|
||||
#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CUL) /**< \brief (SBMATRIX) Special Function 3 */
|
||||
#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120UL) /**< \brief (SBMATRIX) Special Function 4 */
|
||||
#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124UL) /**< \brief (SBMATRIX) Special Function 5 */
|
||||
#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128UL) /**< \brief (SBMATRIX) Special Function 6 */
|
||||
#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CUL) /**< \brief (SBMATRIX) Special Function 7 */
|
||||
#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130UL) /**< \brief (SBMATRIX) Special Function 8 */
|
||||
#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134UL) /**< \brief (SBMATRIX) Special Function 9 */
|
||||
#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138UL) /**< \brief (SBMATRIX) Special Function 10 */
|
||||
#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CUL) /**< \brief (SBMATRIX) Special Function 11 */
|
||||
#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140UL) /**< \brief (SBMATRIX) Special Function 12 */
|
||||
#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144UL) /**< \brief (SBMATRIX) Special Function 13 */
|
||||
#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148UL) /**< \brief (SBMATRIX) Special Function 14 */
|
||||
#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CUL) /**< \brief (SBMATRIX) Special Function 15 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SBMATRIX peripheral ========== */
|
||||
#define SBMATRIX_DEFINED
|
||||
/* ========== Instance parameters for SBMATRIX ========== */
|
||||
#define SBMATRIX_SLAVE_FLASH 0
|
||||
#define SBMATRIX_SLAVE_HPB0 1
|
||||
#define SBMATRIX_SLAVE_HPB1 2
|
||||
#define SBMATRIX_SLAVE_HPB2 3
|
||||
#define SBMATRIX_SLAVE_HMCRAMC0 4
|
||||
#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
|
||||
#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
|
||||
#define SBMATRIX_SLAVE_NUM 7
|
||||
|
||||
#define SBMATRIX_MASTER_CM0PLUS 0
|
||||
#define SBMATRIX_MASTER_DSU 1
|
||||
#define SBMATRIX_MASTER_DMAC 2
|
||||
#define SBMATRIX_MASTER_NUM 3
|
||||
|
||||
#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SBMATRIX
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SBMATRIX_INSTANCE_
|
||||
#define _SAMD21_SBMATRIX_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SBMATRIX peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SBMATRIX_PRAS0 (0x41007080) /**< \brief (SBMATRIX) Priority A for Slave 0 */
|
||||
#define REG_SBMATRIX_PRBS0 (0x41007084) /**< \brief (SBMATRIX) Priority B for Slave 0 */
|
||||
#define REG_SBMATRIX_PRAS1 (0x41007088) /**< \brief (SBMATRIX) Priority A for Slave 1 */
|
||||
#define REG_SBMATRIX_PRBS1 (0x4100708C) /**< \brief (SBMATRIX) Priority B for Slave 1 */
|
||||
#define REG_SBMATRIX_PRAS2 (0x41007090) /**< \brief (SBMATRIX) Priority A for Slave 2 */
|
||||
#define REG_SBMATRIX_PRBS2 (0x41007094) /**< \brief (SBMATRIX) Priority B for Slave 2 */
|
||||
#define REG_SBMATRIX_PRAS3 (0x41007098) /**< \brief (SBMATRIX) Priority A for Slave 3 */
|
||||
#define REG_SBMATRIX_PRBS3 (0x4100709C) /**< \brief (SBMATRIX) Priority B for Slave 3 */
|
||||
#define REG_SBMATRIX_PRAS4 (0x410070A0) /**< \brief (SBMATRIX) Priority A for Slave 4 */
|
||||
#define REG_SBMATRIX_PRBS4 (0x410070A4) /**< \brief (SBMATRIX) Priority B for Slave 4 */
|
||||
#define REG_SBMATRIX_PRAS5 (0x410070A8) /**< \brief (SBMATRIX) Priority A for Slave 5 */
|
||||
#define REG_SBMATRIX_PRBS5 (0x410070AC) /**< \brief (SBMATRIX) Priority B for Slave 5 */
|
||||
#define REG_SBMATRIX_PRAS6 (0x410070B0) /**< \brief (SBMATRIX) Priority A for Slave 6 */
|
||||
#define REG_SBMATRIX_PRBS6 (0x410070B4) /**< \brief (SBMATRIX) Priority B for Slave 6 */
|
||||
#define REG_SBMATRIX_PRAS7 (0x410070B8) /**< \brief (SBMATRIX) Priority A for Slave 7 */
|
||||
#define REG_SBMATRIX_PRBS7 (0x410070BC) /**< \brief (SBMATRIX) Priority B for Slave 7 */
|
||||
#define REG_SBMATRIX_PRAS8 (0x410070C0) /**< \brief (SBMATRIX) Priority A for Slave 8 */
|
||||
#define REG_SBMATRIX_PRBS8 (0x410070C4) /**< \brief (SBMATRIX) Priority B for Slave 8 */
|
||||
#define REG_SBMATRIX_PRAS9 (0x410070C8) /**< \brief (SBMATRIX) Priority A for Slave 9 */
|
||||
#define REG_SBMATRIX_PRBS9 (0x410070CC) /**< \brief (SBMATRIX) Priority B for Slave 9 */
|
||||
#define REG_SBMATRIX_PRAS10 (0x410070D0) /**< \brief (SBMATRIX) Priority A for Slave 10 */
|
||||
#define REG_SBMATRIX_PRBS10 (0x410070D4) /**< \brief (SBMATRIX) Priority B for Slave 10 */
|
||||
#define REG_SBMATRIX_PRAS11 (0x410070D8) /**< \brief (SBMATRIX) Priority A for Slave 11 */
|
||||
#define REG_SBMATRIX_PRBS11 (0x410070DC) /**< \brief (SBMATRIX) Priority B for Slave 11 */
|
||||
#define REG_SBMATRIX_PRAS12 (0x410070E0) /**< \brief (SBMATRIX) Priority A for Slave 12 */
|
||||
#define REG_SBMATRIX_PRBS12 (0x410070E4) /**< \brief (SBMATRIX) Priority B for Slave 12 */
|
||||
#define REG_SBMATRIX_PRAS13 (0x410070E8) /**< \brief (SBMATRIX) Priority A for Slave 13 */
|
||||
#define REG_SBMATRIX_PRBS13 (0x410070EC) /**< \brief (SBMATRIX) Priority B for Slave 13 */
|
||||
#define REG_SBMATRIX_PRAS14 (0x410070F0) /**< \brief (SBMATRIX) Priority A for Slave 14 */
|
||||
#define REG_SBMATRIX_PRBS14 (0x410070F4) /**< \brief (SBMATRIX) Priority B for Slave 14 */
|
||||
#define REG_SBMATRIX_PRAS15 (0x410070F8) /**< \brief (SBMATRIX) Priority A for Slave 15 */
|
||||
#define REG_SBMATRIX_PRBS15 (0x410070FC) /**< \brief (SBMATRIX) Priority B for Slave 15 */
|
||||
#define REG_SBMATRIX_SFR0 (0x41007110) /**< \brief (SBMATRIX) Special Function 0 */
|
||||
#define REG_SBMATRIX_SFR1 (0x41007114) /**< \brief (SBMATRIX) Special Function 1 */
|
||||
#define REG_SBMATRIX_SFR2 (0x41007118) /**< \brief (SBMATRIX) Special Function 2 */
|
||||
#define REG_SBMATRIX_SFR3 (0x4100711C) /**< \brief (SBMATRIX) Special Function 3 */
|
||||
#define REG_SBMATRIX_SFR4 (0x41007120) /**< \brief (SBMATRIX) Special Function 4 */
|
||||
#define REG_SBMATRIX_SFR5 (0x41007124) /**< \brief (SBMATRIX) Special Function 5 */
|
||||
#define REG_SBMATRIX_SFR6 (0x41007128) /**< \brief (SBMATRIX) Special Function 6 */
|
||||
#define REG_SBMATRIX_SFR7 (0x4100712C) /**< \brief (SBMATRIX) Special Function 7 */
|
||||
#define REG_SBMATRIX_SFR8 (0x41007130) /**< \brief (SBMATRIX) Special Function 8 */
|
||||
#define REG_SBMATRIX_SFR9 (0x41007134) /**< \brief (SBMATRIX) Special Function 9 */
|
||||
#define REG_SBMATRIX_SFR10 (0x41007138) /**< \brief (SBMATRIX) Special Function 10 */
|
||||
#define REG_SBMATRIX_SFR11 (0x4100713C) /**< \brief (SBMATRIX) Special Function 11 */
|
||||
#define REG_SBMATRIX_SFR12 (0x41007140) /**< \brief (SBMATRIX) Special Function 12 */
|
||||
#define REG_SBMATRIX_SFR13 (0x41007144) /**< \brief (SBMATRIX) Special Function 13 */
|
||||
#define REG_SBMATRIX_SFR14 (0x41007148) /**< \brief (SBMATRIX) Special Function 14 */
|
||||
#define REG_SBMATRIX_SFR15 (0x4100714C) /**< \brief (SBMATRIX) Special Function 15 */
|
||||
#else
|
||||
#define REG_SBMATRIX_PRAS0 (*(RwReg *)0x41007080UL) /**< \brief (SBMATRIX) Priority A for Slave 0 */
|
||||
#define REG_SBMATRIX_PRBS0 (*(RwReg *)0x41007084UL) /**< \brief (SBMATRIX) Priority B for Slave 0 */
|
||||
#define REG_SBMATRIX_PRAS1 (*(RwReg *)0x41007088UL) /**< \brief (SBMATRIX) Priority A for Slave 1 */
|
||||
#define REG_SBMATRIX_PRBS1 (*(RwReg *)0x4100708CUL) /**< \brief (SBMATRIX) Priority B for Slave 1 */
|
||||
#define REG_SBMATRIX_PRAS2 (*(RwReg *)0x41007090UL) /**< \brief (SBMATRIX) Priority A for Slave 2 */
|
||||
#define REG_SBMATRIX_PRBS2 (*(RwReg *)0x41007094UL) /**< \brief (SBMATRIX) Priority B for Slave 2 */
|
||||
#define REG_SBMATRIX_PRAS3 (*(RwReg *)0x41007098UL) /**< \brief (SBMATRIX) Priority A for Slave 3 */
|
||||
#define REG_SBMATRIX_PRBS3 (*(RwReg *)0x4100709CUL) /**< \brief (SBMATRIX) Priority B for Slave 3 */
|
||||
#define REG_SBMATRIX_PRAS4 (*(RwReg *)0x410070A0UL) /**< \brief (SBMATRIX) Priority A for Slave 4 */
|
||||
#define REG_SBMATRIX_PRBS4 (*(RwReg *)0x410070A4UL) /**< \brief (SBMATRIX) Priority B for Slave 4 */
|
||||
#define REG_SBMATRIX_PRAS5 (*(RwReg *)0x410070A8UL) /**< \brief (SBMATRIX) Priority A for Slave 5 */
|
||||
#define REG_SBMATRIX_PRBS5 (*(RwReg *)0x410070ACUL) /**< \brief (SBMATRIX) Priority B for Slave 5 */
|
||||
#define REG_SBMATRIX_PRAS6 (*(RwReg *)0x410070B0UL) /**< \brief (SBMATRIX) Priority A for Slave 6 */
|
||||
#define REG_SBMATRIX_PRBS6 (*(RwReg *)0x410070B4UL) /**< \brief (SBMATRIX) Priority B for Slave 6 */
|
||||
#define REG_SBMATRIX_PRAS7 (*(RwReg *)0x410070B8UL) /**< \brief (SBMATRIX) Priority A for Slave 7 */
|
||||
#define REG_SBMATRIX_PRBS7 (*(RwReg *)0x410070BCUL) /**< \brief (SBMATRIX) Priority B for Slave 7 */
|
||||
#define REG_SBMATRIX_PRAS8 (*(RwReg *)0x410070C0UL) /**< \brief (SBMATRIX) Priority A for Slave 8 */
|
||||
#define REG_SBMATRIX_PRBS8 (*(RwReg *)0x410070C4UL) /**< \brief (SBMATRIX) Priority B for Slave 8 */
|
||||
#define REG_SBMATRIX_PRAS9 (*(RwReg *)0x410070C8UL) /**< \brief (SBMATRIX) Priority A for Slave 9 */
|
||||
#define REG_SBMATRIX_PRBS9 (*(RwReg *)0x410070CCUL) /**< \brief (SBMATRIX) Priority B for Slave 9 */
|
||||
#define REG_SBMATRIX_PRAS10 (*(RwReg *)0x410070D0UL) /**< \brief (SBMATRIX) Priority A for Slave 10 */
|
||||
#define REG_SBMATRIX_PRBS10 (*(RwReg *)0x410070D4UL) /**< \brief (SBMATRIX) Priority B for Slave 10 */
|
||||
#define REG_SBMATRIX_PRAS11 (*(RwReg *)0x410070D8UL) /**< \brief (SBMATRIX) Priority A for Slave 11 */
|
||||
#define REG_SBMATRIX_PRBS11 (*(RwReg *)0x410070DCUL) /**< \brief (SBMATRIX) Priority B for Slave 11 */
|
||||
#define REG_SBMATRIX_PRAS12 (*(RwReg *)0x410070E0UL) /**< \brief (SBMATRIX) Priority A for Slave 12 */
|
||||
#define REG_SBMATRIX_PRBS12 (*(RwReg *)0x410070E4UL) /**< \brief (SBMATRIX) Priority B for Slave 12 */
|
||||
#define REG_SBMATRIX_PRAS13 (*(RwReg *)0x410070E8UL) /**< \brief (SBMATRIX) Priority A for Slave 13 */
|
||||
#define REG_SBMATRIX_PRBS13 (*(RwReg *)0x410070ECUL) /**< \brief (SBMATRIX) Priority B for Slave 13 */
|
||||
#define REG_SBMATRIX_PRAS14 (*(RwReg *)0x410070F0UL) /**< \brief (SBMATRIX) Priority A for Slave 14 */
|
||||
#define REG_SBMATRIX_PRBS14 (*(RwReg *)0x410070F4UL) /**< \brief (SBMATRIX) Priority B for Slave 14 */
|
||||
#define REG_SBMATRIX_PRAS15 (*(RwReg *)0x410070F8UL) /**< \brief (SBMATRIX) Priority A for Slave 15 */
|
||||
#define REG_SBMATRIX_PRBS15 (*(RwReg *)0x410070FCUL) /**< \brief (SBMATRIX) Priority B for Slave 15 */
|
||||
#define REG_SBMATRIX_SFR0 (*(RwReg *)0x41007110UL) /**< \brief (SBMATRIX) Special Function 0 */
|
||||
#define REG_SBMATRIX_SFR1 (*(RwReg *)0x41007114UL) /**< \brief (SBMATRIX) Special Function 1 */
|
||||
#define REG_SBMATRIX_SFR2 (*(RwReg *)0x41007118UL) /**< \brief (SBMATRIX) Special Function 2 */
|
||||
#define REG_SBMATRIX_SFR3 (*(RwReg *)0x4100711CUL) /**< \brief (SBMATRIX) Special Function 3 */
|
||||
#define REG_SBMATRIX_SFR4 (*(RwReg *)0x41007120UL) /**< \brief (SBMATRIX) Special Function 4 */
|
||||
#define REG_SBMATRIX_SFR5 (*(RwReg *)0x41007124UL) /**< \brief (SBMATRIX) Special Function 5 */
|
||||
#define REG_SBMATRIX_SFR6 (*(RwReg *)0x41007128UL) /**< \brief (SBMATRIX) Special Function 6 */
|
||||
#define REG_SBMATRIX_SFR7 (*(RwReg *)0x4100712CUL) /**< \brief (SBMATRIX) Special Function 7 */
|
||||
#define REG_SBMATRIX_SFR8 (*(RwReg *)0x41007130UL) /**< \brief (SBMATRIX) Special Function 8 */
|
||||
#define REG_SBMATRIX_SFR9 (*(RwReg *)0x41007134UL) /**< \brief (SBMATRIX) Special Function 9 */
|
||||
#define REG_SBMATRIX_SFR10 (*(RwReg *)0x41007138UL) /**< \brief (SBMATRIX) Special Function 10 */
|
||||
#define REG_SBMATRIX_SFR11 (*(RwReg *)0x4100713CUL) /**< \brief (SBMATRIX) Special Function 11 */
|
||||
#define REG_SBMATRIX_SFR12 (*(RwReg *)0x41007140UL) /**< \brief (SBMATRIX) Special Function 12 */
|
||||
#define REG_SBMATRIX_SFR13 (*(RwReg *)0x41007144UL) /**< \brief (SBMATRIX) Special Function 13 */
|
||||
#define REG_SBMATRIX_SFR14 (*(RwReg *)0x41007148UL) /**< \brief (SBMATRIX) Special Function 14 */
|
||||
#define REG_SBMATRIX_SFR15 (*(RwReg *)0x4100714CUL) /**< \brief (SBMATRIX) Special Function 15 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SBMATRIX peripheral ========== */
|
||||
#define SBMATRIX_DEFINED
|
||||
/* ========== Instance parameters for SBMATRIX ========== */
|
||||
#define SBMATRIX_SLAVE_FLASH 0
|
||||
#define SBMATRIX_SLAVE_HPB0 1
|
||||
#define SBMATRIX_SLAVE_HPB1 2
|
||||
#define SBMATRIX_SLAVE_HPB2 3
|
||||
#define SBMATRIX_SLAVE_HMCRAMC0 4
|
||||
#define SBMATRIX_SLAVE_HMCRAMC0_ALT0 5
|
||||
#define SBMATRIX_SLAVE_HMCRAMC0_ALT1 6
|
||||
#define SBMATRIX_SLAVE_NUM 7
|
||||
|
||||
#define SBMATRIX_MASTER_CM0PLUS 0
|
||||
#define SBMATRIX_MASTER_DSU 1
|
||||
#define SBMATRIX_MASTER_DMAC 2
|
||||
#define SBMATRIX_MASTER_NUM 3
|
||||
|
||||
#endif /* _SAMD21_SBMATRIX_INSTANCE_ */
|
||||
|
||||
@@ -1,129 +1,129 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM0_INSTANCE_
|
||||
#define _SAMD21_SERCOM0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM0_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CM Control A */
|
||||
#define REG_SERCOM0_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CM Control B */
|
||||
#define REG_SERCOM0_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM0) I2CM Baud Rate */
|
||||
#define REG_SERCOM0_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM0) I2CM Status */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) I2CM Syncbusy */
|
||||
#define REG_SERCOM0_I2CM_ADDR (0x42000824) /**< \brief (SERCOM0) I2CM Address */
|
||||
#define REG_SERCOM0_I2CM_DATA (0x42000828) /**< \brief (SERCOM0) I2CM Data */
|
||||
#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM0) I2CM Debug Control */
|
||||
#define REG_SERCOM0_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CS Control A */
|
||||
#define REG_SERCOM0_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CS Control B */
|
||||
#define REG_SERCOM0_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM0) I2CS Status */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) I2CS Syncbusy */
|
||||
#define REG_SERCOM0_I2CS_ADDR (0x42000824) /**< \brief (SERCOM0) I2CS Address */
|
||||
#define REG_SERCOM0_I2CS_DATA (0x42000828) /**< \brief (SERCOM0) I2CS Data */
|
||||
#define REG_SERCOM0_SPI_CTRLA (0x42000800) /**< \brief (SERCOM0) SPI Control A */
|
||||
#define REG_SERCOM0_SPI_CTRLB (0x42000804) /**< \brief (SERCOM0) SPI Control B */
|
||||
#define REG_SERCOM0_SPI_BAUD (0x4200080C) /**< \brief (SERCOM0) SPI Baud Rate */
|
||||
#define REG_SERCOM0_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_SPI_INTENSET (0x42000816) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM0_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_SPI_STATUS (0x4200081A) /**< \brief (SERCOM0) SPI Status */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) SPI Syncbusy */
|
||||
#define REG_SERCOM0_SPI_ADDR (0x42000824) /**< \brief (SERCOM0) SPI Address */
|
||||
#define REG_SERCOM0_SPI_DATA (0x42000828) /**< \brief (SERCOM0) SPI Data */
|
||||
#define REG_SERCOM0_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM0) SPI Debug Control */
|
||||
#define REG_SERCOM0_USART_CTRLA (0x42000800) /**< \brief (SERCOM0) USART Control A */
|
||||
#define REG_SERCOM0_USART_CTRLB (0x42000804) /**< \brief (SERCOM0) USART Control B */
|
||||
#define REG_SERCOM0_USART_BAUD (0x4200080C) /**< \brief (SERCOM0) USART Baud Rate */
|
||||
#define REG_SERCOM0_USART_RXPL (0x4200080E) /**< \brief (SERCOM0) USART Receive Pulse Length */
|
||||
#define REG_SERCOM0_USART_INTENCLR (0x42000814) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_USART_INTENSET (0x42000816) /**< \brief (SERCOM0) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM0_USART_INTFLAG (0x42000818) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_USART_STATUS (0x4200081A) /**< \brief (SERCOM0) USART Status */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) USART Syncbusy */
|
||||
#define REG_SERCOM0_USART_DATA (0x42000828) /**< \brief (SERCOM0) USART Data */
|
||||
#define REG_SERCOM0_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM0) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CM Control A */
|
||||
#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CM Control B */
|
||||
#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
|
||||
#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CM Status */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) I2CM Syncbusy */
|
||||
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) I2CM Address */
|
||||
#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CM Data */
|
||||
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) I2CM Debug Control */
|
||||
#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CS Control A */
|
||||
#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CS Control B */
|
||||
#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CS Status */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) I2CS Syncbusy */
|
||||
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) I2CS Address */
|
||||
#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CS Data */
|
||||
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) SPI Control A */
|
||||
#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) SPI Control B */
|
||||
#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) SPI Baud Rate */
|
||||
#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) SPI Status */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) SPI Syncbusy */
|
||||
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) SPI Address */
|
||||
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM0) SPI Data */
|
||||
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) SPI Debug Control */
|
||||
#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) USART Control A */
|
||||
#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) USART Control B */
|
||||
#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM0) USART Baud Rate */
|
||||
#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
|
||||
#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) USART Status */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) USART Syncbusy */
|
||||
#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM0) USART Data */
|
||||
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM0 peripheral ========== */
|
||||
#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
|
||||
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
|
||||
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
|
||||
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM0_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM0_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM0_INSTANCE_
|
||||
#define _SAMD21_SERCOM0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM0_I2CM_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CM Control A */
|
||||
#define REG_SERCOM0_I2CM_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CM Control B */
|
||||
#define REG_SERCOM0_I2CM_BAUD (0x4200080C) /**< \brief (SERCOM0) I2CM Baud Rate */
|
||||
#define REG_SERCOM0_I2CM_INTENCLR (0x42000814) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CM_INTENSET (0x42000816) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CM_INTFLAG (0x42000818) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CM_STATUS (0x4200081A) /**< \brief (SERCOM0) I2CM Status */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) I2CM Syncbusy */
|
||||
#define REG_SERCOM0_I2CM_ADDR (0x42000824) /**< \brief (SERCOM0) I2CM Address */
|
||||
#define REG_SERCOM0_I2CM_DATA (0x42000828) /**< \brief (SERCOM0) I2CM Data */
|
||||
#define REG_SERCOM0_I2CM_DBGCTRL (0x42000830) /**< \brief (SERCOM0) I2CM Debug Control */
|
||||
#define REG_SERCOM0_I2CS_CTRLA (0x42000800) /**< \brief (SERCOM0) I2CS Control A */
|
||||
#define REG_SERCOM0_I2CS_CTRLB (0x42000804) /**< \brief (SERCOM0) I2CS Control B */
|
||||
#define REG_SERCOM0_I2CS_INTENCLR (0x42000814) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CS_INTENSET (0x42000816) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CS_INTFLAG (0x42000818) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CS_STATUS (0x4200081A) /**< \brief (SERCOM0) I2CS Status */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) I2CS Syncbusy */
|
||||
#define REG_SERCOM0_I2CS_ADDR (0x42000824) /**< \brief (SERCOM0) I2CS Address */
|
||||
#define REG_SERCOM0_I2CS_DATA (0x42000828) /**< \brief (SERCOM0) I2CS Data */
|
||||
#define REG_SERCOM0_SPI_CTRLA (0x42000800) /**< \brief (SERCOM0) SPI Control A */
|
||||
#define REG_SERCOM0_SPI_CTRLB (0x42000804) /**< \brief (SERCOM0) SPI Control B */
|
||||
#define REG_SERCOM0_SPI_BAUD (0x4200080C) /**< \brief (SERCOM0) SPI Baud Rate */
|
||||
#define REG_SERCOM0_SPI_INTENCLR (0x42000814) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_SPI_INTENSET (0x42000816) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM0_SPI_INTFLAG (0x42000818) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_SPI_STATUS (0x4200081A) /**< \brief (SERCOM0) SPI Status */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) SPI Syncbusy */
|
||||
#define REG_SERCOM0_SPI_ADDR (0x42000824) /**< \brief (SERCOM0) SPI Address */
|
||||
#define REG_SERCOM0_SPI_DATA (0x42000828) /**< \brief (SERCOM0) SPI Data */
|
||||
#define REG_SERCOM0_SPI_DBGCTRL (0x42000830) /**< \brief (SERCOM0) SPI Debug Control */
|
||||
#define REG_SERCOM0_USART_CTRLA (0x42000800) /**< \brief (SERCOM0) USART Control A */
|
||||
#define REG_SERCOM0_USART_CTRLB (0x42000804) /**< \brief (SERCOM0) USART Control B */
|
||||
#define REG_SERCOM0_USART_BAUD (0x4200080C) /**< \brief (SERCOM0) USART Baud Rate */
|
||||
#define REG_SERCOM0_USART_RXPL (0x4200080E) /**< \brief (SERCOM0) USART Receive Pulse Length */
|
||||
#define REG_SERCOM0_USART_INTENCLR (0x42000814) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_USART_INTENSET (0x42000816) /**< \brief (SERCOM0) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM0_USART_INTFLAG (0x42000818) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_USART_STATUS (0x4200081A) /**< \brief (SERCOM0) USART Status */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (0x4200081C) /**< \brief (SERCOM0) USART Syncbusy */
|
||||
#define REG_SERCOM0_USART_DATA (0x42000828) /**< \brief (SERCOM0) USART Data */
|
||||
#define REG_SERCOM0_USART_DBGCTRL (0x42000830) /**< \brief (SERCOM0) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CM Control A */
|
||||
#define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CM Control B */
|
||||
#define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4200080CUL) /**< \brief (SERCOM0) I2CM Baud Rate */
|
||||
#define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CM Status */
|
||||
#define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) I2CM Syncbusy */
|
||||
#define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) I2CM Address */
|
||||
#define REG_SERCOM0_I2CM_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CM Data */
|
||||
#define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) I2CM Debug Control */
|
||||
#define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) I2CS Control A */
|
||||
#define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) I2CS Control B */
|
||||
#define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) I2CS Status */
|
||||
#define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) I2CS Syncbusy */
|
||||
#define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) I2CS Address */
|
||||
#define REG_SERCOM0_I2CS_DATA (*(RwReg8 *)0x42000828UL) /**< \brief (SERCOM0) I2CS Data */
|
||||
#define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) SPI Control A */
|
||||
#define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) SPI Control B */
|
||||
#define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4200080CUL) /**< \brief (SERCOM0) SPI Baud Rate */
|
||||
#define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) SPI Status */
|
||||
#define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) SPI Syncbusy */
|
||||
#define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x42000824UL) /**< \brief (SERCOM0) SPI Address */
|
||||
#define REG_SERCOM0_SPI_DATA (*(RwReg *)0x42000828UL) /**< \brief (SERCOM0) SPI Data */
|
||||
#define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) SPI Debug Control */
|
||||
#define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x42000800UL) /**< \brief (SERCOM0) USART Control A */
|
||||
#define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x42000804UL) /**< \brief (SERCOM0) USART Control B */
|
||||
#define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4200080CUL) /**< \brief (SERCOM0) USART Baud Rate */
|
||||
#define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4200080EUL) /**< \brief (SERCOM0) USART Receive Pulse Length */
|
||||
#define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x42000814UL) /**< \brief (SERCOM0) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x42000816UL) /**< \brief (SERCOM0) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x42000818UL) /**< \brief (SERCOM0) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4200081AUL) /**< \brief (SERCOM0) USART Status */
|
||||
#define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4200081CUL) /**< \brief (SERCOM0) USART Syncbusy */
|
||||
#define REG_SERCOM0_USART_DATA (*(RwReg16*)0x42000828UL) /**< \brief (SERCOM0) USART Data */
|
||||
#define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x42000830UL) /**< \brief (SERCOM0) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM0 peripheral ========== */
|
||||
#define SERCOM0_DMAC_ID_RX 1 // Index of DMA RX trigger
|
||||
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
|
||||
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
|
||||
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM0_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM0_INSTANCE_ */
|
||||
|
||||
@@ -1,129 +1,129 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM1_INSTANCE_
|
||||
#define _SAMD21_SERCOM1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM1_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CM Control A */
|
||||
#define REG_SERCOM1_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CM Control B */
|
||||
#define REG_SERCOM1_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM1) I2CM Baud Rate */
|
||||
#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM1) I2CM Status */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) I2CM Syncbusy */
|
||||
#define REG_SERCOM1_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM1) I2CM Address */
|
||||
#define REG_SERCOM1_I2CM_DATA (0x42000C28) /**< \brief (SERCOM1) I2CM Data */
|
||||
#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) I2CM Debug Control */
|
||||
#define REG_SERCOM1_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CS Control A */
|
||||
#define REG_SERCOM1_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CS Control B */
|
||||
#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM1) I2CS Status */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) I2CS Syncbusy */
|
||||
#define REG_SERCOM1_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM1) I2CS Address */
|
||||
#define REG_SERCOM1_I2CS_DATA (0x42000C28) /**< \brief (SERCOM1) I2CS Data */
|
||||
#define REG_SERCOM1_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM1) SPI Control A */
|
||||
#define REG_SERCOM1_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM1) SPI Control B */
|
||||
#define REG_SERCOM1_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM1) SPI Baud Rate */
|
||||
#define REG_SERCOM1_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM1_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM1) SPI Status */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) SPI Syncbusy */
|
||||
#define REG_SERCOM1_SPI_ADDR (0x42000C24) /**< \brief (SERCOM1) SPI Address */
|
||||
#define REG_SERCOM1_SPI_DATA (0x42000C28) /**< \brief (SERCOM1) SPI Data */
|
||||
#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) SPI Debug Control */
|
||||
#define REG_SERCOM1_USART_CTRLA (0x42000C00) /**< \brief (SERCOM1) USART Control A */
|
||||
#define REG_SERCOM1_USART_CTRLB (0x42000C04) /**< \brief (SERCOM1) USART Control B */
|
||||
#define REG_SERCOM1_USART_BAUD (0x42000C0C) /**< \brief (SERCOM1) USART Baud Rate */
|
||||
#define REG_SERCOM1_USART_RXPL (0x42000C0E) /**< \brief (SERCOM1) USART Receive Pulse Length */
|
||||
#define REG_SERCOM1_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_USART_INTENSET (0x42000C16) /**< \brief (SERCOM1) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM1_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_USART_STATUS (0x42000C1A) /**< \brief (SERCOM1) USART Status */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) USART Syncbusy */
|
||||
#define REG_SERCOM1_USART_DATA (0x42000C28) /**< \brief (SERCOM1) USART Data */
|
||||
#define REG_SERCOM1_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CM Control A */
|
||||
#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CM Control B */
|
||||
#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
|
||||
#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CM Status */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) I2CM Syncbusy */
|
||||
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) I2CM Address */
|
||||
#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CM Data */
|
||||
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) I2CM Debug Control */
|
||||
#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CS Control A */
|
||||
#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CS Control B */
|
||||
#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CS Status */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) I2CS Syncbusy */
|
||||
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) I2CS Address */
|
||||
#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CS Data */
|
||||
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) SPI Control A */
|
||||
#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) SPI Control B */
|
||||
#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) SPI Baud Rate */
|
||||
#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) SPI Status */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) SPI Syncbusy */
|
||||
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) SPI Address */
|
||||
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM1) SPI Data */
|
||||
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) SPI Debug Control */
|
||||
#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) USART Control A */
|
||||
#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) USART Control B */
|
||||
#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM1) USART Baud Rate */
|
||||
#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
|
||||
#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) USART Status */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) USART Syncbusy */
|
||||
#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM1) USART Data */
|
||||
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM1 peripheral ========== */
|
||||
#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger
|
||||
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
|
||||
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
|
||||
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM1_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM1_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM1_INSTANCE_
|
||||
#define _SAMD21_SERCOM1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM1_I2CM_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CM Control A */
|
||||
#define REG_SERCOM1_I2CM_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CM Control B */
|
||||
#define REG_SERCOM1_I2CM_BAUD (0x42000C0C) /**< \brief (SERCOM1) I2CM Baud Rate */
|
||||
#define REG_SERCOM1_I2CM_INTENCLR (0x42000C14) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CM_INTENSET (0x42000C16) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CM_INTFLAG (0x42000C18) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CM_STATUS (0x42000C1A) /**< \brief (SERCOM1) I2CM Status */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) I2CM Syncbusy */
|
||||
#define REG_SERCOM1_I2CM_ADDR (0x42000C24) /**< \brief (SERCOM1) I2CM Address */
|
||||
#define REG_SERCOM1_I2CM_DATA (0x42000C28) /**< \brief (SERCOM1) I2CM Data */
|
||||
#define REG_SERCOM1_I2CM_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) I2CM Debug Control */
|
||||
#define REG_SERCOM1_I2CS_CTRLA (0x42000C00) /**< \brief (SERCOM1) I2CS Control A */
|
||||
#define REG_SERCOM1_I2CS_CTRLB (0x42000C04) /**< \brief (SERCOM1) I2CS Control B */
|
||||
#define REG_SERCOM1_I2CS_INTENCLR (0x42000C14) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CS_INTENSET (0x42000C16) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CS_INTFLAG (0x42000C18) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CS_STATUS (0x42000C1A) /**< \brief (SERCOM1) I2CS Status */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) I2CS Syncbusy */
|
||||
#define REG_SERCOM1_I2CS_ADDR (0x42000C24) /**< \brief (SERCOM1) I2CS Address */
|
||||
#define REG_SERCOM1_I2CS_DATA (0x42000C28) /**< \brief (SERCOM1) I2CS Data */
|
||||
#define REG_SERCOM1_SPI_CTRLA (0x42000C00) /**< \brief (SERCOM1) SPI Control A */
|
||||
#define REG_SERCOM1_SPI_CTRLB (0x42000C04) /**< \brief (SERCOM1) SPI Control B */
|
||||
#define REG_SERCOM1_SPI_BAUD (0x42000C0C) /**< \brief (SERCOM1) SPI Baud Rate */
|
||||
#define REG_SERCOM1_SPI_INTENCLR (0x42000C14) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_SPI_INTENSET (0x42000C16) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM1_SPI_INTFLAG (0x42000C18) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_SPI_STATUS (0x42000C1A) /**< \brief (SERCOM1) SPI Status */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) SPI Syncbusy */
|
||||
#define REG_SERCOM1_SPI_ADDR (0x42000C24) /**< \brief (SERCOM1) SPI Address */
|
||||
#define REG_SERCOM1_SPI_DATA (0x42000C28) /**< \brief (SERCOM1) SPI Data */
|
||||
#define REG_SERCOM1_SPI_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) SPI Debug Control */
|
||||
#define REG_SERCOM1_USART_CTRLA (0x42000C00) /**< \brief (SERCOM1) USART Control A */
|
||||
#define REG_SERCOM1_USART_CTRLB (0x42000C04) /**< \brief (SERCOM1) USART Control B */
|
||||
#define REG_SERCOM1_USART_BAUD (0x42000C0C) /**< \brief (SERCOM1) USART Baud Rate */
|
||||
#define REG_SERCOM1_USART_RXPL (0x42000C0E) /**< \brief (SERCOM1) USART Receive Pulse Length */
|
||||
#define REG_SERCOM1_USART_INTENCLR (0x42000C14) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_USART_INTENSET (0x42000C16) /**< \brief (SERCOM1) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM1_USART_INTFLAG (0x42000C18) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_USART_STATUS (0x42000C1A) /**< \brief (SERCOM1) USART Status */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (0x42000C1C) /**< \brief (SERCOM1) USART Syncbusy */
|
||||
#define REG_SERCOM1_USART_DATA (0x42000C28) /**< \brief (SERCOM1) USART Data */
|
||||
#define REG_SERCOM1_USART_DBGCTRL (0x42000C30) /**< \brief (SERCOM1) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CM Control A */
|
||||
#define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CM Control B */
|
||||
#define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x42000C0CUL) /**< \brief (SERCOM1) I2CM Baud Rate */
|
||||
#define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CM Status */
|
||||
#define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) I2CM Syncbusy */
|
||||
#define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) I2CM Address */
|
||||
#define REG_SERCOM1_I2CM_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CM Data */
|
||||
#define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) I2CM Debug Control */
|
||||
#define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) I2CS Control A */
|
||||
#define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) I2CS Control B */
|
||||
#define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) I2CS Status */
|
||||
#define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) I2CS Syncbusy */
|
||||
#define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) I2CS Address */
|
||||
#define REG_SERCOM1_I2CS_DATA (*(RwReg8 *)0x42000C28UL) /**< \brief (SERCOM1) I2CS Data */
|
||||
#define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) SPI Control A */
|
||||
#define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) SPI Control B */
|
||||
#define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x42000C0CUL) /**< \brief (SERCOM1) SPI Baud Rate */
|
||||
#define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) SPI Status */
|
||||
#define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) SPI Syncbusy */
|
||||
#define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x42000C24UL) /**< \brief (SERCOM1) SPI Address */
|
||||
#define REG_SERCOM1_SPI_DATA (*(RwReg *)0x42000C28UL) /**< \brief (SERCOM1) SPI Data */
|
||||
#define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) SPI Debug Control */
|
||||
#define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x42000C00UL) /**< \brief (SERCOM1) USART Control A */
|
||||
#define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x42000C04UL) /**< \brief (SERCOM1) USART Control B */
|
||||
#define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x42000C0CUL) /**< \brief (SERCOM1) USART Baud Rate */
|
||||
#define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x42000C0EUL) /**< \brief (SERCOM1) USART Receive Pulse Length */
|
||||
#define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x42000C14UL) /**< \brief (SERCOM1) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x42000C16UL) /**< \brief (SERCOM1) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x42000C18UL) /**< \brief (SERCOM1) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x42000C1AUL) /**< \brief (SERCOM1) USART Status */
|
||||
#define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x42000C1CUL) /**< \brief (SERCOM1) USART Syncbusy */
|
||||
#define REG_SERCOM1_USART_DATA (*(RwReg16*)0x42000C28UL) /**< \brief (SERCOM1) USART Data */
|
||||
#define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x42000C30UL) /**< \brief (SERCOM1) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM1 peripheral ========== */
|
||||
#define SERCOM1_DMAC_ID_RX 3 // Index of DMA RX trigger
|
||||
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
|
||||
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
|
||||
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM1_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM1_INSTANCE_ */
|
||||
|
||||
@@ -1,129 +1,129 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM2_INSTANCE_
|
||||
#define _SAMD21_SERCOM2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM2_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CM Control A */
|
||||
#define REG_SERCOM2_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CM Control B */
|
||||
#define REG_SERCOM2_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM2) I2CM Baud Rate */
|
||||
#define REG_SERCOM2_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM2) I2CM Status */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) I2CM Syncbusy */
|
||||
#define REG_SERCOM2_I2CM_ADDR (0x42001024) /**< \brief (SERCOM2) I2CM Address */
|
||||
#define REG_SERCOM2_I2CM_DATA (0x42001028) /**< \brief (SERCOM2) I2CM Data */
|
||||
#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM2) I2CM Debug Control */
|
||||
#define REG_SERCOM2_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CS Control A */
|
||||
#define REG_SERCOM2_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CS Control B */
|
||||
#define REG_SERCOM2_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM2) I2CS Status */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) I2CS Syncbusy */
|
||||
#define REG_SERCOM2_I2CS_ADDR (0x42001024) /**< \brief (SERCOM2) I2CS Address */
|
||||
#define REG_SERCOM2_I2CS_DATA (0x42001028) /**< \brief (SERCOM2) I2CS Data */
|
||||
#define REG_SERCOM2_SPI_CTRLA (0x42001000) /**< \brief (SERCOM2) SPI Control A */
|
||||
#define REG_SERCOM2_SPI_CTRLB (0x42001004) /**< \brief (SERCOM2) SPI Control B */
|
||||
#define REG_SERCOM2_SPI_BAUD (0x4200100C) /**< \brief (SERCOM2) SPI Baud Rate */
|
||||
#define REG_SERCOM2_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_SPI_INTENSET (0x42001016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM2_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_SPI_STATUS (0x4200101A) /**< \brief (SERCOM2) SPI Status */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) SPI Syncbusy */
|
||||
#define REG_SERCOM2_SPI_ADDR (0x42001024) /**< \brief (SERCOM2) SPI Address */
|
||||
#define REG_SERCOM2_SPI_DATA (0x42001028) /**< \brief (SERCOM2) SPI Data */
|
||||
#define REG_SERCOM2_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM2) SPI Debug Control */
|
||||
#define REG_SERCOM2_USART_CTRLA (0x42001000) /**< \brief (SERCOM2) USART Control A */
|
||||
#define REG_SERCOM2_USART_CTRLB (0x42001004) /**< \brief (SERCOM2) USART Control B */
|
||||
#define REG_SERCOM2_USART_BAUD (0x4200100C) /**< \brief (SERCOM2) USART Baud Rate */
|
||||
#define REG_SERCOM2_USART_RXPL (0x4200100E) /**< \brief (SERCOM2) USART Receive Pulse Length */
|
||||
#define REG_SERCOM2_USART_INTENCLR (0x42001014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_USART_INTENSET (0x42001016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM2_USART_INTFLAG (0x42001018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_USART_STATUS (0x4200101A) /**< \brief (SERCOM2) USART Status */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) USART Syncbusy */
|
||||
#define REG_SERCOM2_USART_DATA (0x42001028) /**< \brief (SERCOM2) USART Data */
|
||||
#define REG_SERCOM2_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM2) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CM Control A */
|
||||
#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CM Control B */
|
||||
#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
|
||||
#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CM Status */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) I2CM Syncbusy */
|
||||
#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) I2CM Address */
|
||||
#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CM Data */
|
||||
#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) I2CM Debug Control */
|
||||
#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CS Control A */
|
||||
#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CS Control B */
|
||||
#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CS Status */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) I2CS Syncbusy */
|
||||
#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) I2CS Address */
|
||||
#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CS Data */
|
||||
#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) SPI Control A */
|
||||
#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) SPI Control B */
|
||||
#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) SPI Baud Rate */
|
||||
#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) SPI Status */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) SPI Syncbusy */
|
||||
#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) SPI Address */
|
||||
#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM2) SPI Data */
|
||||
#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) SPI Debug Control */
|
||||
#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) USART Control A */
|
||||
#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) USART Control B */
|
||||
#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM2) USART Baud Rate */
|
||||
#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
|
||||
#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) USART Status */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) USART Syncbusy */
|
||||
#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM2) USART Data */
|
||||
#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM2 peripheral ========== */
|
||||
#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
|
||||
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
|
||||
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
|
||||
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM2_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM2_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM2_INSTANCE_
|
||||
#define _SAMD21_SERCOM2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM2_I2CM_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CM Control A */
|
||||
#define REG_SERCOM2_I2CM_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CM Control B */
|
||||
#define REG_SERCOM2_I2CM_BAUD (0x4200100C) /**< \brief (SERCOM2) I2CM Baud Rate */
|
||||
#define REG_SERCOM2_I2CM_INTENCLR (0x42001014) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CM_INTENSET (0x42001016) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CM_INTFLAG (0x42001018) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CM_STATUS (0x4200101A) /**< \brief (SERCOM2) I2CM Status */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) I2CM Syncbusy */
|
||||
#define REG_SERCOM2_I2CM_ADDR (0x42001024) /**< \brief (SERCOM2) I2CM Address */
|
||||
#define REG_SERCOM2_I2CM_DATA (0x42001028) /**< \brief (SERCOM2) I2CM Data */
|
||||
#define REG_SERCOM2_I2CM_DBGCTRL (0x42001030) /**< \brief (SERCOM2) I2CM Debug Control */
|
||||
#define REG_SERCOM2_I2CS_CTRLA (0x42001000) /**< \brief (SERCOM2) I2CS Control A */
|
||||
#define REG_SERCOM2_I2CS_CTRLB (0x42001004) /**< \brief (SERCOM2) I2CS Control B */
|
||||
#define REG_SERCOM2_I2CS_INTENCLR (0x42001014) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CS_INTENSET (0x42001016) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CS_INTFLAG (0x42001018) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CS_STATUS (0x4200101A) /**< \brief (SERCOM2) I2CS Status */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) I2CS Syncbusy */
|
||||
#define REG_SERCOM2_I2CS_ADDR (0x42001024) /**< \brief (SERCOM2) I2CS Address */
|
||||
#define REG_SERCOM2_I2CS_DATA (0x42001028) /**< \brief (SERCOM2) I2CS Data */
|
||||
#define REG_SERCOM2_SPI_CTRLA (0x42001000) /**< \brief (SERCOM2) SPI Control A */
|
||||
#define REG_SERCOM2_SPI_CTRLB (0x42001004) /**< \brief (SERCOM2) SPI Control B */
|
||||
#define REG_SERCOM2_SPI_BAUD (0x4200100C) /**< \brief (SERCOM2) SPI Baud Rate */
|
||||
#define REG_SERCOM2_SPI_INTENCLR (0x42001014) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_SPI_INTENSET (0x42001016) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM2_SPI_INTFLAG (0x42001018) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_SPI_STATUS (0x4200101A) /**< \brief (SERCOM2) SPI Status */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) SPI Syncbusy */
|
||||
#define REG_SERCOM2_SPI_ADDR (0x42001024) /**< \brief (SERCOM2) SPI Address */
|
||||
#define REG_SERCOM2_SPI_DATA (0x42001028) /**< \brief (SERCOM2) SPI Data */
|
||||
#define REG_SERCOM2_SPI_DBGCTRL (0x42001030) /**< \brief (SERCOM2) SPI Debug Control */
|
||||
#define REG_SERCOM2_USART_CTRLA (0x42001000) /**< \brief (SERCOM2) USART Control A */
|
||||
#define REG_SERCOM2_USART_CTRLB (0x42001004) /**< \brief (SERCOM2) USART Control B */
|
||||
#define REG_SERCOM2_USART_BAUD (0x4200100C) /**< \brief (SERCOM2) USART Baud Rate */
|
||||
#define REG_SERCOM2_USART_RXPL (0x4200100E) /**< \brief (SERCOM2) USART Receive Pulse Length */
|
||||
#define REG_SERCOM2_USART_INTENCLR (0x42001014) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_USART_INTENSET (0x42001016) /**< \brief (SERCOM2) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM2_USART_INTFLAG (0x42001018) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_USART_STATUS (0x4200101A) /**< \brief (SERCOM2) USART Status */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (0x4200101C) /**< \brief (SERCOM2) USART Syncbusy */
|
||||
#define REG_SERCOM2_USART_DATA (0x42001028) /**< \brief (SERCOM2) USART Data */
|
||||
#define REG_SERCOM2_USART_DBGCTRL (0x42001030) /**< \brief (SERCOM2) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM2_I2CM_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CM Control A */
|
||||
#define REG_SERCOM2_I2CM_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CM Control B */
|
||||
#define REG_SERCOM2_I2CM_BAUD (*(RwReg *)0x4200100CUL) /**< \brief (SERCOM2) I2CM Baud Rate */
|
||||
#define REG_SERCOM2_I2CM_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CM_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CM_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CM_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CM Status */
|
||||
#define REG_SERCOM2_I2CM_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) I2CM Syncbusy */
|
||||
#define REG_SERCOM2_I2CM_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) I2CM Address */
|
||||
#define REG_SERCOM2_I2CM_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CM Data */
|
||||
#define REG_SERCOM2_I2CM_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) I2CM Debug Control */
|
||||
#define REG_SERCOM2_I2CS_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) I2CS Control A */
|
||||
#define REG_SERCOM2_I2CS_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) I2CS Control B */
|
||||
#define REG_SERCOM2_I2CS_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_I2CS_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM2_I2CS_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_I2CS_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) I2CS Status */
|
||||
#define REG_SERCOM2_I2CS_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) I2CS Syncbusy */
|
||||
#define REG_SERCOM2_I2CS_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) I2CS Address */
|
||||
#define REG_SERCOM2_I2CS_DATA (*(RwReg8 *)0x42001028UL) /**< \brief (SERCOM2) I2CS Data */
|
||||
#define REG_SERCOM2_SPI_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) SPI Control A */
|
||||
#define REG_SERCOM2_SPI_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) SPI Control B */
|
||||
#define REG_SERCOM2_SPI_BAUD (*(RwReg8 *)0x4200100CUL) /**< \brief (SERCOM2) SPI Baud Rate */
|
||||
#define REG_SERCOM2_SPI_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_SPI_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM2_SPI_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_SPI_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) SPI Status */
|
||||
#define REG_SERCOM2_SPI_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) SPI Syncbusy */
|
||||
#define REG_SERCOM2_SPI_ADDR (*(RwReg *)0x42001024UL) /**< \brief (SERCOM2) SPI Address */
|
||||
#define REG_SERCOM2_SPI_DATA (*(RwReg *)0x42001028UL) /**< \brief (SERCOM2) SPI Data */
|
||||
#define REG_SERCOM2_SPI_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) SPI Debug Control */
|
||||
#define REG_SERCOM2_USART_CTRLA (*(RwReg *)0x42001000UL) /**< \brief (SERCOM2) USART Control A */
|
||||
#define REG_SERCOM2_USART_CTRLB (*(RwReg *)0x42001004UL) /**< \brief (SERCOM2) USART Control B */
|
||||
#define REG_SERCOM2_USART_BAUD (*(RwReg16*)0x4200100CUL) /**< \brief (SERCOM2) USART Baud Rate */
|
||||
#define REG_SERCOM2_USART_RXPL (*(RwReg8 *)0x4200100EUL) /**< \brief (SERCOM2) USART Receive Pulse Length */
|
||||
#define REG_SERCOM2_USART_INTENCLR (*(RwReg8 *)0x42001014UL) /**< \brief (SERCOM2) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM2_USART_INTENSET (*(RwReg8 *)0x42001016UL) /**< \brief (SERCOM2) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM2_USART_INTFLAG (*(RwReg8 *)0x42001018UL) /**< \brief (SERCOM2) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM2_USART_STATUS (*(RwReg16*)0x4200101AUL) /**< \brief (SERCOM2) USART Status */
|
||||
#define REG_SERCOM2_USART_SYNCBUSY (*(RoReg *)0x4200101CUL) /**< \brief (SERCOM2) USART Syncbusy */
|
||||
#define REG_SERCOM2_USART_DATA (*(RwReg16*)0x42001028UL) /**< \brief (SERCOM2) USART Data */
|
||||
#define REG_SERCOM2_USART_DBGCTRL (*(RwReg8 *)0x42001030UL) /**< \brief (SERCOM2) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM2 peripheral ========== */
|
||||
#define SERCOM2_DMAC_ID_RX 5 // Index of DMA RX trigger
|
||||
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
|
||||
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
|
||||
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM2_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM2_INSTANCE_ */
|
||||
|
||||
@@ -1,129 +1,129 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM3
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM3_INSTANCE_
|
||||
#define _SAMD21_SERCOM3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM3_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CM Control A */
|
||||
#define REG_SERCOM3_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CM Control B */
|
||||
#define REG_SERCOM3_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM3) I2CM Baud Rate */
|
||||
#define REG_SERCOM3_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (0x42001424) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (0x42001428) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
#define REG_SERCOM3_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CS Control A */
|
||||
#define REG_SERCOM3_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CS Control B */
|
||||
#define REG_SERCOM3_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (0x42001424) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (0x42001428) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (0x42001400) /**< \brief (SERCOM3) SPI Control A */
|
||||
#define REG_SERCOM3_SPI_CTRLB (0x42001404) /**< \brief (SERCOM3) SPI Control B */
|
||||
#define REG_SERCOM3_SPI_BAUD (0x4200140C) /**< \brief (SERCOM3) SPI Baud Rate */
|
||||
#define REG_SERCOM3_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_SPI_INTENSET (0x42001416) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (0x4200141A) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_ADDR (0x42001424) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (0x42001428) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
#define REG_SERCOM3_USART_CTRLA (0x42001400) /**< \brief (SERCOM3) USART Control A */
|
||||
#define REG_SERCOM3_USART_CTRLB (0x42001404) /**< \brief (SERCOM3) USART Control B */
|
||||
#define REG_SERCOM3_USART_BAUD (0x4200140C) /**< \brief (SERCOM3) USART Baud Rate */
|
||||
#define REG_SERCOM3_USART_RXPL (0x4200140E) /**< \brief (SERCOM3) USART Receive Pulse Length */
|
||||
#define REG_SERCOM3_USART_INTENCLR (0x42001414) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_USART_INTENSET (0x42001416) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (0x42001418) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (0x4200141A) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_DATA (0x42001428) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CM Control A */
|
||||
#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CM Control B */
|
||||
#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
|
||||
#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CS Control A */
|
||||
#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CS Control B */
|
||||
#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) SPI Control A */
|
||||
#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) SPI Control B */
|
||||
#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) SPI Baud Rate */
|
||||
#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) USART Control A */
|
||||
#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) USART Control B */
|
||||
#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM3) USART Baud Rate */
|
||||
#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
|
||||
#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM3 peripheral ========== */
|
||||
#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
|
||||
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
|
||||
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
|
||||
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM3_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM3_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM3
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM3_INSTANCE_
|
||||
#define _SAMD21_SERCOM3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM3_I2CM_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CM Control A */
|
||||
#define REG_SERCOM3_I2CM_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CM Control B */
|
||||
#define REG_SERCOM3_I2CM_BAUD (0x4200140C) /**< \brief (SERCOM3) I2CM Baud Rate */
|
||||
#define REG_SERCOM3_I2CM_INTENCLR (0x42001414) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CM_INTENSET (0x42001416) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (0x42001418) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (0x4200141A) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (0x42001424) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (0x42001428) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (0x42001430) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
#define REG_SERCOM3_I2CS_CTRLA (0x42001400) /**< \brief (SERCOM3) I2CS Control A */
|
||||
#define REG_SERCOM3_I2CS_CTRLB (0x42001404) /**< \brief (SERCOM3) I2CS Control B */
|
||||
#define REG_SERCOM3_I2CS_INTENCLR (0x42001414) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CS_INTENSET (0x42001416) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (0x42001418) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (0x4200141A) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (0x42001424) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (0x42001428) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (0x42001400) /**< \brief (SERCOM3) SPI Control A */
|
||||
#define REG_SERCOM3_SPI_CTRLB (0x42001404) /**< \brief (SERCOM3) SPI Control B */
|
||||
#define REG_SERCOM3_SPI_BAUD (0x4200140C) /**< \brief (SERCOM3) SPI Baud Rate */
|
||||
#define REG_SERCOM3_SPI_INTENCLR (0x42001414) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_SPI_INTENSET (0x42001416) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (0x42001418) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (0x4200141A) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_ADDR (0x42001424) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (0x42001428) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (0x42001430) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
#define REG_SERCOM3_USART_CTRLA (0x42001400) /**< \brief (SERCOM3) USART Control A */
|
||||
#define REG_SERCOM3_USART_CTRLB (0x42001404) /**< \brief (SERCOM3) USART Control B */
|
||||
#define REG_SERCOM3_USART_BAUD (0x4200140C) /**< \brief (SERCOM3) USART Baud Rate */
|
||||
#define REG_SERCOM3_USART_RXPL (0x4200140E) /**< \brief (SERCOM3) USART Receive Pulse Length */
|
||||
#define REG_SERCOM3_USART_INTENCLR (0x42001414) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_USART_INTENSET (0x42001416) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (0x42001418) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (0x4200141A) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (0x4200141C) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_DATA (0x42001428) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (0x42001430) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM3_I2CM_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CM Control A */
|
||||
#define REG_SERCOM3_I2CM_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CM Control B */
|
||||
#define REG_SERCOM3_I2CM_BAUD (*(RwReg *)0x4200140CUL) /**< \brief (SERCOM3) I2CM Baud Rate */
|
||||
#define REG_SERCOM3_I2CM_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CM_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CM_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CM_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CM Status */
|
||||
#define REG_SERCOM3_I2CM_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) I2CM Syncbusy */
|
||||
#define REG_SERCOM3_I2CM_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) I2CM Address */
|
||||
#define REG_SERCOM3_I2CM_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CM Data */
|
||||
#define REG_SERCOM3_I2CM_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) I2CM Debug Control */
|
||||
#define REG_SERCOM3_I2CS_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) I2CS Control A */
|
||||
#define REG_SERCOM3_I2CS_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) I2CS Control B */
|
||||
#define REG_SERCOM3_I2CS_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_I2CS_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM3_I2CS_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_I2CS_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) I2CS Status */
|
||||
#define REG_SERCOM3_I2CS_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) I2CS Syncbusy */
|
||||
#define REG_SERCOM3_I2CS_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) I2CS Address */
|
||||
#define REG_SERCOM3_I2CS_DATA (*(RwReg8 *)0x42001428UL) /**< \brief (SERCOM3) I2CS Data */
|
||||
#define REG_SERCOM3_SPI_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) SPI Control A */
|
||||
#define REG_SERCOM3_SPI_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) SPI Control B */
|
||||
#define REG_SERCOM3_SPI_BAUD (*(RwReg8 *)0x4200140CUL) /**< \brief (SERCOM3) SPI Baud Rate */
|
||||
#define REG_SERCOM3_SPI_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_SPI_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM3_SPI_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_SPI_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) SPI Status */
|
||||
#define REG_SERCOM3_SPI_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) SPI Syncbusy */
|
||||
#define REG_SERCOM3_SPI_ADDR (*(RwReg *)0x42001424UL) /**< \brief (SERCOM3) SPI Address */
|
||||
#define REG_SERCOM3_SPI_DATA (*(RwReg *)0x42001428UL) /**< \brief (SERCOM3) SPI Data */
|
||||
#define REG_SERCOM3_SPI_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) SPI Debug Control */
|
||||
#define REG_SERCOM3_USART_CTRLA (*(RwReg *)0x42001400UL) /**< \brief (SERCOM3) USART Control A */
|
||||
#define REG_SERCOM3_USART_CTRLB (*(RwReg *)0x42001404UL) /**< \brief (SERCOM3) USART Control B */
|
||||
#define REG_SERCOM3_USART_BAUD (*(RwReg16*)0x4200140CUL) /**< \brief (SERCOM3) USART Baud Rate */
|
||||
#define REG_SERCOM3_USART_RXPL (*(RwReg8 *)0x4200140EUL) /**< \brief (SERCOM3) USART Receive Pulse Length */
|
||||
#define REG_SERCOM3_USART_INTENCLR (*(RwReg8 *)0x42001414UL) /**< \brief (SERCOM3) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM3_USART_INTENSET (*(RwReg8 *)0x42001416UL) /**< \brief (SERCOM3) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM3_USART_INTFLAG (*(RwReg8 *)0x42001418UL) /**< \brief (SERCOM3) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM3_USART_STATUS (*(RwReg16*)0x4200141AUL) /**< \brief (SERCOM3) USART Status */
|
||||
#define REG_SERCOM3_USART_SYNCBUSY (*(RoReg *)0x4200141CUL) /**< \brief (SERCOM3) USART Syncbusy */
|
||||
#define REG_SERCOM3_USART_DATA (*(RwReg16*)0x42001428UL) /**< \brief (SERCOM3) USART Data */
|
||||
#define REG_SERCOM3_USART_DBGCTRL (*(RwReg8 *)0x42001430UL) /**< \brief (SERCOM3) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM3 peripheral ========== */
|
||||
#define SERCOM3_DMAC_ID_RX 7 // Index of DMA RX trigger
|
||||
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
|
||||
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
|
||||
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM3_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM3_INSTANCE_ */
|
||||
|
||||
@@ -1,129 +1,129 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM4
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM4_INSTANCE_
|
||||
#define _SAMD21_SERCOM4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM4_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CM Control A */
|
||||
#define REG_SERCOM4_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CM Control B */
|
||||
#define REG_SERCOM4_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM4) I2CM Baud Rate */
|
||||
#define REG_SERCOM4_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (0x42001824) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (0x42001828) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
#define REG_SERCOM4_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CS Control A */
|
||||
#define REG_SERCOM4_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CS Control B */
|
||||
#define REG_SERCOM4_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (0x42001824) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (0x42001828) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (0x42001800) /**< \brief (SERCOM4) SPI Control A */
|
||||
#define REG_SERCOM4_SPI_CTRLB (0x42001804) /**< \brief (SERCOM4) SPI Control B */
|
||||
#define REG_SERCOM4_SPI_BAUD (0x4200180C) /**< \brief (SERCOM4) SPI Baud Rate */
|
||||
#define REG_SERCOM4_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_SPI_INTENSET (0x42001816) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (0x4200181A) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_ADDR (0x42001824) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (0x42001828) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
#define REG_SERCOM4_USART_CTRLA (0x42001800) /**< \brief (SERCOM4) USART Control A */
|
||||
#define REG_SERCOM4_USART_CTRLB (0x42001804) /**< \brief (SERCOM4) USART Control B */
|
||||
#define REG_SERCOM4_USART_BAUD (0x4200180C) /**< \brief (SERCOM4) USART Baud Rate */
|
||||
#define REG_SERCOM4_USART_RXPL (0x4200180E) /**< \brief (SERCOM4) USART Receive Pulse Length */
|
||||
#define REG_SERCOM4_USART_INTENCLR (0x42001814) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_USART_INTENSET (0x42001816) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (0x42001818) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (0x4200181A) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_DATA (0x42001828) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CM Control A */
|
||||
#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CM Control B */
|
||||
#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
|
||||
#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CS Control A */
|
||||
#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CS Control B */
|
||||
#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) SPI Control A */
|
||||
#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) SPI Control B */
|
||||
#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) SPI Baud Rate */
|
||||
#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) USART Control A */
|
||||
#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) USART Control B */
|
||||
#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM4) USART Baud Rate */
|
||||
#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
|
||||
#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM4 peripheral ========== */
|
||||
#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger
|
||||
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
|
||||
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
|
||||
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM4_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM4_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM4
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM4_INSTANCE_
|
||||
#define _SAMD21_SERCOM4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM4_I2CM_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CM Control A */
|
||||
#define REG_SERCOM4_I2CM_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CM Control B */
|
||||
#define REG_SERCOM4_I2CM_BAUD (0x4200180C) /**< \brief (SERCOM4) I2CM Baud Rate */
|
||||
#define REG_SERCOM4_I2CM_INTENCLR (0x42001814) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CM_INTENSET (0x42001816) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (0x42001818) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (0x4200181A) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (0x42001824) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (0x42001828) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (0x42001830) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
#define REG_SERCOM4_I2CS_CTRLA (0x42001800) /**< \brief (SERCOM4) I2CS Control A */
|
||||
#define REG_SERCOM4_I2CS_CTRLB (0x42001804) /**< \brief (SERCOM4) I2CS Control B */
|
||||
#define REG_SERCOM4_I2CS_INTENCLR (0x42001814) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CS_INTENSET (0x42001816) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (0x42001818) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (0x4200181A) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (0x42001824) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (0x42001828) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (0x42001800) /**< \brief (SERCOM4) SPI Control A */
|
||||
#define REG_SERCOM4_SPI_CTRLB (0x42001804) /**< \brief (SERCOM4) SPI Control B */
|
||||
#define REG_SERCOM4_SPI_BAUD (0x4200180C) /**< \brief (SERCOM4) SPI Baud Rate */
|
||||
#define REG_SERCOM4_SPI_INTENCLR (0x42001814) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_SPI_INTENSET (0x42001816) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (0x42001818) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (0x4200181A) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_ADDR (0x42001824) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (0x42001828) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (0x42001830) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
#define REG_SERCOM4_USART_CTRLA (0x42001800) /**< \brief (SERCOM4) USART Control A */
|
||||
#define REG_SERCOM4_USART_CTRLB (0x42001804) /**< \brief (SERCOM4) USART Control B */
|
||||
#define REG_SERCOM4_USART_BAUD (0x4200180C) /**< \brief (SERCOM4) USART Baud Rate */
|
||||
#define REG_SERCOM4_USART_RXPL (0x4200180E) /**< \brief (SERCOM4) USART Receive Pulse Length */
|
||||
#define REG_SERCOM4_USART_INTENCLR (0x42001814) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_USART_INTENSET (0x42001816) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (0x42001818) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (0x4200181A) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (0x4200181C) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_DATA (0x42001828) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (0x42001830) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM4_I2CM_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CM Control A */
|
||||
#define REG_SERCOM4_I2CM_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CM Control B */
|
||||
#define REG_SERCOM4_I2CM_BAUD (*(RwReg *)0x4200180CUL) /**< \brief (SERCOM4) I2CM Baud Rate */
|
||||
#define REG_SERCOM4_I2CM_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CM_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CM_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CM_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CM Status */
|
||||
#define REG_SERCOM4_I2CM_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) I2CM Syncbusy */
|
||||
#define REG_SERCOM4_I2CM_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) I2CM Address */
|
||||
#define REG_SERCOM4_I2CM_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CM Data */
|
||||
#define REG_SERCOM4_I2CM_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) I2CM Debug Control */
|
||||
#define REG_SERCOM4_I2CS_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) I2CS Control A */
|
||||
#define REG_SERCOM4_I2CS_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) I2CS Control B */
|
||||
#define REG_SERCOM4_I2CS_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_I2CS_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM4_I2CS_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_I2CS_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) I2CS Status */
|
||||
#define REG_SERCOM4_I2CS_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) I2CS Syncbusy */
|
||||
#define REG_SERCOM4_I2CS_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) I2CS Address */
|
||||
#define REG_SERCOM4_I2CS_DATA (*(RwReg8 *)0x42001828UL) /**< \brief (SERCOM4) I2CS Data */
|
||||
#define REG_SERCOM4_SPI_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) SPI Control A */
|
||||
#define REG_SERCOM4_SPI_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) SPI Control B */
|
||||
#define REG_SERCOM4_SPI_BAUD (*(RwReg8 *)0x4200180CUL) /**< \brief (SERCOM4) SPI Baud Rate */
|
||||
#define REG_SERCOM4_SPI_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_SPI_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM4_SPI_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_SPI_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) SPI Status */
|
||||
#define REG_SERCOM4_SPI_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) SPI Syncbusy */
|
||||
#define REG_SERCOM4_SPI_ADDR (*(RwReg *)0x42001824UL) /**< \brief (SERCOM4) SPI Address */
|
||||
#define REG_SERCOM4_SPI_DATA (*(RwReg *)0x42001828UL) /**< \brief (SERCOM4) SPI Data */
|
||||
#define REG_SERCOM4_SPI_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) SPI Debug Control */
|
||||
#define REG_SERCOM4_USART_CTRLA (*(RwReg *)0x42001800UL) /**< \brief (SERCOM4) USART Control A */
|
||||
#define REG_SERCOM4_USART_CTRLB (*(RwReg *)0x42001804UL) /**< \brief (SERCOM4) USART Control B */
|
||||
#define REG_SERCOM4_USART_BAUD (*(RwReg16*)0x4200180CUL) /**< \brief (SERCOM4) USART Baud Rate */
|
||||
#define REG_SERCOM4_USART_RXPL (*(RwReg8 *)0x4200180EUL) /**< \brief (SERCOM4) USART Receive Pulse Length */
|
||||
#define REG_SERCOM4_USART_INTENCLR (*(RwReg8 *)0x42001814UL) /**< \brief (SERCOM4) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM4_USART_INTENSET (*(RwReg8 *)0x42001816UL) /**< \brief (SERCOM4) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM4_USART_INTFLAG (*(RwReg8 *)0x42001818UL) /**< \brief (SERCOM4) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM4_USART_STATUS (*(RwReg16*)0x4200181AUL) /**< \brief (SERCOM4) USART Status */
|
||||
#define REG_SERCOM4_USART_SYNCBUSY (*(RoReg *)0x4200181CUL) /**< \brief (SERCOM4) USART Syncbusy */
|
||||
#define REG_SERCOM4_USART_DATA (*(RwReg16*)0x42001828UL) /**< \brief (SERCOM4) USART Data */
|
||||
#define REG_SERCOM4_USART_DBGCTRL (*(RwReg8 *)0x42001830UL) /**< \brief (SERCOM4) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM4 peripheral ========== */
|
||||
#define SERCOM4_DMAC_ID_RX 9 // Index of DMA RX trigger
|
||||
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
|
||||
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
|
||||
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM4_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM4_INSTANCE_ */
|
||||
|
||||
@@ -1,129 +1,129 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM5
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM5_INSTANCE_
|
||||
#define _SAMD21_SERCOM5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM5_I2CM_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CM Control A */
|
||||
#define REG_SERCOM5_I2CM_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CM Control B */
|
||||
#define REG_SERCOM5_I2CM_BAUD (0x42001C0C) /**< \brief (SERCOM5) I2CM Baud Rate */
|
||||
#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CM_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (0x42001C28) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
#define REG_SERCOM5_I2CS_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CS Control A */
|
||||
#define REG_SERCOM5_I2CS_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CS Control B */
|
||||
#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CS_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (0x42001C28) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (0x42001C00) /**< \brief (SERCOM5) SPI Control A */
|
||||
#define REG_SERCOM5_SPI_CTRLB (0x42001C04) /**< \brief (SERCOM5) SPI Control B */
|
||||
#define REG_SERCOM5_SPI_BAUD (0x42001C0C) /**< \brief (SERCOM5) SPI Baud Rate */
|
||||
#define REG_SERCOM5_SPI_INTENCLR (0x42001C14) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_SPI_INTENSET (0x42001C16) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (0x42001C18) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (0x42001C1A) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_ADDR (0x42001C24) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (0x42001C28) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
#define REG_SERCOM5_USART_CTRLA (0x42001C00) /**< \brief (SERCOM5) USART Control A */
|
||||
#define REG_SERCOM5_USART_CTRLB (0x42001C04) /**< \brief (SERCOM5) USART Control B */
|
||||
#define REG_SERCOM5_USART_BAUD (0x42001C0C) /**< \brief (SERCOM5) USART Baud Rate */
|
||||
#define REG_SERCOM5_USART_RXPL (0x42001C0E) /**< \brief (SERCOM5) USART Receive Pulse Length */
|
||||
#define REG_SERCOM5_USART_INTENCLR (0x42001C14) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_USART_INTENSET (0x42001C16) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (0x42001C18) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (0x42001C1A) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_DATA (0x42001C28) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CM Control A */
|
||||
#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CM Control B */
|
||||
#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
|
||||
#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CS Control A */
|
||||
#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CS Control B */
|
||||
#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) SPI Control A */
|
||||
#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) SPI Control B */
|
||||
#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Baud Rate */
|
||||
#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28UL) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) USART Control A */
|
||||
#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) USART Control B */
|
||||
#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CUL) /**< \brief (SERCOM5) USART Baud Rate */
|
||||
#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
|
||||
#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28UL) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM5 peripheral ========== */
|
||||
#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger
|
||||
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
|
||||
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
|
||||
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM5_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM5_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SERCOM5
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SERCOM5_INSTANCE_
|
||||
#define _SAMD21_SERCOM5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SERCOM5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SERCOM5_I2CM_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CM Control A */
|
||||
#define REG_SERCOM5_I2CM_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CM Control B */
|
||||
#define REG_SERCOM5_I2CM_BAUD (0x42001C0C) /**< \brief (SERCOM5) I2CM Baud Rate */
|
||||
#define REG_SERCOM5_I2CM_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CM_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (0x42001C28) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
#define REG_SERCOM5_I2CS_CTRLA (0x42001C00) /**< \brief (SERCOM5) I2CS Control A */
|
||||
#define REG_SERCOM5_I2CS_CTRLB (0x42001C04) /**< \brief (SERCOM5) I2CS Control B */
|
||||
#define REG_SERCOM5_I2CS_INTENCLR (0x42001C14) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CS_INTENSET (0x42001C16) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (0x42001C18) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (0x42001C1A) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (0x42001C24) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (0x42001C28) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (0x42001C00) /**< \brief (SERCOM5) SPI Control A */
|
||||
#define REG_SERCOM5_SPI_CTRLB (0x42001C04) /**< \brief (SERCOM5) SPI Control B */
|
||||
#define REG_SERCOM5_SPI_BAUD (0x42001C0C) /**< \brief (SERCOM5) SPI Baud Rate */
|
||||
#define REG_SERCOM5_SPI_INTENCLR (0x42001C14) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_SPI_INTENSET (0x42001C16) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (0x42001C18) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (0x42001C1A) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_ADDR (0x42001C24) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (0x42001C28) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
#define REG_SERCOM5_USART_CTRLA (0x42001C00) /**< \brief (SERCOM5) USART Control A */
|
||||
#define REG_SERCOM5_USART_CTRLB (0x42001C04) /**< \brief (SERCOM5) USART Control B */
|
||||
#define REG_SERCOM5_USART_BAUD (0x42001C0C) /**< \brief (SERCOM5) USART Baud Rate */
|
||||
#define REG_SERCOM5_USART_RXPL (0x42001C0E) /**< \brief (SERCOM5) USART Receive Pulse Length */
|
||||
#define REG_SERCOM5_USART_INTENCLR (0x42001C14) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_USART_INTENSET (0x42001C16) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (0x42001C18) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (0x42001C1A) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (0x42001C1C) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_DATA (0x42001C28) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (0x42001C30) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#else
|
||||
#define REG_SERCOM5_I2CM_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CM Control A */
|
||||
#define REG_SERCOM5_I2CM_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CM Control B */
|
||||
#define REG_SERCOM5_I2CM_BAUD (*(RwReg *)0x42001C0CUL) /**< \brief (SERCOM5) I2CM Baud Rate */
|
||||
#define REG_SERCOM5_I2CM_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CM_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CM Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CM_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CM Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CM_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CM Status */
|
||||
#define REG_SERCOM5_I2CM_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CM Syncbusy */
|
||||
#define REG_SERCOM5_I2CM_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CM Address */
|
||||
#define REG_SERCOM5_I2CM_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CM Data */
|
||||
#define REG_SERCOM5_I2CM_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) I2CM Debug Control */
|
||||
#define REG_SERCOM5_I2CS_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) I2CS Control A */
|
||||
#define REG_SERCOM5_I2CS_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) I2CS Control B */
|
||||
#define REG_SERCOM5_I2CS_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_I2CS_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) I2CS Interrupt Enable Set */
|
||||
#define REG_SERCOM5_I2CS_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) I2CS Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_I2CS_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) I2CS Status */
|
||||
#define REG_SERCOM5_I2CS_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) I2CS Syncbusy */
|
||||
#define REG_SERCOM5_I2CS_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) I2CS Address */
|
||||
#define REG_SERCOM5_I2CS_DATA (*(RwReg8 *)0x42001C28UL) /**< \brief (SERCOM5) I2CS Data */
|
||||
#define REG_SERCOM5_SPI_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) SPI Control A */
|
||||
#define REG_SERCOM5_SPI_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) SPI Control B */
|
||||
#define REG_SERCOM5_SPI_BAUD (*(RwReg8 *)0x42001C0CUL) /**< \brief (SERCOM5) SPI Baud Rate */
|
||||
#define REG_SERCOM5_SPI_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) SPI Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_SPI_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) SPI Interrupt Enable Set */
|
||||
#define REG_SERCOM5_SPI_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) SPI Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_SPI_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) SPI Status */
|
||||
#define REG_SERCOM5_SPI_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) SPI Syncbusy */
|
||||
#define REG_SERCOM5_SPI_ADDR (*(RwReg *)0x42001C24UL) /**< \brief (SERCOM5) SPI Address */
|
||||
#define REG_SERCOM5_SPI_DATA (*(RwReg *)0x42001C28UL) /**< \brief (SERCOM5) SPI Data */
|
||||
#define REG_SERCOM5_SPI_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) SPI Debug Control */
|
||||
#define REG_SERCOM5_USART_CTRLA (*(RwReg *)0x42001C00UL) /**< \brief (SERCOM5) USART Control A */
|
||||
#define REG_SERCOM5_USART_CTRLB (*(RwReg *)0x42001C04UL) /**< \brief (SERCOM5) USART Control B */
|
||||
#define REG_SERCOM5_USART_BAUD (*(RwReg16*)0x42001C0CUL) /**< \brief (SERCOM5) USART Baud Rate */
|
||||
#define REG_SERCOM5_USART_RXPL (*(RwReg8 *)0x42001C0EUL) /**< \brief (SERCOM5) USART Receive Pulse Length */
|
||||
#define REG_SERCOM5_USART_INTENCLR (*(RwReg8 *)0x42001C14UL) /**< \brief (SERCOM5) USART Interrupt Enable Clear */
|
||||
#define REG_SERCOM5_USART_INTENSET (*(RwReg8 *)0x42001C16UL) /**< \brief (SERCOM5) USART Interrupt Enable Set */
|
||||
#define REG_SERCOM5_USART_INTFLAG (*(RwReg8 *)0x42001C18UL) /**< \brief (SERCOM5) USART Interrupt Flag Status and Clear */
|
||||
#define REG_SERCOM5_USART_STATUS (*(RwReg16*)0x42001C1AUL) /**< \brief (SERCOM5) USART Status */
|
||||
#define REG_SERCOM5_USART_SYNCBUSY (*(RoReg *)0x42001C1CUL) /**< \brief (SERCOM5) USART Syncbusy */
|
||||
#define REG_SERCOM5_USART_DATA (*(RwReg16*)0x42001C28UL) /**< \brief (SERCOM5) USART Data */
|
||||
#define REG_SERCOM5_USART_DBGCTRL (*(RwReg8 *)0x42001C30UL) /**< \brief (SERCOM5) USART Debug Control */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SERCOM5 peripheral ========== */
|
||||
#define SERCOM5_DMAC_ID_RX 11 // Index of DMA RX trigger
|
||||
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
|
||||
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
|
||||
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
|
||||
#define SERCOM5_INT_MSB 6
|
||||
|
||||
#endif /* _SAMD21_SERCOM5_INSTANCE_ */
|
||||
|
||||
@@ -1,107 +1,107 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SYSCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SYSCTRL_INSTANCE_
|
||||
#define _SAMD21_SYSCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SYSCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SYSCTRL_INTENCLR (0x40000800) /**< \brief (SYSCTRL) Interrupt Enable Clear */
|
||||
#define REG_SYSCTRL_INTENSET (0x40000804) /**< \brief (SYSCTRL) Interrupt Enable Set */
|
||||
#define REG_SYSCTRL_INTFLAG (0x40000808) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_SYSCTRL_PCLKSR (0x4000080C) /**< \brief (SYSCTRL) Power and Clocks Status */
|
||||
#define REG_SYSCTRL_XOSC (0x40000810) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
|
||||
#define REG_SYSCTRL_XOSC32K (0x40000814) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
|
||||
#define REG_SYSCTRL_OSC32K (0x40000818) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
|
||||
#define REG_SYSCTRL_OSCULP32K (0x4000081C) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
|
||||
#define REG_SYSCTRL_OSC8M (0x40000820) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
|
||||
#define REG_SYSCTRL_DFLLCTRL (0x40000824) /**< \brief (SYSCTRL) DFLL48M Control */
|
||||
#define REG_SYSCTRL_DFLLVAL (0x40000828) /**< \brief (SYSCTRL) DFLL48M Value */
|
||||
#define REG_SYSCTRL_DFLLMUL (0x4000082C) /**< \brief (SYSCTRL) DFLL48M Multiplier */
|
||||
#define REG_SYSCTRL_DFLLSYNC (0x40000830) /**< \brief (SYSCTRL) DFLL48M Synchronization */
|
||||
#define REG_SYSCTRL_BOD33 (0x40000834) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
#define REG_SYSCTRL_VREG (0x4000083C) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
|
||||
#define REG_SYSCTRL_VREF (0x40000840) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLA (0x40000844) /**< \brief (SYSCTRL) DPLL Control A */
|
||||
#define REG_SYSCTRL_DPLLRATIO (0x40000848) /**< \brief (SYSCTRL) DPLL Ratio Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLB (0x4000084C) /**< \brief (SYSCTRL) DPLL Control B */
|
||||
#define REG_SYSCTRL_DPLLSTATUS (0x40000850) /**< \brief (SYSCTRL) DPLL Status */
|
||||
#else
|
||||
#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800UL) /**< \brief (SYSCTRL) Interrupt Enable Clear */
|
||||
#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804UL) /**< \brief (SYSCTRL) Interrupt Enable Set */
|
||||
#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808UL) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CUL) /**< \brief (SYSCTRL) Power and Clocks Status */
|
||||
#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810UL) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
|
||||
#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814UL) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
|
||||
#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818UL) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
|
||||
#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CUL) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
|
||||
#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820UL) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
|
||||
#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824UL) /**< \brief (SYSCTRL) DFLL48M Control */
|
||||
#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828UL) /**< \brief (SYSCTRL) DFLL48M Value */
|
||||
#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CUL) /**< \brief (SYSCTRL) DFLL48M Multiplier */
|
||||
#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830UL) /**< \brief (SYSCTRL) DFLL48M Synchronization */
|
||||
#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834UL) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CUL) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
|
||||
#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840UL) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844UL) /**< \brief (SYSCTRL) DPLL Control A */
|
||||
#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848UL) /**< \brief (SYSCTRL) DPLL Ratio Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CUL) /**< \brief (SYSCTRL) DPLL Control B */
|
||||
#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850UL) /**< \brief (SYSCTRL) DPLL Status */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SYSCTRL peripheral ========== */
|
||||
#define SYSCTRL_BGAP_CALIB_MSB 11
|
||||
#define SYSCTRL_BOD33_CALIB_MSB 5
|
||||
#define SYSCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define SYSCTRL_DFLL48M_FINE_MSB 9
|
||||
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
|
||||
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
|
||||
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
|
||||
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
|
||||
#define SYSCTRL_POR33_ENTEST_MSB 1
|
||||
#define SYSCTRL_SYSTEM_CLOCK 1000000 // Initial system clock frequency
|
||||
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
|
||||
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
|
||||
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
|
||||
#define SYSCTRL_VREF_CONTROL_MSB 48
|
||||
#define SYSCTRL_VREF_STATUS_MSB 7
|
||||
#define SYSCTRL_VREG_LEVEL_MSB 2
|
||||
#define SYSCTRL_BOD12_VERSION 0x111
|
||||
#define SYSCTRL_BOD33_VERSION 0x111
|
||||
#define SYSCTRL_DFLL48M_VERSION 0x301
|
||||
#define SYSCTRL_FDPLL_VERSION 0x111
|
||||
#define SYSCTRL_OSCULP32K_VERSION 0x111
|
||||
#define SYSCTRL_OSC8M_VERSION 0x120
|
||||
#define SYSCTRL_OSC32K_VERSION 0x1101
|
||||
#define SYSCTRL_VREF_VERSION 0x200
|
||||
#define SYSCTRL_VREG_VERSION 0x201
|
||||
#define SYSCTRL_XOSC_VERSION 0x1111
|
||||
#define SYSCTRL_XOSC32K_VERSION 0x1111
|
||||
|
||||
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SYSCTRL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_SYSCTRL_INSTANCE_
|
||||
#define _SAMD21_SYSCTRL_INSTANCE_
|
||||
|
||||
/* ========== Register definition for SYSCTRL peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_SYSCTRL_INTENCLR (0x40000800) /**< \brief (SYSCTRL) Interrupt Enable Clear */
|
||||
#define REG_SYSCTRL_INTENSET (0x40000804) /**< \brief (SYSCTRL) Interrupt Enable Set */
|
||||
#define REG_SYSCTRL_INTFLAG (0x40000808) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_SYSCTRL_PCLKSR (0x4000080C) /**< \brief (SYSCTRL) Power and Clocks Status */
|
||||
#define REG_SYSCTRL_XOSC (0x40000810) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
|
||||
#define REG_SYSCTRL_XOSC32K (0x40000814) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
|
||||
#define REG_SYSCTRL_OSC32K (0x40000818) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
|
||||
#define REG_SYSCTRL_OSCULP32K (0x4000081C) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
|
||||
#define REG_SYSCTRL_OSC8M (0x40000820) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
|
||||
#define REG_SYSCTRL_DFLLCTRL (0x40000824) /**< \brief (SYSCTRL) DFLL48M Control */
|
||||
#define REG_SYSCTRL_DFLLVAL (0x40000828) /**< \brief (SYSCTRL) DFLL48M Value */
|
||||
#define REG_SYSCTRL_DFLLMUL (0x4000082C) /**< \brief (SYSCTRL) DFLL48M Multiplier */
|
||||
#define REG_SYSCTRL_DFLLSYNC (0x40000830) /**< \brief (SYSCTRL) DFLL48M Synchronization */
|
||||
#define REG_SYSCTRL_BOD33 (0x40000834) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
#define REG_SYSCTRL_VREG (0x4000083C) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
|
||||
#define REG_SYSCTRL_VREF (0x40000840) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLA (0x40000844) /**< \brief (SYSCTRL) DPLL Control A */
|
||||
#define REG_SYSCTRL_DPLLRATIO (0x40000848) /**< \brief (SYSCTRL) DPLL Ratio Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLB (0x4000084C) /**< \brief (SYSCTRL) DPLL Control B */
|
||||
#define REG_SYSCTRL_DPLLSTATUS (0x40000850) /**< \brief (SYSCTRL) DPLL Status */
|
||||
#else
|
||||
#define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800UL) /**< \brief (SYSCTRL) Interrupt Enable Clear */
|
||||
#define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804UL) /**< \brief (SYSCTRL) Interrupt Enable Set */
|
||||
#define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808UL) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */
|
||||
#define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CUL) /**< \brief (SYSCTRL) Power and Clocks Status */
|
||||
#define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810UL) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
|
||||
#define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814UL) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */
|
||||
#define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818UL) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */
|
||||
#define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CUL) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
|
||||
#define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820UL) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */
|
||||
#define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824UL) /**< \brief (SYSCTRL) DFLL48M Control */
|
||||
#define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828UL) /**< \brief (SYSCTRL) DFLL48M Value */
|
||||
#define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CUL) /**< \brief (SYSCTRL) DFLL48M Multiplier */
|
||||
#define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830UL) /**< \brief (SYSCTRL) DFLL48M Synchronization */
|
||||
#define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834UL) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */
|
||||
#define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CUL) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */
|
||||
#define REG_SYSCTRL_VREF (*(RwReg *)0x40000840UL) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844UL) /**< \brief (SYSCTRL) DPLL Control A */
|
||||
#define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848UL) /**< \brief (SYSCTRL) DPLL Ratio Control */
|
||||
#define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CUL) /**< \brief (SYSCTRL) DPLL Control B */
|
||||
#define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850UL) /**< \brief (SYSCTRL) DPLL Status */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for SYSCTRL peripheral ========== */
|
||||
#define SYSCTRL_BGAP_CALIB_MSB 11
|
||||
#define SYSCTRL_BOD33_CALIB_MSB 5
|
||||
#define SYSCTRL_DFLL48M_COARSE_MSB 5
|
||||
#define SYSCTRL_DFLL48M_FINE_MSB 9
|
||||
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
|
||||
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
|
||||
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
|
||||
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
|
||||
#define SYSCTRL_POR33_ENTEST_MSB 1
|
||||
#define SYSCTRL_SYSTEM_CLOCK 1000000 // Initial system clock frequency
|
||||
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
|
||||
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
|
||||
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
|
||||
#define SYSCTRL_VREF_CONTROL_MSB 48
|
||||
#define SYSCTRL_VREF_STATUS_MSB 7
|
||||
#define SYSCTRL_VREG_LEVEL_MSB 2
|
||||
#define SYSCTRL_BOD12_VERSION 0x111
|
||||
#define SYSCTRL_BOD33_VERSION 0x111
|
||||
#define SYSCTRL_DFLL48M_VERSION 0x301
|
||||
#define SYSCTRL_FDPLL_VERSION 0x111
|
||||
#define SYSCTRL_OSCULP32K_VERSION 0x111
|
||||
#define SYSCTRL_OSC8M_VERSION 0x120
|
||||
#define SYSCTRL_OSC32K_VERSION 0x1101
|
||||
#define SYSCTRL_VREF_VERSION 0x200
|
||||
#define SYSCTRL_VREG_VERSION 0x201
|
||||
#define SYSCTRL_XOSC_VERSION 0x1111
|
||||
#define SYSCTRL_XOSC32K_VERSION 0x1111
|
||||
|
||||
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */
|
||||
|
||||
@@ -1,97 +1,97 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC3
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC3_INSTANCE_
|
||||
#define _SAMD21_TC3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */
|
||||
#define REG_TC3_READREQ (0x42002C02) /**< \brief (TC3) Read Request */
|
||||
#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */
|
||||
#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */
|
||||
#define REG_TC3_CTRLC (0x42002C06) /**< \brief (TC3) Control C */
|
||||
#define REG_TC3_DBGCTRL (0x42002C08) /**< \brief (TC3) Debug Control */
|
||||
#define REG_TC3_EVCTRL (0x42002C0A) /**< \brief (TC3) Event Control */
|
||||
#define REG_TC3_INTENCLR (0x42002C0C) /**< \brief (TC3) Interrupt Enable Clear */
|
||||
#define REG_TC3_INTENSET (0x42002C0D) /**< \brief (TC3) Interrupt Enable Set */
|
||||
#define REG_TC3_INTFLAG (0x42002C0E) /**< \brief (TC3) Interrupt Flag Status and Clear */
|
||||
#define REG_TC3_STATUS (0x42002C0F) /**< \brief (TC3) Status */
|
||||
#define REG_TC3_COUNT16_COUNT (0x42002C10) /**< \brief (TC3) COUNT16 Counter Value */
|
||||
#define REG_TC3_COUNT16_CC0 (0x42002C18) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT16_CC1 (0x42002C1A) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT32_COUNT (0x42002C10) /**< \brief (TC3) COUNT32 Counter Value */
|
||||
#define REG_TC3_COUNT32_CC0 (0x42002C18) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT32_CC1 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT8_COUNT (0x42002C10) /**< \brief (TC3) COUNT8 Counter Value */
|
||||
#define REG_TC3_COUNT8_PER (0x42002C14) /**< \brief (TC3) COUNT8 Period Value */
|
||||
#define REG_TC3_COUNT8_CC0 (0x42002C18) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT8_CC1 (0x42002C19) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00UL) /**< \brief (TC3) Control A */
|
||||
#define REG_TC3_READREQ (*(RwReg16*)0x42002C02UL) /**< \brief (TC3) Read Request */
|
||||
#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */
|
||||
#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */
|
||||
#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06UL) /**< \brief (TC3) Control C */
|
||||
#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Debug Control */
|
||||
#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AUL) /**< \brief (TC3) Event Control */
|
||||
#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Interrupt Enable Clear */
|
||||
#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Interrupt Enable Set */
|
||||
#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
|
||||
#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FUL) /**< \brief (TC3) Status */
|
||||
#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10UL) /**< \brief (TC3) COUNT16 Counter Value */
|
||||
#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18UL) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AUL) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10UL) /**< \brief (TC3) COUNT32 Counter Value */
|
||||
#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18UL) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10UL) /**< \brief (TC3) COUNT8 Counter Value */
|
||||
#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Period Value */
|
||||
#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18UL) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19UL) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC3 peripheral ========== */
|
||||
#define TC3_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC3_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC3_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC3_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC3_DMAC_ID_MC_0 25
|
||||
#define TC3_DMAC_ID_MC_1 26
|
||||
#define TC3_DMAC_ID_MC_LSB 25
|
||||
#define TC3_DMAC_ID_MC_MSB 26
|
||||
#define TC3_DMAC_ID_MC_SIZE 2
|
||||
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
|
||||
#define TC3_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TC3_MASTER 0
|
||||
#define TC3_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC3_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC3_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC3
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC3_INSTANCE_
|
||||
#define _SAMD21_TC3_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC3_CTRLA (0x42002C00) /**< \brief (TC3) Control A */
|
||||
#define REG_TC3_READREQ (0x42002C02) /**< \brief (TC3) Read Request */
|
||||
#define REG_TC3_CTRLBCLR (0x42002C04) /**< \brief (TC3) Control B Clear */
|
||||
#define REG_TC3_CTRLBSET (0x42002C05) /**< \brief (TC3) Control B Set */
|
||||
#define REG_TC3_CTRLC (0x42002C06) /**< \brief (TC3) Control C */
|
||||
#define REG_TC3_DBGCTRL (0x42002C08) /**< \brief (TC3) Debug Control */
|
||||
#define REG_TC3_EVCTRL (0x42002C0A) /**< \brief (TC3) Event Control */
|
||||
#define REG_TC3_INTENCLR (0x42002C0C) /**< \brief (TC3) Interrupt Enable Clear */
|
||||
#define REG_TC3_INTENSET (0x42002C0D) /**< \brief (TC3) Interrupt Enable Set */
|
||||
#define REG_TC3_INTFLAG (0x42002C0E) /**< \brief (TC3) Interrupt Flag Status and Clear */
|
||||
#define REG_TC3_STATUS (0x42002C0F) /**< \brief (TC3) Status */
|
||||
#define REG_TC3_COUNT16_COUNT (0x42002C10) /**< \brief (TC3) COUNT16 Counter Value */
|
||||
#define REG_TC3_COUNT16_CC0 (0x42002C18) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT16_CC1 (0x42002C1A) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT32_COUNT (0x42002C10) /**< \brief (TC3) COUNT32 Counter Value */
|
||||
#define REG_TC3_COUNT32_CC0 (0x42002C18) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT32_CC1 (0x42002C1C) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT8_COUNT (0x42002C10) /**< \brief (TC3) COUNT8 Counter Value */
|
||||
#define REG_TC3_COUNT8_PER (0x42002C14) /**< \brief (TC3) COUNT8 Period Value */
|
||||
#define REG_TC3_COUNT8_CC0 (0x42002C18) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT8_CC1 (0x42002C19) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC3_CTRLA (*(RwReg16*)0x42002C00UL) /**< \brief (TC3) Control A */
|
||||
#define REG_TC3_READREQ (*(RwReg16*)0x42002C02UL) /**< \brief (TC3) Read Request */
|
||||
#define REG_TC3_CTRLBCLR (*(RwReg8 *)0x42002C04UL) /**< \brief (TC3) Control B Clear */
|
||||
#define REG_TC3_CTRLBSET (*(RwReg8 *)0x42002C05UL) /**< \brief (TC3) Control B Set */
|
||||
#define REG_TC3_CTRLC (*(RwReg8 *)0x42002C06UL) /**< \brief (TC3) Control C */
|
||||
#define REG_TC3_DBGCTRL (*(RwReg8 *)0x42002C08UL) /**< \brief (TC3) Debug Control */
|
||||
#define REG_TC3_EVCTRL (*(RwReg16*)0x42002C0AUL) /**< \brief (TC3) Event Control */
|
||||
#define REG_TC3_INTENCLR (*(RwReg8 *)0x42002C0CUL) /**< \brief (TC3) Interrupt Enable Clear */
|
||||
#define REG_TC3_INTENSET (*(RwReg8 *)0x42002C0DUL) /**< \brief (TC3) Interrupt Enable Set */
|
||||
#define REG_TC3_INTFLAG (*(RwReg8 *)0x42002C0EUL) /**< \brief (TC3) Interrupt Flag Status and Clear */
|
||||
#define REG_TC3_STATUS (*(RoReg8 *)0x42002C0FUL) /**< \brief (TC3) Status */
|
||||
#define REG_TC3_COUNT16_COUNT (*(RwReg16*)0x42002C10UL) /**< \brief (TC3) COUNT16 Counter Value */
|
||||
#define REG_TC3_COUNT16_CC0 (*(RwReg16*)0x42002C18UL) /**< \brief (TC3) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT16_CC1 (*(RwReg16*)0x42002C1AUL) /**< \brief (TC3) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT32_COUNT (*(RwReg *)0x42002C10UL) /**< \brief (TC3) COUNT32 Counter Value */
|
||||
#define REG_TC3_COUNT32_CC0 (*(RwReg *)0x42002C18UL) /**< \brief (TC3) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT32_CC1 (*(RwReg *)0x42002C1CUL) /**< \brief (TC3) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC3_COUNT8_COUNT (*(RwReg8 *)0x42002C10UL) /**< \brief (TC3) COUNT8 Counter Value */
|
||||
#define REG_TC3_COUNT8_PER (*(RwReg8 *)0x42002C14UL) /**< \brief (TC3) COUNT8 Period Value */
|
||||
#define REG_TC3_COUNT8_CC0 (*(RwReg8 *)0x42002C18UL) /**< \brief (TC3) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC3_COUNT8_CC1 (*(RwReg8 *)0x42002C19UL) /**< \brief (TC3) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC3 peripheral ========== */
|
||||
#define TC3_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC3_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC3_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC3_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC3_DMAC_ID_MC_0 25
|
||||
#define TC3_DMAC_ID_MC_1 26
|
||||
#define TC3_DMAC_ID_MC_LSB 25
|
||||
#define TC3_DMAC_ID_MC_MSB 26
|
||||
#define TC3_DMAC_ID_MC_SIZE 2
|
||||
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
|
||||
#define TC3_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TC3_MASTER 0
|
||||
#define TC3_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC3_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC3_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC3_INSTANCE_ */
|
||||
|
||||
@@ -1,97 +1,97 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC4
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC4_INSTANCE_
|
||||
#define _SAMD21_TC4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC4_CTRLA (0x42003000) /**< \brief (TC4) Control A */
|
||||
#define REG_TC4_READREQ (0x42003002) /**< \brief (TC4) Read Request */
|
||||
#define REG_TC4_CTRLBCLR (0x42003004) /**< \brief (TC4) Control B Clear */
|
||||
#define REG_TC4_CTRLBSET (0x42003005) /**< \brief (TC4) Control B Set */
|
||||
#define REG_TC4_CTRLC (0x42003006) /**< \brief (TC4) Control C */
|
||||
#define REG_TC4_DBGCTRL (0x42003008) /**< \brief (TC4) Debug Control */
|
||||
#define REG_TC4_EVCTRL (0x4200300A) /**< \brief (TC4) Event Control */
|
||||
#define REG_TC4_INTENCLR (0x4200300C) /**< \brief (TC4) Interrupt Enable Clear */
|
||||
#define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */
|
||||
#define REG_TC4_INTFLAG (0x4200300E) /**< \brief (TC4) Interrupt Flag Status and Clear */
|
||||
#define REG_TC4_STATUS (0x4200300F) /**< \brief (TC4) Status */
|
||||
#define REG_TC4_COUNT16_COUNT (0x42003010) /**< \brief (TC4) COUNT16 Counter Value */
|
||||
#define REG_TC4_COUNT16_CC0 (0x42003018) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT16_CC1 (0x4200301A) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT32_COUNT (0x42003010) /**< \brief (TC4) COUNT32 Counter Value */
|
||||
#define REG_TC4_COUNT32_CC0 (0x42003018) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT32_CC1 (0x4200301C) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT8_COUNT (0x42003010) /**< \brief (TC4) COUNT8 Counter Value */
|
||||
#define REG_TC4_COUNT8_PER (0x42003014) /**< \brief (TC4) COUNT8 Period Value */
|
||||
#define REG_TC4_COUNT8_CC0 (0x42003018) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT8_CC1 (0x42003019) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC4_CTRLA (*(RwReg16*)0x42003000UL) /**< \brief (TC4) Control A */
|
||||
#define REG_TC4_READREQ (*(RwReg16*)0x42003002UL) /**< \brief (TC4) Read Request */
|
||||
#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004UL) /**< \brief (TC4) Control B Clear */
|
||||
#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005UL) /**< \brief (TC4) Control B Set */
|
||||
#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006UL) /**< \brief (TC4) Control C */
|
||||
#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008UL) /**< \brief (TC4) Debug Control */
|
||||
#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AUL) /**< \brief (TC4) Event Control */
|
||||
#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CUL) /**< \brief (TC4) Interrupt Enable Clear */
|
||||
#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set */
|
||||
#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
|
||||
#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FUL) /**< \brief (TC4) Status */
|
||||
#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010UL) /**< \brief (TC4) COUNT16 Counter Value */
|
||||
#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018UL) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AUL) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010UL) /**< \brief (TC4) COUNT32 Counter Value */
|
||||
#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018UL) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CUL) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010UL) /**< \brief (TC4) COUNT8 Counter Value */
|
||||
#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014UL) /**< \brief (TC4) COUNT8 Period Value */
|
||||
#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018UL) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019UL) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC4 peripheral ========== */
|
||||
#define TC4_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC4_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC4_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC4_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC4_DMAC_ID_MC_0 28
|
||||
#define TC4_DMAC_ID_MC_1 29
|
||||
#define TC4_DMAC_ID_MC_LSB 28
|
||||
#define TC4_DMAC_ID_MC_MSB 29
|
||||
#define TC4_DMAC_ID_MC_SIZE 2
|
||||
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
|
||||
#define TC4_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC4_MASTER 1
|
||||
#define TC4_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC4_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC4_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC4
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC4_INSTANCE_
|
||||
#define _SAMD21_TC4_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC4_CTRLA (0x42003000) /**< \brief (TC4) Control A */
|
||||
#define REG_TC4_READREQ (0x42003002) /**< \brief (TC4) Read Request */
|
||||
#define REG_TC4_CTRLBCLR (0x42003004) /**< \brief (TC4) Control B Clear */
|
||||
#define REG_TC4_CTRLBSET (0x42003005) /**< \brief (TC4) Control B Set */
|
||||
#define REG_TC4_CTRLC (0x42003006) /**< \brief (TC4) Control C */
|
||||
#define REG_TC4_DBGCTRL (0x42003008) /**< \brief (TC4) Debug Control */
|
||||
#define REG_TC4_EVCTRL (0x4200300A) /**< \brief (TC4) Event Control */
|
||||
#define REG_TC4_INTENCLR (0x4200300C) /**< \brief (TC4) Interrupt Enable Clear */
|
||||
#define REG_TC4_INTENSET (0x4200300D) /**< \brief (TC4) Interrupt Enable Set */
|
||||
#define REG_TC4_INTFLAG (0x4200300E) /**< \brief (TC4) Interrupt Flag Status and Clear */
|
||||
#define REG_TC4_STATUS (0x4200300F) /**< \brief (TC4) Status */
|
||||
#define REG_TC4_COUNT16_COUNT (0x42003010) /**< \brief (TC4) COUNT16 Counter Value */
|
||||
#define REG_TC4_COUNT16_CC0 (0x42003018) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT16_CC1 (0x4200301A) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT32_COUNT (0x42003010) /**< \brief (TC4) COUNT32 Counter Value */
|
||||
#define REG_TC4_COUNT32_CC0 (0x42003018) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT32_CC1 (0x4200301C) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT8_COUNT (0x42003010) /**< \brief (TC4) COUNT8 Counter Value */
|
||||
#define REG_TC4_COUNT8_PER (0x42003014) /**< \brief (TC4) COUNT8 Period Value */
|
||||
#define REG_TC4_COUNT8_CC0 (0x42003018) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT8_CC1 (0x42003019) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC4_CTRLA (*(RwReg16*)0x42003000UL) /**< \brief (TC4) Control A */
|
||||
#define REG_TC4_READREQ (*(RwReg16*)0x42003002UL) /**< \brief (TC4) Read Request */
|
||||
#define REG_TC4_CTRLBCLR (*(RwReg8 *)0x42003004UL) /**< \brief (TC4) Control B Clear */
|
||||
#define REG_TC4_CTRLBSET (*(RwReg8 *)0x42003005UL) /**< \brief (TC4) Control B Set */
|
||||
#define REG_TC4_CTRLC (*(RwReg8 *)0x42003006UL) /**< \brief (TC4) Control C */
|
||||
#define REG_TC4_DBGCTRL (*(RwReg8 *)0x42003008UL) /**< \brief (TC4) Debug Control */
|
||||
#define REG_TC4_EVCTRL (*(RwReg16*)0x4200300AUL) /**< \brief (TC4) Event Control */
|
||||
#define REG_TC4_INTENCLR (*(RwReg8 *)0x4200300CUL) /**< \brief (TC4) Interrupt Enable Clear */
|
||||
#define REG_TC4_INTENSET (*(RwReg8 *)0x4200300DUL) /**< \brief (TC4) Interrupt Enable Set */
|
||||
#define REG_TC4_INTFLAG (*(RwReg8 *)0x4200300EUL) /**< \brief (TC4) Interrupt Flag Status and Clear */
|
||||
#define REG_TC4_STATUS (*(RoReg8 *)0x4200300FUL) /**< \brief (TC4) Status */
|
||||
#define REG_TC4_COUNT16_COUNT (*(RwReg16*)0x42003010UL) /**< \brief (TC4) COUNT16 Counter Value */
|
||||
#define REG_TC4_COUNT16_CC0 (*(RwReg16*)0x42003018UL) /**< \brief (TC4) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT16_CC1 (*(RwReg16*)0x4200301AUL) /**< \brief (TC4) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT32_COUNT (*(RwReg *)0x42003010UL) /**< \brief (TC4) COUNT32 Counter Value */
|
||||
#define REG_TC4_COUNT32_CC0 (*(RwReg *)0x42003018UL) /**< \brief (TC4) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT32_CC1 (*(RwReg *)0x4200301CUL) /**< \brief (TC4) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC4_COUNT8_COUNT (*(RwReg8 *)0x42003010UL) /**< \brief (TC4) COUNT8 Counter Value */
|
||||
#define REG_TC4_COUNT8_PER (*(RwReg8 *)0x42003014UL) /**< \brief (TC4) COUNT8 Period Value */
|
||||
#define REG_TC4_COUNT8_CC0 (*(RwReg8 *)0x42003018UL) /**< \brief (TC4) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC4_COUNT8_CC1 (*(RwReg8 *)0x42003019UL) /**< \brief (TC4) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC4 peripheral ========== */
|
||||
#define TC4_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC4_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC4_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC4_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC4_DMAC_ID_MC_0 28
|
||||
#define TC4_DMAC_ID_MC_1 29
|
||||
#define TC4_DMAC_ID_MC_LSB 28
|
||||
#define TC4_DMAC_ID_MC_MSB 29
|
||||
#define TC4_DMAC_ID_MC_SIZE 2
|
||||
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
|
||||
#define TC4_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC4_MASTER 1
|
||||
#define TC4_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC4_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC4_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC4_INSTANCE_ */
|
||||
|
||||
@@ -1,97 +1,97 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC5
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC5_INSTANCE_
|
||||
#define _SAMD21_TC5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC5_CTRLA (0x42003400) /**< \brief (TC5) Control A */
|
||||
#define REG_TC5_READREQ (0x42003402) /**< \brief (TC5) Read Request */
|
||||
#define REG_TC5_CTRLBCLR (0x42003404) /**< \brief (TC5) Control B Clear */
|
||||
#define REG_TC5_CTRLBSET (0x42003405) /**< \brief (TC5) Control B Set */
|
||||
#define REG_TC5_CTRLC (0x42003406) /**< \brief (TC5) Control C */
|
||||
#define REG_TC5_DBGCTRL (0x42003408) /**< \brief (TC5) Debug Control */
|
||||
#define REG_TC5_EVCTRL (0x4200340A) /**< \brief (TC5) Event Control */
|
||||
#define REG_TC5_INTENCLR (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */
|
||||
#define REG_TC5_INTENSET (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */
|
||||
#define REG_TC5_INTFLAG (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */
|
||||
#define REG_TC5_STATUS (0x4200340F) /**< \brief (TC5) Status */
|
||||
#define REG_TC5_COUNT16_COUNT (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */
|
||||
#define REG_TC5_COUNT16_CC0 (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT16_CC1 (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT32_COUNT (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */
|
||||
#define REG_TC5_COUNT32_CC0 (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT32_CC1 (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT8_COUNT (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */
|
||||
#define REG_TC5_COUNT8_PER (0x42003414) /**< \brief (TC5) COUNT8 Period Value */
|
||||
#define REG_TC5_COUNT8_CC0 (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT8_CC1 (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC5_CTRLA (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */
|
||||
#define REG_TC5_READREQ (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */
|
||||
#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */
|
||||
#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */
|
||||
#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */
|
||||
#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */
|
||||
#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */
|
||||
#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */
|
||||
#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */
|
||||
#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
|
||||
#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */
|
||||
#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */
|
||||
#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */
|
||||
#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */
|
||||
#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */
|
||||
#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC5 peripheral ========== */
|
||||
#define TC5_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC5_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC5_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC5_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC5_DMAC_ID_MC_0 31
|
||||
#define TC5_DMAC_ID_MC_1 32
|
||||
#define TC5_DMAC_ID_MC_LSB 31
|
||||
#define TC5_DMAC_ID_MC_MSB 32
|
||||
#define TC5_DMAC_ID_MC_SIZE 2
|
||||
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
|
||||
#define TC5_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC5_MASTER 0
|
||||
#define TC5_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC5_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC5_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC5
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC5_INSTANCE_
|
||||
#define _SAMD21_TC5_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC5 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC5_CTRLA (0x42003400) /**< \brief (TC5) Control A */
|
||||
#define REG_TC5_READREQ (0x42003402) /**< \brief (TC5) Read Request */
|
||||
#define REG_TC5_CTRLBCLR (0x42003404) /**< \brief (TC5) Control B Clear */
|
||||
#define REG_TC5_CTRLBSET (0x42003405) /**< \brief (TC5) Control B Set */
|
||||
#define REG_TC5_CTRLC (0x42003406) /**< \brief (TC5) Control C */
|
||||
#define REG_TC5_DBGCTRL (0x42003408) /**< \brief (TC5) Debug Control */
|
||||
#define REG_TC5_EVCTRL (0x4200340A) /**< \brief (TC5) Event Control */
|
||||
#define REG_TC5_INTENCLR (0x4200340C) /**< \brief (TC5) Interrupt Enable Clear */
|
||||
#define REG_TC5_INTENSET (0x4200340D) /**< \brief (TC5) Interrupt Enable Set */
|
||||
#define REG_TC5_INTFLAG (0x4200340E) /**< \brief (TC5) Interrupt Flag Status and Clear */
|
||||
#define REG_TC5_STATUS (0x4200340F) /**< \brief (TC5) Status */
|
||||
#define REG_TC5_COUNT16_COUNT (0x42003410) /**< \brief (TC5) COUNT16 Counter Value */
|
||||
#define REG_TC5_COUNT16_CC0 (0x42003418) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT16_CC1 (0x4200341A) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT32_COUNT (0x42003410) /**< \brief (TC5) COUNT32 Counter Value */
|
||||
#define REG_TC5_COUNT32_CC0 (0x42003418) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT32_CC1 (0x4200341C) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT8_COUNT (0x42003410) /**< \brief (TC5) COUNT8 Counter Value */
|
||||
#define REG_TC5_COUNT8_PER (0x42003414) /**< \brief (TC5) COUNT8 Period Value */
|
||||
#define REG_TC5_COUNT8_CC0 (0x42003418) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT8_CC1 (0x42003419) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC5_CTRLA (*(RwReg16*)0x42003400UL) /**< \brief (TC5) Control A */
|
||||
#define REG_TC5_READREQ (*(RwReg16*)0x42003402UL) /**< \brief (TC5) Read Request */
|
||||
#define REG_TC5_CTRLBCLR (*(RwReg8 *)0x42003404UL) /**< \brief (TC5) Control B Clear */
|
||||
#define REG_TC5_CTRLBSET (*(RwReg8 *)0x42003405UL) /**< \brief (TC5) Control B Set */
|
||||
#define REG_TC5_CTRLC (*(RwReg8 *)0x42003406UL) /**< \brief (TC5) Control C */
|
||||
#define REG_TC5_DBGCTRL (*(RwReg8 *)0x42003408UL) /**< \brief (TC5) Debug Control */
|
||||
#define REG_TC5_EVCTRL (*(RwReg16*)0x4200340AUL) /**< \brief (TC5) Event Control */
|
||||
#define REG_TC5_INTENCLR (*(RwReg8 *)0x4200340CUL) /**< \brief (TC5) Interrupt Enable Clear */
|
||||
#define REG_TC5_INTENSET (*(RwReg8 *)0x4200340DUL) /**< \brief (TC5) Interrupt Enable Set */
|
||||
#define REG_TC5_INTFLAG (*(RwReg8 *)0x4200340EUL) /**< \brief (TC5) Interrupt Flag Status and Clear */
|
||||
#define REG_TC5_STATUS (*(RoReg8 *)0x4200340FUL) /**< \brief (TC5) Status */
|
||||
#define REG_TC5_COUNT16_COUNT (*(RwReg16*)0x42003410UL) /**< \brief (TC5) COUNT16 Counter Value */
|
||||
#define REG_TC5_COUNT16_CC0 (*(RwReg16*)0x42003418UL) /**< \brief (TC5) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT16_CC1 (*(RwReg16*)0x4200341AUL) /**< \brief (TC5) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT32_COUNT (*(RwReg *)0x42003410UL) /**< \brief (TC5) COUNT32 Counter Value */
|
||||
#define REG_TC5_COUNT32_CC0 (*(RwReg *)0x42003418UL) /**< \brief (TC5) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT32_CC1 (*(RwReg *)0x4200341CUL) /**< \brief (TC5) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC5_COUNT8_COUNT (*(RwReg8 *)0x42003410UL) /**< \brief (TC5) COUNT8 Counter Value */
|
||||
#define REG_TC5_COUNT8_PER (*(RwReg8 *)0x42003414UL) /**< \brief (TC5) COUNT8 Period Value */
|
||||
#define REG_TC5_COUNT8_CC0 (*(RwReg8 *)0x42003418UL) /**< \brief (TC5) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC5_COUNT8_CC1 (*(RwReg8 *)0x42003419UL) /**< \brief (TC5) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC5 peripheral ========== */
|
||||
#define TC5_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC5_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC5_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC5_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC5_DMAC_ID_MC_0 31
|
||||
#define TC5_DMAC_ID_MC_1 32
|
||||
#define TC5_DMAC_ID_MC_LSB 31
|
||||
#define TC5_DMAC_ID_MC_MSB 32
|
||||
#define TC5_DMAC_ID_MC_SIZE 2
|
||||
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
|
||||
#define TC5_GCLK_ID 28 // Index of Generic Clock
|
||||
#define TC5_MASTER 0
|
||||
#define TC5_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC5_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC5_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC5_INSTANCE_ */
|
||||
|
||||
@@ -1,97 +1,97 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC6
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC6_INSTANCE_
|
||||
#define _SAMD21_TC6_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC6 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC6_CTRLA (0x42003800) /**< \brief (TC6) Control A */
|
||||
#define REG_TC6_READREQ (0x42003802) /**< \brief (TC6) Read Request */
|
||||
#define REG_TC6_CTRLBCLR (0x42003804) /**< \brief (TC6) Control B Clear */
|
||||
#define REG_TC6_CTRLBSET (0x42003805) /**< \brief (TC6) Control B Set */
|
||||
#define REG_TC6_CTRLC (0x42003806) /**< \brief (TC6) Control C */
|
||||
#define REG_TC6_DBGCTRL (0x42003808) /**< \brief (TC6) Debug Control */
|
||||
#define REG_TC6_EVCTRL (0x4200380A) /**< \brief (TC6) Event Control */
|
||||
#define REG_TC6_INTENCLR (0x4200380C) /**< \brief (TC6) Interrupt Enable Clear */
|
||||
#define REG_TC6_INTENSET (0x4200380D) /**< \brief (TC6) Interrupt Enable Set */
|
||||
#define REG_TC6_INTFLAG (0x4200380E) /**< \brief (TC6) Interrupt Flag Status and Clear */
|
||||
#define REG_TC6_STATUS (0x4200380F) /**< \brief (TC6) Status */
|
||||
#define REG_TC6_COUNT16_COUNT (0x42003810) /**< \brief (TC6) COUNT16 Counter Value */
|
||||
#define REG_TC6_COUNT16_CC0 (0x42003818) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT16_CC1 (0x4200381A) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT32_COUNT (0x42003810) /**< \brief (TC6) COUNT32 Counter Value */
|
||||
#define REG_TC6_COUNT32_CC0 (0x42003818) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT32_CC1 (0x4200381C) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT8_COUNT (0x42003810) /**< \brief (TC6) COUNT8 Counter Value */
|
||||
#define REG_TC6_COUNT8_PER (0x42003814) /**< \brief (TC6) COUNT8 Period Value */
|
||||
#define REG_TC6_COUNT8_CC0 (0x42003818) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT8_CC1 (0x42003819) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC6_CTRLA (*(RwReg16*)0x42003800UL) /**< \brief (TC6) Control A */
|
||||
#define REG_TC6_READREQ (*(RwReg16*)0x42003802UL) /**< \brief (TC6) Read Request */
|
||||
#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC6) Control B Clear */
|
||||
#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC6) Control B Set */
|
||||
#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806UL) /**< \brief (TC6) Control C */
|
||||
#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808UL) /**< \brief (TC6) Debug Control */
|
||||
#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AUL) /**< \brief (TC6) Event Control */
|
||||
#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CUL) /**< \brief (TC6) Interrupt Enable Clear */
|
||||
#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DUL) /**< \brief (TC6) Interrupt Enable Set */
|
||||
#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
|
||||
#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FUL) /**< \brief (TC6) Status */
|
||||
#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810UL) /**< \brief (TC6) COUNT16 Counter Value */
|
||||
#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818UL) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AUL) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810UL) /**< \brief (TC6) COUNT32 Counter Value */
|
||||
#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818UL) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CUL) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810UL) /**< \brief (TC6) COUNT8 Counter Value */
|
||||
#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814UL) /**< \brief (TC6) COUNT8 Period Value */
|
||||
#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818UL) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819UL) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC6 peripheral ========== */
|
||||
#define TC6_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC6_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC6_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC6_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC6_DMAC_ID_MC_0 34
|
||||
#define TC6_DMAC_ID_MC_1 35
|
||||
#define TC6_DMAC_ID_MC_LSB 34
|
||||
#define TC6_DMAC_ID_MC_MSB 35
|
||||
#define TC6_DMAC_ID_MC_SIZE 2
|
||||
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
|
||||
#define TC6_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC6_MASTER 1
|
||||
#define TC6_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC6_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC6_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC6_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC6
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC6_INSTANCE_
|
||||
#define _SAMD21_TC6_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC6 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC6_CTRLA (0x42003800) /**< \brief (TC6) Control A */
|
||||
#define REG_TC6_READREQ (0x42003802) /**< \brief (TC6) Read Request */
|
||||
#define REG_TC6_CTRLBCLR (0x42003804) /**< \brief (TC6) Control B Clear */
|
||||
#define REG_TC6_CTRLBSET (0x42003805) /**< \brief (TC6) Control B Set */
|
||||
#define REG_TC6_CTRLC (0x42003806) /**< \brief (TC6) Control C */
|
||||
#define REG_TC6_DBGCTRL (0x42003808) /**< \brief (TC6) Debug Control */
|
||||
#define REG_TC6_EVCTRL (0x4200380A) /**< \brief (TC6) Event Control */
|
||||
#define REG_TC6_INTENCLR (0x4200380C) /**< \brief (TC6) Interrupt Enable Clear */
|
||||
#define REG_TC6_INTENSET (0x4200380D) /**< \brief (TC6) Interrupt Enable Set */
|
||||
#define REG_TC6_INTFLAG (0x4200380E) /**< \brief (TC6) Interrupt Flag Status and Clear */
|
||||
#define REG_TC6_STATUS (0x4200380F) /**< \brief (TC6) Status */
|
||||
#define REG_TC6_COUNT16_COUNT (0x42003810) /**< \brief (TC6) COUNT16 Counter Value */
|
||||
#define REG_TC6_COUNT16_CC0 (0x42003818) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT16_CC1 (0x4200381A) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT32_COUNT (0x42003810) /**< \brief (TC6) COUNT32 Counter Value */
|
||||
#define REG_TC6_COUNT32_CC0 (0x42003818) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT32_CC1 (0x4200381C) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT8_COUNT (0x42003810) /**< \brief (TC6) COUNT8 Counter Value */
|
||||
#define REG_TC6_COUNT8_PER (0x42003814) /**< \brief (TC6) COUNT8 Period Value */
|
||||
#define REG_TC6_COUNT8_CC0 (0x42003818) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT8_CC1 (0x42003819) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC6_CTRLA (*(RwReg16*)0x42003800UL) /**< \brief (TC6) Control A */
|
||||
#define REG_TC6_READREQ (*(RwReg16*)0x42003802UL) /**< \brief (TC6) Read Request */
|
||||
#define REG_TC6_CTRLBCLR (*(RwReg8 *)0x42003804UL) /**< \brief (TC6) Control B Clear */
|
||||
#define REG_TC6_CTRLBSET (*(RwReg8 *)0x42003805UL) /**< \brief (TC6) Control B Set */
|
||||
#define REG_TC6_CTRLC (*(RwReg8 *)0x42003806UL) /**< \brief (TC6) Control C */
|
||||
#define REG_TC6_DBGCTRL (*(RwReg8 *)0x42003808UL) /**< \brief (TC6) Debug Control */
|
||||
#define REG_TC6_EVCTRL (*(RwReg16*)0x4200380AUL) /**< \brief (TC6) Event Control */
|
||||
#define REG_TC6_INTENCLR (*(RwReg8 *)0x4200380CUL) /**< \brief (TC6) Interrupt Enable Clear */
|
||||
#define REG_TC6_INTENSET (*(RwReg8 *)0x4200380DUL) /**< \brief (TC6) Interrupt Enable Set */
|
||||
#define REG_TC6_INTFLAG (*(RwReg8 *)0x4200380EUL) /**< \brief (TC6) Interrupt Flag Status and Clear */
|
||||
#define REG_TC6_STATUS (*(RoReg8 *)0x4200380FUL) /**< \brief (TC6) Status */
|
||||
#define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x42003810UL) /**< \brief (TC6) COUNT16 Counter Value */
|
||||
#define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x42003818UL) /**< \brief (TC6) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4200381AUL) /**< \brief (TC6) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT32_COUNT (*(RwReg *)0x42003810UL) /**< \brief (TC6) COUNT32 Counter Value */
|
||||
#define REG_TC6_COUNT32_CC0 (*(RwReg *)0x42003818UL) /**< \brief (TC6) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT32_CC1 (*(RwReg *)0x4200381CUL) /**< \brief (TC6) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x42003810UL) /**< \brief (TC6) COUNT8 Counter Value */
|
||||
#define REG_TC6_COUNT8_PER (*(RwReg8 *)0x42003814UL) /**< \brief (TC6) COUNT8 Period Value */
|
||||
#define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x42003818UL) /**< \brief (TC6) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x42003819UL) /**< \brief (TC6) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC6 peripheral ========== */
|
||||
#define TC6_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC6_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC6_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC6_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC6_DMAC_ID_MC_0 34
|
||||
#define TC6_DMAC_ID_MC_1 35
|
||||
#define TC6_DMAC_ID_MC_LSB 34
|
||||
#define TC6_DMAC_ID_MC_MSB 35
|
||||
#define TC6_DMAC_ID_MC_SIZE 2
|
||||
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
|
||||
#define TC6_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC6_MASTER 1
|
||||
#define TC6_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC6_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC6_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC6_INSTANCE_ */
|
||||
|
||||
@@ -1,97 +1,97 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC7
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC7_INSTANCE_
|
||||
#define _SAMD21_TC7_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC7 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC7_CTRLA (0x42003C00) /**< \brief (TC7) Control A */
|
||||
#define REG_TC7_READREQ (0x42003C02) /**< \brief (TC7) Read Request */
|
||||
#define REG_TC7_CTRLBCLR (0x42003C04) /**< \brief (TC7) Control B Clear */
|
||||
#define REG_TC7_CTRLBSET (0x42003C05) /**< \brief (TC7) Control B Set */
|
||||
#define REG_TC7_CTRLC (0x42003C06) /**< \brief (TC7) Control C */
|
||||
#define REG_TC7_DBGCTRL (0x42003C08) /**< \brief (TC7) Debug Control */
|
||||
#define REG_TC7_EVCTRL (0x42003C0A) /**< \brief (TC7) Event Control */
|
||||
#define REG_TC7_INTENCLR (0x42003C0C) /**< \brief (TC7) Interrupt Enable Clear */
|
||||
#define REG_TC7_INTENSET (0x42003C0D) /**< \brief (TC7) Interrupt Enable Set */
|
||||
#define REG_TC7_INTFLAG (0x42003C0E) /**< \brief (TC7) Interrupt Flag Status and Clear */
|
||||
#define REG_TC7_STATUS (0x42003C0F) /**< \brief (TC7) Status */
|
||||
#define REG_TC7_COUNT16_COUNT (0x42003C10) /**< \brief (TC7) COUNT16 Counter Value */
|
||||
#define REG_TC7_COUNT16_CC0 (0x42003C18) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT16_CC1 (0x42003C1A) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT32_COUNT (0x42003C10) /**< \brief (TC7) COUNT32 Counter Value */
|
||||
#define REG_TC7_COUNT32_CC0 (0x42003C18) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT32_CC1 (0x42003C1C) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT8_COUNT (0x42003C10) /**< \brief (TC7) COUNT8 Counter Value */
|
||||
#define REG_TC7_COUNT8_PER (0x42003C14) /**< \brief (TC7) COUNT8 Period Value */
|
||||
#define REG_TC7_COUNT8_CC0 (0x42003C18) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT8_CC1 (0x42003C19) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00UL) /**< \brief (TC7) Control A */
|
||||
#define REG_TC7_READREQ (*(RwReg16*)0x42003C02UL) /**< \brief (TC7) Read Request */
|
||||
#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04UL) /**< \brief (TC7) Control B Clear */
|
||||
#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05UL) /**< \brief (TC7) Control B Set */
|
||||
#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06UL) /**< \brief (TC7) Control C */
|
||||
#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08UL) /**< \brief (TC7) Debug Control */
|
||||
#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AUL) /**< \brief (TC7) Event Control */
|
||||
#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC7) Interrupt Enable Clear */
|
||||
#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC7) Interrupt Enable Set */
|
||||
#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EUL) /**< \brief (TC7) Interrupt Flag Status and Clear */
|
||||
#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FUL) /**< \brief (TC7) Status */
|
||||
#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10UL) /**< \brief (TC7) COUNT16 Counter Value */
|
||||
#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18UL) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AUL) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10UL) /**< \brief (TC7) COUNT32 Counter Value */
|
||||
#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18UL) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CUL) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10UL) /**< \brief (TC7) COUNT8 Counter Value */
|
||||
#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14UL) /**< \brief (TC7) COUNT8 Period Value */
|
||||
#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC7 peripheral ========== */
|
||||
#define TC7_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC7_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC7_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC7_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC7_DMAC_ID_MC_0 37
|
||||
#define TC7_DMAC_ID_MC_1 38
|
||||
#define TC7_DMAC_ID_MC_LSB 37
|
||||
#define TC7_DMAC_ID_MC_MSB 38
|
||||
#define TC7_DMAC_ID_MC_SIZE 2
|
||||
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
|
||||
#define TC7_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC7_MASTER 0
|
||||
#define TC7_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC7_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC7_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC7_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC7
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TC7_INSTANCE_
|
||||
#define _SAMD21_TC7_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TC7 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TC7_CTRLA (0x42003C00) /**< \brief (TC7) Control A */
|
||||
#define REG_TC7_READREQ (0x42003C02) /**< \brief (TC7) Read Request */
|
||||
#define REG_TC7_CTRLBCLR (0x42003C04) /**< \brief (TC7) Control B Clear */
|
||||
#define REG_TC7_CTRLBSET (0x42003C05) /**< \brief (TC7) Control B Set */
|
||||
#define REG_TC7_CTRLC (0x42003C06) /**< \brief (TC7) Control C */
|
||||
#define REG_TC7_DBGCTRL (0x42003C08) /**< \brief (TC7) Debug Control */
|
||||
#define REG_TC7_EVCTRL (0x42003C0A) /**< \brief (TC7) Event Control */
|
||||
#define REG_TC7_INTENCLR (0x42003C0C) /**< \brief (TC7) Interrupt Enable Clear */
|
||||
#define REG_TC7_INTENSET (0x42003C0D) /**< \brief (TC7) Interrupt Enable Set */
|
||||
#define REG_TC7_INTFLAG (0x42003C0E) /**< \brief (TC7) Interrupt Flag Status and Clear */
|
||||
#define REG_TC7_STATUS (0x42003C0F) /**< \brief (TC7) Status */
|
||||
#define REG_TC7_COUNT16_COUNT (0x42003C10) /**< \brief (TC7) COUNT16 Counter Value */
|
||||
#define REG_TC7_COUNT16_CC0 (0x42003C18) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT16_CC1 (0x42003C1A) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT32_COUNT (0x42003C10) /**< \brief (TC7) COUNT32 Counter Value */
|
||||
#define REG_TC7_COUNT32_CC0 (0x42003C18) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT32_CC1 (0x42003C1C) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT8_COUNT (0x42003C10) /**< \brief (TC7) COUNT8 Counter Value */
|
||||
#define REG_TC7_COUNT8_PER (0x42003C14) /**< \brief (TC7) COUNT8 Period Value */
|
||||
#define REG_TC7_COUNT8_CC0 (0x42003C18) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT8_CC1 (0x42003C19) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
|
||||
#else
|
||||
#define REG_TC7_CTRLA (*(RwReg16*)0x42003C00UL) /**< \brief (TC7) Control A */
|
||||
#define REG_TC7_READREQ (*(RwReg16*)0x42003C02UL) /**< \brief (TC7) Read Request */
|
||||
#define REG_TC7_CTRLBCLR (*(RwReg8 *)0x42003C04UL) /**< \brief (TC7) Control B Clear */
|
||||
#define REG_TC7_CTRLBSET (*(RwReg8 *)0x42003C05UL) /**< \brief (TC7) Control B Set */
|
||||
#define REG_TC7_CTRLC (*(RwReg8 *)0x42003C06UL) /**< \brief (TC7) Control C */
|
||||
#define REG_TC7_DBGCTRL (*(RwReg8 *)0x42003C08UL) /**< \brief (TC7) Debug Control */
|
||||
#define REG_TC7_EVCTRL (*(RwReg16*)0x42003C0AUL) /**< \brief (TC7) Event Control */
|
||||
#define REG_TC7_INTENCLR (*(RwReg8 *)0x42003C0CUL) /**< \brief (TC7) Interrupt Enable Clear */
|
||||
#define REG_TC7_INTENSET (*(RwReg8 *)0x42003C0DUL) /**< \brief (TC7) Interrupt Enable Set */
|
||||
#define REG_TC7_INTFLAG (*(RwReg8 *)0x42003C0EUL) /**< \brief (TC7) Interrupt Flag Status and Clear */
|
||||
#define REG_TC7_STATUS (*(RoReg8 *)0x42003C0FUL) /**< \brief (TC7) Status */
|
||||
#define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x42003C10UL) /**< \brief (TC7) COUNT16 Counter Value */
|
||||
#define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x42003C18UL) /**< \brief (TC7) COUNT16 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x42003C1AUL) /**< \brief (TC7) COUNT16 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT32_COUNT (*(RwReg *)0x42003C10UL) /**< \brief (TC7) COUNT32 Counter Value */
|
||||
#define REG_TC7_COUNT32_CC0 (*(RwReg *)0x42003C18UL) /**< \brief (TC7) COUNT32 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT32_CC1 (*(RwReg *)0x42003C1CUL) /**< \brief (TC7) COUNT32 Compare/Capture 1 */
|
||||
#define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x42003C10UL) /**< \brief (TC7) COUNT8 Counter Value */
|
||||
#define REG_TC7_COUNT8_PER (*(RwReg8 *)0x42003C14UL) /**< \brief (TC7) COUNT8 Period Value */
|
||||
#define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x42003C18UL) /**< \brief (TC7) COUNT8 Compare/Capture 0 */
|
||||
#define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x42003C19UL) /**< \brief (TC7) COUNT8 Compare/Capture 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TC7 peripheral ========== */
|
||||
#define TC7_CC8_NUM 2 // Number of 8-bit Counters
|
||||
#define TC7_CC16_NUM 2 // Number of 16-bit Counters
|
||||
#define TC7_CC32_NUM 2 // Number of 32-bit Counters
|
||||
#define TC7_DITHERING_EXT 0 // Dithering feature implemented
|
||||
#define TC7_DMAC_ID_MC_0 37
|
||||
#define TC7_DMAC_ID_MC_1 38
|
||||
#define TC7_DMAC_ID_MC_LSB 37
|
||||
#define TC7_DMAC_ID_MC_MSB 38
|
||||
#define TC7_DMAC_ID_MC_SIZE 2
|
||||
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
|
||||
#define TC7_GCLK_ID 29 // Index of Generic Clock
|
||||
#define TC7_MASTER 0
|
||||
#define TC7_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TC7_PERIOD_EXT 0 // Period feature implemented
|
||||
#define TC7_SHADOW_EXT 0 // Shadow feature implemented
|
||||
|
||||
#endif /* _SAMD21_TC7_INSTANCE_ */
|
||||
|
||||
@@ -1,117 +1,117 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC0_INSTANCE_
|
||||
#define _SAMD21_TCC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC0_CTRLA (0x42002000) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (0x42002004) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (0x42002005) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (0x42002008) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (0x4200200C) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (0x42002010) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (0x42002014) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (0x42002018) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (0x4200201E) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (0x42002020) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (0x42002024) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (0x42002028) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (0x4200202C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (0x42002030) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (0x42002034) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (0x42002038) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (0x4200203C) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (0x42002040) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (0x42002044) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (0x42002048) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (0x4200204C) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (0x42002050) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (0x42002064) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (0x42002068) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (0x4200206C) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (0x42002070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (0x42002074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (0x42002078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (0x4200207C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#else
|
||||
#define REG_TCC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008UL) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014UL) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018UL) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EUL) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020UL) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024UL) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (*(RwReg *)0x42002028UL) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (*(RwReg *)0x42002030UL) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (*(RwReg *)0x42002034UL) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (*(RwReg16*)0x42002038UL) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (*(RwReg *)0x4200203CUL) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (*(RwReg *)0x42002040UL) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (*(RwReg *)0x42002044UL) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (*(RwReg *)0x42002048UL) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (*(RwReg *)0x4200204CUL) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (*(RwReg *)0x42002050UL) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (*(RwReg16*)0x42002064UL) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (*(RwReg *)0x42002068UL) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (*(RwReg *)0x4200206CUL) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (*(RwReg *)0x42002070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (*(RwReg *)0x42002074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (*(RwReg *)0x42002078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC0 peripheral ========== */
|
||||
#define TCC0_CC_NUM 4 // Number of Compare/Capture units
|
||||
#define TCC0_DITHERING 1 // Dithering feature implemented
|
||||
#define TCC0_DMAC_ID_MC_0 14
|
||||
#define TCC0_DMAC_ID_MC_1 15
|
||||
#define TCC0_DMAC_ID_MC_2 16
|
||||
#define TCC0_DMAC_ID_MC_3 17
|
||||
#define TCC0_DMAC_ID_MC_LSB 14
|
||||
#define TCC0_DMAC_ID_MC_MSB 17
|
||||
#define TCC0_DMAC_ID_MC_SIZE 4
|
||||
#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
|
||||
#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
|
||||
#define TCC0_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC0_OTMX 1 // Output Matrix feature implemented
|
||||
#define TCC0_OW_NUM 8 // Number of Output Waveforms
|
||||
#define TCC0_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC0_SIZE 24
|
||||
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
|
||||
#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC0_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC0
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC0_INSTANCE_
|
||||
#define _SAMD21_TCC0_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC0_CTRLA (0x42002000) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (0x42002004) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (0x42002005) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (0x42002008) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (0x4200200C) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (0x42002010) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (0x42002014) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (0x42002018) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (0x4200201E) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (0x42002020) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (0x42002024) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (0x42002028) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (0x4200202C) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (0x42002030) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (0x42002034) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (0x42002038) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (0x4200203C) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (0x42002040) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (0x42002044) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (0x42002048) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (0x4200204C) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (0x42002050) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (0x42002064) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (0x42002068) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (0x4200206C) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (0x42002070) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (0x42002074) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (0x42002078) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (0x4200207C) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#else
|
||||
#define REG_TCC0_CTRLA (*(RwReg *)0x42002000UL) /**< \brief (TCC0) Control A */
|
||||
#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x42002004UL) /**< \brief (TCC0) Control B Clear */
|
||||
#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x42002005UL) /**< \brief (TCC0) Control B Set */
|
||||
#define REG_TCC0_SYNCBUSY (*(RoReg *)0x42002008UL) /**< \brief (TCC0) Synchronization Busy */
|
||||
#define REG_TCC0_FCTRLA (*(RwReg *)0x4200200CUL) /**< \brief (TCC0) Recoverable Fault A Configuration */
|
||||
#define REG_TCC0_FCTRLB (*(RwReg *)0x42002010UL) /**< \brief (TCC0) Recoverable Fault B Configuration */
|
||||
#define REG_TCC0_WEXCTRL (*(RwReg *)0x42002014UL) /**< \brief (TCC0) Waveform Extension Configuration */
|
||||
#define REG_TCC0_DRVCTRL (*(RwReg *)0x42002018UL) /**< \brief (TCC0) Driver Control */
|
||||
#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4200201EUL) /**< \brief (TCC0) Debug Control */
|
||||
#define REG_TCC0_EVCTRL (*(RwReg *)0x42002020UL) /**< \brief (TCC0) Event Control */
|
||||
#define REG_TCC0_INTENCLR (*(RwReg *)0x42002024UL) /**< \brief (TCC0) Interrupt Enable Clear */
|
||||
#define REG_TCC0_INTENSET (*(RwReg *)0x42002028UL) /**< \brief (TCC0) Interrupt Enable Set */
|
||||
#define REG_TCC0_INTFLAG (*(RwReg *)0x4200202CUL) /**< \brief (TCC0) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC0_STATUS (*(RwReg *)0x42002030UL) /**< \brief (TCC0) Status */
|
||||
#define REG_TCC0_COUNT (*(RwReg *)0x42002034UL) /**< \brief (TCC0) Count */
|
||||
#define REG_TCC0_PATT (*(RwReg16*)0x42002038UL) /**< \brief (TCC0) Pattern */
|
||||
#define REG_TCC0_WAVE (*(RwReg *)0x4200203CUL) /**< \brief (TCC0) Waveform Control */
|
||||
#define REG_TCC0_PER (*(RwReg *)0x42002040UL) /**< \brief (TCC0) Period */
|
||||
#define REG_TCC0_CC0 (*(RwReg *)0x42002044UL) /**< \brief (TCC0) Compare and Capture 0 */
|
||||
#define REG_TCC0_CC1 (*(RwReg *)0x42002048UL) /**< \brief (TCC0) Compare and Capture 1 */
|
||||
#define REG_TCC0_CC2 (*(RwReg *)0x4200204CUL) /**< \brief (TCC0) Compare and Capture 2 */
|
||||
#define REG_TCC0_CC3 (*(RwReg *)0x42002050UL) /**< \brief (TCC0) Compare and Capture 3 */
|
||||
#define REG_TCC0_PATTB (*(RwReg16*)0x42002064UL) /**< \brief (TCC0) Pattern Buffer */
|
||||
#define REG_TCC0_WAVEB (*(RwReg *)0x42002068UL) /**< \brief (TCC0) Waveform Control Buffer */
|
||||
#define REG_TCC0_PERB (*(RwReg *)0x4200206CUL) /**< \brief (TCC0) Period Buffer */
|
||||
#define REG_TCC0_CCB0 (*(RwReg *)0x42002070UL) /**< \brief (TCC0) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC0_CCB1 (*(RwReg *)0x42002074UL) /**< \brief (TCC0) Compare and Capture Buffer 1 */
|
||||
#define REG_TCC0_CCB2 (*(RwReg *)0x42002078UL) /**< \brief (TCC0) Compare and Capture Buffer 2 */
|
||||
#define REG_TCC0_CCB3 (*(RwReg *)0x4200207CUL) /**< \brief (TCC0) Compare and Capture Buffer 3 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC0 peripheral ========== */
|
||||
#define TCC0_CC_NUM 4 // Number of Compare/Capture units
|
||||
#define TCC0_DITHERING 1 // Dithering feature implemented
|
||||
#define TCC0_DMAC_ID_MC_0 14
|
||||
#define TCC0_DMAC_ID_MC_1 15
|
||||
#define TCC0_DMAC_ID_MC_2 16
|
||||
#define TCC0_DMAC_ID_MC_3 17
|
||||
#define TCC0_DMAC_ID_MC_LSB 14
|
||||
#define TCC0_DMAC_ID_MC_MSB 17
|
||||
#define TCC0_DMAC_ID_MC_SIZE 4
|
||||
#define TCC0_DMAC_ID_OVF 13 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
|
||||
#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
|
||||
#define TCC0_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC0_OTMX 1 // Output Matrix feature implemented
|
||||
#define TCC0_OW_NUM 8 // Number of Output Waveforms
|
||||
#define TCC0_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC0_SIZE 24
|
||||
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
|
||||
#define TCC0_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC0_INSTANCE_ */
|
||||
|
||||
@@ -1,105 +1,105 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC1_INSTANCE_
|
||||
#define _SAMD21_TCC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC1_CTRLA (0x42002400) /**< \brief (TCC1) Control A */
|
||||
#define REG_TCC1_CTRLBCLR (0x42002404) /**< \brief (TCC1) Control B Clear */
|
||||
#define REG_TCC1_CTRLBSET (0x42002405) /**< \brief (TCC1) Control B Set */
|
||||
#define REG_TCC1_SYNCBUSY (0x42002408) /**< \brief (TCC1) Synchronization Busy */
|
||||
#define REG_TCC1_FCTRLA (0x4200240C) /**< \brief (TCC1) Recoverable Fault A Configuration */
|
||||
#define REG_TCC1_FCTRLB (0x42002410) /**< \brief (TCC1) Recoverable Fault B Configuration */
|
||||
#define REG_TCC1_DRVCTRL (0x42002418) /**< \brief (TCC1) Driver Control */
|
||||
#define REG_TCC1_DBGCTRL (0x4200241E) /**< \brief (TCC1) Debug Control */
|
||||
#define REG_TCC1_EVCTRL (0x42002420) /**< \brief (TCC1) Event Control */
|
||||
#define REG_TCC1_INTENCLR (0x42002424) /**< \brief (TCC1) Interrupt Enable Clear */
|
||||
#define REG_TCC1_INTENSET (0x42002428) /**< \brief (TCC1) Interrupt Enable Set */
|
||||
#define REG_TCC1_INTFLAG (0x4200242C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC1_STATUS (0x42002430) /**< \brief (TCC1) Status */
|
||||
#define REG_TCC1_COUNT (0x42002434) /**< \brief (TCC1) Count */
|
||||
#define REG_TCC1_PATT (0x42002438) /**< \brief (TCC1) Pattern */
|
||||
#define REG_TCC1_WAVE (0x4200243C) /**< \brief (TCC1) Waveform Control */
|
||||
#define REG_TCC1_PER (0x42002440) /**< \brief (TCC1) Period */
|
||||
#define REG_TCC1_CC0 (0x42002444) /**< \brief (TCC1) Compare and Capture 0 */
|
||||
#define REG_TCC1_CC1 (0x42002448) /**< \brief (TCC1) Compare and Capture 1 */
|
||||
#define REG_TCC1_PATTB (0x42002464) /**< \brief (TCC1) Pattern Buffer */
|
||||
#define REG_TCC1_WAVEB (0x42002468) /**< \brief (TCC1) Waveform Control Buffer */
|
||||
#define REG_TCC1_PERB (0x4200246C) /**< \brief (TCC1) Period Buffer */
|
||||
#define REG_TCC1_CCB0 (0x42002470) /**< \brief (TCC1) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC1_CCB1 (0x42002474) /**< \brief (TCC1) Compare and Capture Buffer 1 */
|
||||
#else
|
||||
#define REG_TCC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TCC1) Control A */
|
||||
#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TCC1) Control B Clear */
|
||||
#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TCC1) Control B Set */
|
||||
#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408UL) /**< \brief (TCC1) Synchronization Busy */
|
||||
#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
|
||||
#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
|
||||
#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418UL) /**< \brief (TCC1) Driver Control */
|
||||
#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EUL) /**< \brief (TCC1) Debug Control */
|
||||
#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420UL) /**< \brief (TCC1) Event Control */
|
||||
#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424UL) /**< \brief (TCC1) Interrupt Enable Clear */
|
||||
#define REG_TCC1_INTENSET (*(RwReg *)0x42002428UL) /**< \brief (TCC1) Interrupt Enable Set */
|
||||
#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC1_STATUS (*(RwReg *)0x42002430UL) /**< \brief (TCC1) Status */
|
||||
#define REG_TCC1_COUNT (*(RwReg *)0x42002434UL) /**< \brief (TCC1) Count */
|
||||
#define REG_TCC1_PATT (*(RwReg16*)0x42002438UL) /**< \brief (TCC1) Pattern */
|
||||
#define REG_TCC1_WAVE (*(RwReg *)0x4200243CUL) /**< \brief (TCC1) Waveform Control */
|
||||
#define REG_TCC1_PER (*(RwReg *)0x42002440UL) /**< \brief (TCC1) Period */
|
||||
#define REG_TCC1_CC0 (*(RwReg *)0x42002444UL) /**< \brief (TCC1) Compare and Capture 0 */
|
||||
#define REG_TCC1_CC1 (*(RwReg *)0x42002448UL) /**< \brief (TCC1) Compare and Capture 1 */
|
||||
#define REG_TCC1_PATTB (*(RwReg16*)0x42002464UL) /**< \brief (TCC1) Pattern Buffer */
|
||||
#define REG_TCC1_WAVEB (*(RwReg *)0x42002468UL) /**< \brief (TCC1) Waveform Control Buffer */
|
||||
#define REG_TCC1_PERB (*(RwReg *)0x4200246CUL) /**< \brief (TCC1) Period Buffer */
|
||||
#define REG_TCC1_CCB0 (*(RwReg *)0x42002470UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC1_CCB1 (*(RwReg *)0x42002474UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC1 peripheral ========== */
|
||||
#define TCC1_CC_NUM 2 // Number of Compare/Capture units
|
||||
#define TCC1_DITHERING 1 // Dithering feature implemented
|
||||
#define TCC1_DMAC_ID_MC_0 19
|
||||
#define TCC1_DMAC_ID_MC_1 20
|
||||
#define TCC1_DMAC_ID_MC_LSB 19
|
||||
#define TCC1_DMAC_ID_MC_MSB 20
|
||||
#define TCC1_DMAC_ID_MC_SIZE 2
|
||||
#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC1_EXT 24 // Coding of implemented extended features
|
||||
#define TCC1_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC1_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC1_OW_NUM 4 // Number of Output Waveforms
|
||||
#define TCC1_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC1_SIZE 24
|
||||
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC1_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC1
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC1_INSTANCE_
|
||||
#define _SAMD21_TCC1_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC1_CTRLA (0x42002400) /**< \brief (TCC1) Control A */
|
||||
#define REG_TCC1_CTRLBCLR (0x42002404) /**< \brief (TCC1) Control B Clear */
|
||||
#define REG_TCC1_CTRLBSET (0x42002405) /**< \brief (TCC1) Control B Set */
|
||||
#define REG_TCC1_SYNCBUSY (0x42002408) /**< \brief (TCC1) Synchronization Busy */
|
||||
#define REG_TCC1_FCTRLA (0x4200240C) /**< \brief (TCC1) Recoverable Fault A Configuration */
|
||||
#define REG_TCC1_FCTRLB (0x42002410) /**< \brief (TCC1) Recoverable Fault B Configuration */
|
||||
#define REG_TCC1_DRVCTRL (0x42002418) /**< \brief (TCC1) Driver Control */
|
||||
#define REG_TCC1_DBGCTRL (0x4200241E) /**< \brief (TCC1) Debug Control */
|
||||
#define REG_TCC1_EVCTRL (0x42002420) /**< \brief (TCC1) Event Control */
|
||||
#define REG_TCC1_INTENCLR (0x42002424) /**< \brief (TCC1) Interrupt Enable Clear */
|
||||
#define REG_TCC1_INTENSET (0x42002428) /**< \brief (TCC1) Interrupt Enable Set */
|
||||
#define REG_TCC1_INTFLAG (0x4200242C) /**< \brief (TCC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC1_STATUS (0x42002430) /**< \brief (TCC1) Status */
|
||||
#define REG_TCC1_COUNT (0x42002434) /**< \brief (TCC1) Count */
|
||||
#define REG_TCC1_PATT (0x42002438) /**< \brief (TCC1) Pattern */
|
||||
#define REG_TCC1_WAVE (0x4200243C) /**< \brief (TCC1) Waveform Control */
|
||||
#define REG_TCC1_PER (0x42002440) /**< \brief (TCC1) Period */
|
||||
#define REG_TCC1_CC0 (0x42002444) /**< \brief (TCC1) Compare and Capture 0 */
|
||||
#define REG_TCC1_CC1 (0x42002448) /**< \brief (TCC1) Compare and Capture 1 */
|
||||
#define REG_TCC1_PATTB (0x42002464) /**< \brief (TCC1) Pattern Buffer */
|
||||
#define REG_TCC1_WAVEB (0x42002468) /**< \brief (TCC1) Waveform Control Buffer */
|
||||
#define REG_TCC1_PERB (0x4200246C) /**< \brief (TCC1) Period Buffer */
|
||||
#define REG_TCC1_CCB0 (0x42002470) /**< \brief (TCC1) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC1_CCB1 (0x42002474) /**< \brief (TCC1) Compare and Capture Buffer 1 */
|
||||
#else
|
||||
#define REG_TCC1_CTRLA (*(RwReg *)0x42002400UL) /**< \brief (TCC1) Control A */
|
||||
#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404UL) /**< \brief (TCC1) Control B Clear */
|
||||
#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405UL) /**< \brief (TCC1) Control B Set */
|
||||
#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408UL) /**< \brief (TCC1) Synchronization Busy */
|
||||
#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CUL) /**< \brief (TCC1) Recoverable Fault A Configuration */
|
||||
#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410UL) /**< \brief (TCC1) Recoverable Fault B Configuration */
|
||||
#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418UL) /**< \brief (TCC1) Driver Control */
|
||||
#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EUL) /**< \brief (TCC1) Debug Control */
|
||||
#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420UL) /**< \brief (TCC1) Event Control */
|
||||
#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424UL) /**< \brief (TCC1) Interrupt Enable Clear */
|
||||
#define REG_TCC1_INTENSET (*(RwReg *)0x42002428UL) /**< \brief (TCC1) Interrupt Enable Set */
|
||||
#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CUL) /**< \brief (TCC1) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC1_STATUS (*(RwReg *)0x42002430UL) /**< \brief (TCC1) Status */
|
||||
#define REG_TCC1_COUNT (*(RwReg *)0x42002434UL) /**< \brief (TCC1) Count */
|
||||
#define REG_TCC1_PATT (*(RwReg16*)0x42002438UL) /**< \brief (TCC1) Pattern */
|
||||
#define REG_TCC1_WAVE (*(RwReg *)0x4200243CUL) /**< \brief (TCC1) Waveform Control */
|
||||
#define REG_TCC1_PER (*(RwReg *)0x42002440UL) /**< \brief (TCC1) Period */
|
||||
#define REG_TCC1_CC0 (*(RwReg *)0x42002444UL) /**< \brief (TCC1) Compare and Capture 0 */
|
||||
#define REG_TCC1_CC1 (*(RwReg *)0x42002448UL) /**< \brief (TCC1) Compare and Capture 1 */
|
||||
#define REG_TCC1_PATTB (*(RwReg16*)0x42002464UL) /**< \brief (TCC1) Pattern Buffer */
|
||||
#define REG_TCC1_WAVEB (*(RwReg *)0x42002468UL) /**< \brief (TCC1) Waveform Control Buffer */
|
||||
#define REG_TCC1_PERB (*(RwReg *)0x4200246CUL) /**< \brief (TCC1) Period Buffer */
|
||||
#define REG_TCC1_CCB0 (*(RwReg *)0x42002470UL) /**< \brief (TCC1) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC1_CCB1 (*(RwReg *)0x42002474UL) /**< \brief (TCC1) Compare and Capture Buffer 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC1 peripheral ========== */
|
||||
#define TCC1_CC_NUM 2 // Number of Compare/Capture units
|
||||
#define TCC1_DITHERING 1 // Dithering feature implemented
|
||||
#define TCC1_DMAC_ID_MC_0 19
|
||||
#define TCC1_DMAC_ID_MC_1 20
|
||||
#define TCC1_DMAC_ID_MC_LSB 19
|
||||
#define TCC1_DMAC_ID_MC_MSB 20
|
||||
#define TCC1_DMAC_ID_MC_SIZE 2
|
||||
#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC1_EXT 24 // Coding of implemented extended features
|
||||
#define TCC1_GCLK_ID 26 // Index of Generic Clock
|
||||
#define TCC1_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC1_OW_NUM 4 // Number of Output Waveforms
|
||||
#define TCC1_PG 1 // Pattern Generation feature implemented
|
||||
#define TCC1_SIZE 24
|
||||
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC1_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC1_INSTANCE_ */
|
||||
|
||||
@@ -1,101 +1,101 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC2_INSTANCE_
|
||||
#define _SAMD21_TCC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC2_CTRLA (0x42002800) /**< \brief (TCC2) Control A */
|
||||
#define REG_TCC2_CTRLBCLR (0x42002804) /**< \brief (TCC2) Control B Clear */
|
||||
#define REG_TCC2_CTRLBSET (0x42002805) /**< \brief (TCC2) Control B Set */
|
||||
#define REG_TCC2_SYNCBUSY (0x42002808) /**< \brief (TCC2) Synchronization Busy */
|
||||
#define REG_TCC2_FCTRLA (0x4200280C) /**< \brief (TCC2) Recoverable Fault A Configuration */
|
||||
#define REG_TCC2_FCTRLB (0x42002810) /**< \brief (TCC2) Recoverable Fault B Configuration */
|
||||
#define REG_TCC2_DRVCTRL (0x42002818) /**< \brief (TCC2) Driver Control */
|
||||
#define REG_TCC2_DBGCTRL (0x4200281E) /**< \brief (TCC2) Debug Control */
|
||||
#define REG_TCC2_EVCTRL (0x42002820) /**< \brief (TCC2) Event Control */
|
||||
#define REG_TCC2_INTENCLR (0x42002824) /**< \brief (TCC2) Interrupt Enable Clear */
|
||||
#define REG_TCC2_INTENSET (0x42002828) /**< \brief (TCC2) Interrupt Enable Set */
|
||||
#define REG_TCC2_INTFLAG (0x4200282C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC2_STATUS (0x42002830) /**< \brief (TCC2) Status */
|
||||
#define REG_TCC2_COUNT (0x42002834) /**< \brief (TCC2) Count */
|
||||
#define REG_TCC2_WAVE (0x4200283C) /**< \brief (TCC2) Waveform Control */
|
||||
#define REG_TCC2_PER (0x42002840) /**< \brief (TCC2) Period */
|
||||
#define REG_TCC2_CC0 (0x42002844) /**< \brief (TCC2) Compare and Capture 0 */
|
||||
#define REG_TCC2_CC1 (0x42002848) /**< \brief (TCC2) Compare and Capture 1 */
|
||||
#define REG_TCC2_WAVEB (0x42002868) /**< \brief (TCC2) Waveform Control Buffer */
|
||||
#define REG_TCC2_PERB (0x4200286C) /**< \brief (TCC2) Period Buffer */
|
||||
#define REG_TCC2_CCB0 (0x42002870) /**< \brief (TCC2) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC2_CCB1 (0x42002874) /**< \brief (TCC2) Compare and Capture Buffer 1 */
|
||||
#else
|
||||
#define REG_TCC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TCC2) Control A */
|
||||
#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TCC2) Control B Clear */
|
||||
#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TCC2) Control B Set */
|
||||
#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808UL) /**< \brief (TCC2) Synchronization Busy */
|
||||
#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
|
||||
#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
|
||||
#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818UL) /**< \brief (TCC2) Driver Control */
|
||||
#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EUL) /**< \brief (TCC2) Debug Control */
|
||||
#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820UL) /**< \brief (TCC2) Event Control */
|
||||
#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824UL) /**< \brief (TCC2) Interrupt Enable Clear */
|
||||
#define REG_TCC2_INTENSET (*(RwReg *)0x42002828UL) /**< \brief (TCC2) Interrupt Enable Set */
|
||||
#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC2_STATUS (*(RwReg *)0x42002830UL) /**< \brief (TCC2) Status */
|
||||
#define REG_TCC2_COUNT (*(RwReg *)0x42002834UL) /**< \brief (TCC2) Count */
|
||||
#define REG_TCC2_WAVE (*(RwReg *)0x4200283CUL) /**< \brief (TCC2) Waveform Control */
|
||||
#define REG_TCC2_PER (*(RwReg *)0x42002840UL) /**< \brief (TCC2) Period */
|
||||
#define REG_TCC2_CC0 (*(RwReg *)0x42002844UL) /**< \brief (TCC2) Compare and Capture 0 */
|
||||
#define REG_TCC2_CC1 (*(RwReg *)0x42002848UL) /**< \brief (TCC2) Compare and Capture 1 */
|
||||
#define REG_TCC2_WAVEB (*(RwReg *)0x42002868UL) /**< \brief (TCC2) Waveform Control Buffer */
|
||||
#define REG_TCC2_PERB (*(RwReg *)0x4200286CUL) /**< \brief (TCC2) Period Buffer */
|
||||
#define REG_TCC2_CCB0 (*(RwReg *)0x42002870UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC2_CCB1 (*(RwReg *)0x42002874UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC2 peripheral ========== */
|
||||
#define TCC2_CC_NUM 2 // Number of Compare/Capture units
|
||||
#define TCC2_DITHERING 0 // Dithering feature implemented
|
||||
#define TCC2_DMAC_ID_MC_0 22
|
||||
#define TCC2_DMAC_ID_MC_1 23
|
||||
#define TCC2_DMAC_ID_MC_LSB 22
|
||||
#define TCC2_DMAC_ID_MC_MSB 23
|
||||
#define TCC2_DMAC_ID_MC_SIZE 2
|
||||
#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC2_EXT 0 // Coding of implemented extended features
|
||||
#define TCC2_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TCC2_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC2_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TCC2_PG 0 // Pattern Generation feature implemented
|
||||
#define TCC2_SIZE 16
|
||||
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC2_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TCC2
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_TCC2_INSTANCE_
|
||||
#define _SAMD21_TCC2_INSTANCE_
|
||||
|
||||
/* ========== Register definition for TCC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_TCC2_CTRLA (0x42002800) /**< \brief (TCC2) Control A */
|
||||
#define REG_TCC2_CTRLBCLR (0x42002804) /**< \brief (TCC2) Control B Clear */
|
||||
#define REG_TCC2_CTRLBSET (0x42002805) /**< \brief (TCC2) Control B Set */
|
||||
#define REG_TCC2_SYNCBUSY (0x42002808) /**< \brief (TCC2) Synchronization Busy */
|
||||
#define REG_TCC2_FCTRLA (0x4200280C) /**< \brief (TCC2) Recoverable Fault A Configuration */
|
||||
#define REG_TCC2_FCTRLB (0x42002810) /**< \brief (TCC2) Recoverable Fault B Configuration */
|
||||
#define REG_TCC2_DRVCTRL (0x42002818) /**< \brief (TCC2) Driver Control */
|
||||
#define REG_TCC2_DBGCTRL (0x4200281E) /**< \brief (TCC2) Debug Control */
|
||||
#define REG_TCC2_EVCTRL (0x42002820) /**< \brief (TCC2) Event Control */
|
||||
#define REG_TCC2_INTENCLR (0x42002824) /**< \brief (TCC2) Interrupt Enable Clear */
|
||||
#define REG_TCC2_INTENSET (0x42002828) /**< \brief (TCC2) Interrupt Enable Set */
|
||||
#define REG_TCC2_INTFLAG (0x4200282C) /**< \brief (TCC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC2_STATUS (0x42002830) /**< \brief (TCC2) Status */
|
||||
#define REG_TCC2_COUNT (0x42002834) /**< \brief (TCC2) Count */
|
||||
#define REG_TCC2_WAVE (0x4200283C) /**< \brief (TCC2) Waveform Control */
|
||||
#define REG_TCC2_PER (0x42002840) /**< \brief (TCC2) Period */
|
||||
#define REG_TCC2_CC0 (0x42002844) /**< \brief (TCC2) Compare and Capture 0 */
|
||||
#define REG_TCC2_CC1 (0x42002848) /**< \brief (TCC2) Compare and Capture 1 */
|
||||
#define REG_TCC2_WAVEB (0x42002868) /**< \brief (TCC2) Waveform Control Buffer */
|
||||
#define REG_TCC2_PERB (0x4200286C) /**< \brief (TCC2) Period Buffer */
|
||||
#define REG_TCC2_CCB0 (0x42002870) /**< \brief (TCC2) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC2_CCB1 (0x42002874) /**< \brief (TCC2) Compare and Capture Buffer 1 */
|
||||
#else
|
||||
#define REG_TCC2_CTRLA (*(RwReg *)0x42002800UL) /**< \brief (TCC2) Control A */
|
||||
#define REG_TCC2_CTRLBCLR (*(RwReg8 *)0x42002804UL) /**< \brief (TCC2) Control B Clear */
|
||||
#define REG_TCC2_CTRLBSET (*(RwReg8 *)0x42002805UL) /**< \brief (TCC2) Control B Set */
|
||||
#define REG_TCC2_SYNCBUSY (*(RoReg *)0x42002808UL) /**< \brief (TCC2) Synchronization Busy */
|
||||
#define REG_TCC2_FCTRLA (*(RwReg *)0x4200280CUL) /**< \brief (TCC2) Recoverable Fault A Configuration */
|
||||
#define REG_TCC2_FCTRLB (*(RwReg *)0x42002810UL) /**< \brief (TCC2) Recoverable Fault B Configuration */
|
||||
#define REG_TCC2_DRVCTRL (*(RwReg *)0x42002818UL) /**< \brief (TCC2) Driver Control */
|
||||
#define REG_TCC2_DBGCTRL (*(RwReg8 *)0x4200281EUL) /**< \brief (TCC2) Debug Control */
|
||||
#define REG_TCC2_EVCTRL (*(RwReg *)0x42002820UL) /**< \brief (TCC2) Event Control */
|
||||
#define REG_TCC2_INTENCLR (*(RwReg *)0x42002824UL) /**< \brief (TCC2) Interrupt Enable Clear */
|
||||
#define REG_TCC2_INTENSET (*(RwReg *)0x42002828UL) /**< \brief (TCC2) Interrupt Enable Set */
|
||||
#define REG_TCC2_INTFLAG (*(RwReg *)0x4200282CUL) /**< \brief (TCC2) Interrupt Flag Status and Clear */
|
||||
#define REG_TCC2_STATUS (*(RwReg *)0x42002830UL) /**< \brief (TCC2) Status */
|
||||
#define REG_TCC2_COUNT (*(RwReg *)0x42002834UL) /**< \brief (TCC2) Count */
|
||||
#define REG_TCC2_WAVE (*(RwReg *)0x4200283CUL) /**< \brief (TCC2) Waveform Control */
|
||||
#define REG_TCC2_PER (*(RwReg *)0x42002840UL) /**< \brief (TCC2) Period */
|
||||
#define REG_TCC2_CC0 (*(RwReg *)0x42002844UL) /**< \brief (TCC2) Compare and Capture 0 */
|
||||
#define REG_TCC2_CC1 (*(RwReg *)0x42002848UL) /**< \brief (TCC2) Compare and Capture 1 */
|
||||
#define REG_TCC2_WAVEB (*(RwReg *)0x42002868UL) /**< \brief (TCC2) Waveform Control Buffer */
|
||||
#define REG_TCC2_PERB (*(RwReg *)0x4200286CUL) /**< \brief (TCC2) Period Buffer */
|
||||
#define REG_TCC2_CCB0 (*(RwReg *)0x42002870UL) /**< \brief (TCC2) Compare and Capture Buffer 0 */
|
||||
#define REG_TCC2_CCB1 (*(RwReg *)0x42002874UL) /**< \brief (TCC2) Compare and Capture Buffer 1 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for TCC2 peripheral ========== */
|
||||
#define TCC2_CC_NUM 2 // Number of Compare/Capture units
|
||||
#define TCC2_DITHERING 0 // Dithering feature implemented
|
||||
#define TCC2_DMAC_ID_MC_0 22
|
||||
#define TCC2_DMAC_ID_MC_1 23
|
||||
#define TCC2_DMAC_ID_MC_LSB 22
|
||||
#define TCC2_DMAC_ID_MC_MSB 23
|
||||
#define TCC2_DMAC_ID_MC_SIZE 2
|
||||
#define TCC2_DMAC_ID_OVF 21 // DMA overflow/underflow/retrigger trigger
|
||||
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
|
||||
#define TCC2_EXT 0 // Coding of implemented extended features
|
||||
#define TCC2_GCLK_ID 27 // Index of Generic Clock
|
||||
#define TCC2_OTMX 0 // Output Matrix feature implemented
|
||||
#define TCC2_OW_NUM 2 // Number of Output Waveforms
|
||||
#define TCC2_PG 0 // Pattern Generation feature implemented
|
||||
#define TCC2_SIZE 16
|
||||
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
|
||||
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave
|
||||
|
||||
#endif /* _SAMD21_TCC2_INSTANCE_ */
|
||||
|
||||
@@ -1,330 +1,330 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for USB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_USB_INSTANCE_
|
||||
#define _SAMD21_USB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USB peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_USB_CTRLA (0x41005000) /**< \brief (USB) Control A */
|
||||
#define REG_USB_SYNCBUSY (0x41005002) /**< \brief (USB) Synchronization Busy */
|
||||
#define REG_USB_QOSCTRL (0x41005003) /**< \brief (USB) USB Quality Of Service */
|
||||
#define REG_USB_FSMSTATUS (0x4100500D) /**< \brief (USB) Finite State Machine Status */
|
||||
#define REG_USB_DESCADD (0x41005024) /**< \brief (USB) Descriptor Address */
|
||||
#define REG_USB_PADCAL (0x41005028) /**< \brief (USB) USB PAD Calibration */
|
||||
#define REG_USB_DEVICE_CTRLB (0x41005008) /**< \brief (USB) DEVICE Control B */
|
||||
#define REG_USB_DEVICE_DADD (0x4100500A) /**< \brief (USB) DEVICE Device Address */
|
||||
#define REG_USB_DEVICE_STATUS (0x4100500C) /**< \brief (USB) DEVICE Status */
|
||||
#define REG_USB_DEVICE_FNUM (0x41005010) /**< \brief (USB) DEVICE Device Frame Number */
|
||||
#define REG_USB_DEVICE_INTENCLR (0x41005014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
|
||||
#define REG_USB_DEVICE_INTENSET (0x41005018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
|
||||
#define REG_USB_DEVICE_INTFLAG (0x4100501C) /**< \brief (USB) DEVICE Device Interrupt Flag */
|
||||
#define REG_USB_DEVICE_EPINTSMRY (0x41005020) /**< \brief (USB) DEVICE End Point Interrupt Summary */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
|
||||
#define REG_USB_HOST_CTRLB (0x41005008) /**< \brief (USB) HOST Control B */
|
||||
#define REG_USB_HOST_HSOFC (0x4100500A) /**< \brief (USB) HOST Host Start Of Frame Control */
|
||||
#define REG_USB_HOST_STATUS (0x4100500C) /**< \brief (USB) HOST Status */
|
||||
#define REG_USB_HOST_FNUM (0x41005010) /**< \brief (USB) HOST Host Frame Number */
|
||||
#define REG_USB_HOST_FLENHIGH (0x41005012) /**< \brief (USB) HOST Host Frame Length */
|
||||
#define REG_USB_HOST_INTENCLR (0x41005014) /**< \brief (USB) HOST Host Interrupt Enable Clear */
|
||||
#define REG_USB_HOST_INTENSET (0x41005018) /**< \brief (USB) HOST Host Interrupt Enable Set */
|
||||
#define REG_USB_HOST_INTFLAG (0x4100501C) /**< \brief (USB) HOST Host Interrupt Flag */
|
||||
#define REG_USB_HOST_PINTSMRY (0x41005020) /**< \brief (USB) HOST Pipe Interrupt Summary */
|
||||
#define REG_USB_HOST_PIPE_PCFG0 (0x41005100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PCFG1 (0x41005120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PCFG2 (0x41005140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PCFG3 (0x41005160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PCFG4 (0x41005180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
|
||||
#else
|
||||
#define REG_USB_CTRLA (*(RwReg8 *)0x41005000UL) /**< \brief (USB) Control A */
|
||||
#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002UL) /**< \brief (USB) Synchronization Busy */
|
||||
#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003UL) /**< \brief (USB) USB Quality Of Service */
|
||||
#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DUL) /**< \brief (USB) Finite State Machine Status */
|
||||
#define REG_USB_DESCADD (*(RwReg *)0x41005024UL) /**< \brief (USB) Descriptor Address */
|
||||
#define REG_USB_PADCAL (*(RwReg16*)0x41005028UL) /**< \brief (USB) USB PAD Calibration */
|
||||
#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008UL) /**< \brief (USB) DEVICE Control B */
|
||||
#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) DEVICE Device Address */
|
||||
#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CUL) /**< \brief (USB) DEVICE Status */
|
||||
#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010UL) /**< \brief (USB) DEVICE Device Frame Number */
|
||||
#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
|
||||
#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
|
||||
#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */
|
||||
#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
|
||||
#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008UL) /**< \brief (USB) HOST Control B */
|
||||
#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) HOST Host Start Of Frame Control */
|
||||
#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CUL) /**< \brief (USB) HOST Status */
|
||||
#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010UL) /**< \brief (USB) HOST Host Frame Number */
|
||||
#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012UL) /**< \brief (USB) HOST Host Frame Length */
|
||||
#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */
|
||||
#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */
|
||||
#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CUL) /**< \brief (USB) HOST Host Interrupt Flag */
|
||||
#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */
|
||||
#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for USB peripheral ========== */
|
||||
#define USB_EPT_NBR 8 // Number of USB end points (obsolete)
|
||||
#define USB_EPT_NUM 8 // Number of USB end points
|
||||
#define USB_GCLK_ID 6 // Index of Generic Clock
|
||||
#define USB_PIPE_NUM 8 // Number of USB pipes
|
||||
|
||||
#endif /* _SAMD21_USB_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for USB
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_USB_INSTANCE_
|
||||
#define _SAMD21_USB_INSTANCE_
|
||||
|
||||
/* ========== Register definition for USB peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_USB_CTRLA (0x41005000) /**< \brief (USB) Control A */
|
||||
#define REG_USB_SYNCBUSY (0x41005002) /**< \brief (USB) Synchronization Busy */
|
||||
#define REG_USB_QOSCTRL (0x41005003) /**< \brief (USB) USB Quality Of Service */
|
||||
#define REG_USB_FSMSTATUS (0x4100500D) /**< \brief (USB) Finite State Machine Status */
|
||||
#define REG_USB_DESCADD (0x41005024) /**< \brief (USB) Descriptor Address */
|
||||
#define REG_USB_PADCAL (0x41005028) /**< \brief (USB) USB PAD Calibration */
|
||||
#define REG_USB_DEVICE_CTRLB (0x41005008) /**< \brief (USB) DEVICE Control B */
|
||||
#define REG_USB_DEVICE_DADD (0x4100500A) /**< \brief (USB) DEVICE Device Address */
|
||||
#define REG_USB_DEVICE_STATUS (0x4100500C) /**< \brief (USB) DEVICE Status */
|
||||
#define REG_USB_DEVICE_FNUM (0x41005010) /**< \brief (USB) DEVICE Device Frame Number */
|
||||
#define REG_USB_DEVICE_INTENCLR (0x41005014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
|
||||
#define REG_USB_DEVICE_INTENSET (0x41005018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
|
||||
#define REG_USB_DEVICE_INTFLAG (0x4100501C) /**< \brief (USB) DEVICE Device Interrupt Flag */
|
||||
#define REG_USB_DEVICE_EPINTSMRY (0x41005020) /**< \brief (USB) DEVICE End Point Interrupt Summary */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41005100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41005104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41005105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41005106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41005107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41005108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41005109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41005120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41005124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41005125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41005126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41005127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41005128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41005129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41005140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41005144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41005145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41005146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41005147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41005148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41005149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41005160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41005164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41005165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41005166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41005167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41005168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41005169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41005180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41005184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41005185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41005186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41005187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41005188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41005189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410051A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410051A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410051A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410051A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410051A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410051A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410051A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410051C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410051C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410051C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410051C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410051C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410051C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410051C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410051E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410051E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410051E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410051E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410051E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410051E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410051E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
|
||||
#define REG_USB_HOST_CTRLB (0x41005008) /**< \brief (USB) HOST Control B */
|
||||
#define REG_USB_HOST_HSOFC (0x4100500A) /**< \brief (USB) HOST Host Start Of Frame Control */
|
||||
#define REG_USB_HOST_STATUS (0x4100500C) /**< \brief (USB) HOST Status */
|
||||
#define REG_USB_HOST_FNUM (0x41005010) /**< \brief (USB) HOST Host Frame Number */
|
||||
#define REG_USB_HOST_FLENHIGH (0x41005012) /**< \brief (USB) HOST Host Frame Length */
|
||||
#define REG_USB_HOST_INTENCLR (0x41005014) /**< \brief (USB) HOST Host Interrupt Enable Clear */
|
||||
#define REG_USB_HOST_INTENSET (0x41005018) /**< \brief (USB) HOST Host Interrupt Enable Set */
|
||||
#define REG_USB_HOST_INTFLAG (0x4100501C) /**< \brief (USB) HOST Host Interrupt Flag */
|
||||
#define REG_USB_HOST_PINTSMRY (0x41005020) /**< \brief (USB) HOST Pipe Interrupt Summary */
|
||||
#define REG_USB_HOST_PIPE_PCFG0 (0x41005100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41005103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41005104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41005105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS0 (0x41005106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41005107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41005108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET0 (0x41005109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PCFG1 (0x41005120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41005123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41005124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41005125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS1 (0x41005126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41005127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41005128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET1 (0x41005129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PCFG2 (0x41005140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41005143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41005144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41005145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS2 (0x41005146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41005147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41005148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET2 (0x41005149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PCFG3 (0x41005160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41005163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41005164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41005165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS3 (0x41005166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41005167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41005168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET3 (0x41005169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PCFG4 (0x41005180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41005183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41005184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41005185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS4 (0x41005186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41005187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41005188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET4 (0x41005189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PCFG5 (0x410051A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410051A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410051A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410051A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS5 (0x410051A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410051A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410051A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET5 (0x410051A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PCFG6 (0x410051C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410051C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410051C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410051C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS6 (0x410051C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410051C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410051C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET6 (0x410051C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PCFG7 (0x410051E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410051E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410051E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410051E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS7 (0x410051E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410051E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410051E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET7 (0x410051E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
|
||||
#else
|
||||
#define REG_USB_CTRLA (*(RwReg8 *)0x41005000UL) /**< \brief (USB) Control A */
|
||||
#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41005002UL) /**< \brief (USB) Synchronization Busy */
|
||||
#define REG_USB_QOSCTRL (*(RwReg8 *)0x41005003UL) /**< \brief (USB) USB Quality Of Service */
|
||||
#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100500DUL) /**< \brief (USB) Finite State Machine Status */
|
||||
#define REG_USB_DESCADD (*(RwReg *)0x41005024UL) /**< \brief (USB) Descriptor Address */
|
||||
#define REG_USB_PADCAL (*(RwReg16*)0x41005028UL) /**< \brief (USB) USB PAD Calibration */
|
||||
#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41005008UL) /**< \brief (USB) DEVICE Control B */
|
||||
#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) DEVICE Device Address */
|
||||
#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100500CUL) /**< \brief (USB) DEVICE Status */
|
||||
#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41005010UL) /**< \brief (USB) DEVICE Device Frame Number */
|
||||
#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41005014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */
|
||||
#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41005018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */
|
||||
#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100501CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */
|
||||
#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41005020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */
|
||||
#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */
|
||||
#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41005008UL) /**< \brief (USB) HOST Control B */
|
||||
#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100500AUL) /**< \brief (USB) HOST Host Start Of Frame Control */
|
||||
#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100500CUL) /**< \brief (USB) HOST Status */
|
||||
#define REG_USB_HOST_FNUM (*(RwReg16*)0x41005010UL) /**< \brief (USB) HOST Host Frame Number */
|
||||
#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41005012UL) /**< \brief (USB) HOST Host Frame Length */
|
||||
#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41005014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */
|
||||
#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41005018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */
|
||||
#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100501CUL) /**< \brief (USB) HOST Host Interrupt Flag */
|
||||
#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41005020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */
|
||||
#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41005100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41005103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41005104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41005105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41005106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41005107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41005108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41005109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */
|
||||
#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41005120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41005123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41005124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41005125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41005126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41005127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41005128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41005129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */
|
||||
#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41005140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41005143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41005144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41005145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41005146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41005147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41005148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41005149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */
|
||||
#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41005160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41005163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41005164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41005165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41005166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41005167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41005168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41005169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */
|
||||
#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41005180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41005183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41005184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41005185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41005186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41005187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41005188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41005189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */
|
||||
#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410051A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410051A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410051A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410051A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410051A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410051A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410051A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410051A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */
|
||||
#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410051C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410051C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410051C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410051C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410051C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410051C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410051C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410051C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */
|
||||
#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410051E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */
|
||||
#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410051E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410051E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410051E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */
|
||||
#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410051E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410051E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410051E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */
|
||||
#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410051E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for USB peripheral ========== */
|
||||
#define USB_EPT_NBR 8 // Number of USB end points (obsolete)
|
||||
#define USB_EPT_NUM 8 // Number of USB end points
|
||||
#define USB_GCLK_ID 6 // Index of Generic Clock
|
||||
#define USB_PIPE_NUM 8 // Number of USB pipes
|
||||
|
||||
#endif /* _SAMD21_USB_INSTANCE_ */
|
||||
|
||||
@@ -1,57 +1,57 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for WDT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_INSTANCE_
|
||||
#define _SAMD21_WDT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_WDT_CTRL (0x40001000) /**< \brief (WDT) Control */
|
||||
#define REG_WDT_CONFIG (0x40001001) /**< \brief (WDT) Configuration */
|
||||
#define REG_WDT_EWCTRL (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */
|
||||
#define REG_WDT_INTENCLR (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */
|
||||
#define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */
|
||||
#define REG_WDT_INTFLAG (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */
|
||||
#define REG_WDT_STATUS (0x40001007) /**< \brief (WDT) Status */
|
||||
#define REG_WDT_CLEAR (0x40001008) /**< \brief (WDT) Clear */
|
||||
#else
|
||||
#define REG_WDT_CTRL (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */
|
||||
#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */
|
||||
#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */
|
||||
#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */
|
||||
#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */
|
||||
#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
|
||||
#define REG_WDT_STATUS (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */
|
||||
#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for WDT peripheral ========== */
|
||||
#define WDT_GCLK_ID 3 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_WDT_INSTANCE_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for WDT
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_WDT_INSTANCE_
|
||||
#define _SAMD21_WDT_INSTANCE_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
#define REG_WDT_CTRL (0x40001000) /**< \brief (WDT) Control */
|
||||
#define REG_WDT_CONFIG (0x40001001) /**< \brief (WDT) Configuration */
|
||||
#define REG_WDT_EWCTRL (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */
|
||||
#define REG_WDT_INTENCLR (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */
|
||||
#define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */
|
||||
#define REG_WDT_INTFLAG (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */
|
||||
#define REG_WDT_STATUS (0x40001007) /**< \brief (WDT) Status */
|
||||
#define REG_WDT_CLEAR (0x40001008) /**< \brief (WDT) Clear */
|
||||
#else
|
||||
#define REG_WDT_CTRL (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */
|
||||
#define REG_WDT_CONFIG (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */
|
||||
#define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */
|
||||
#define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */
|
||||
#define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */
|
||||
#define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */
|
||||
#define REG_WDT_STATUS (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */
|
||||
#define REG_WDT_CLEAR (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */
|
||||
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance parameters for WDT peripheral ========== */
|
||||
#define WDT_GCLK_ID 3 // Index of Generic Clock
|
||||
|
||||
#endif /* _SAMD21_WDT_INSTANCE_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,66 +1,66 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Top level header file
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAM_
|
||||
#define _SAM_
|
||||
|
||||
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
|
||||
#include "samd21e15a.h"
|
||||
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
|
||||
#include "samd21e16a.h"
|
||||
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
|
||||
#include "samd21e17a.h"
|
||||
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
|
||||
#include "samd21e18a.h"
|
||||
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
|
||||
#include "samd21g15a.h"
|
||||
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
|
||||
#include "samd21g16a.h"
|
||||
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
|
||||
#include "samd21g17a.h"
|
||||
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
|
||||
#include "samd21g17au.h"
|
||||
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
|
||||
#include "samd21g18a.h"
|
||||
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
|
||||
#include "samd21g18au.h"
|
||||
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
|
||||
#include "samd21j15a.h"
|
||||
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
|
||||
#include "samd21j16a.h"
|
||||
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
|
||||
#include "samd21j17a.h"
|
||||
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
|
||||
#include "samd21j18a.h"
|
||||
#else
|
||||
#error Library does not support the specified device
|
||||
#endif
|
||||
|
||||
#endif /* _SAM_ */
|
||||
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Top level header file
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAM_
|
||||
#define _SAM_
|
||||
|
||||
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
|
||||
#include "samd21e15a.h"
|
||||
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
|
||||
#include "samd21e16a.h"
|
||||
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
|
||||
#include "samd21e17a.h"
|
||||
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
|
||||
#include "samd21e18a.h"
|
||||
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
|
||||
#include "samd21g15a.h"
|
||||
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
|
||||
#include "samd21g16a.h"
|
||||
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
|
||||
#include "samd21g17a.h"
|
||||
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
|
||||
#include "samd21g17au.h"
|
||||
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
|
||||
#include "samd21g18a.h"
|
||||
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
|
||||
#include "samd21g18au.h"
|
||||
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
|
||||
#include "samd21j15a.h"
|
||||
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
|
||||
#include "samd21j16a.h"
|
||||
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
|
||||
#include "samd21j17a.h"
|
||||
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
|
||||
#include "samd21j18a.h"
|
||||
#else
|
||||
#error Library does not support the specified device
|
||||
#endif
|
||||
|
||||
#endif /* _SAM_ */
|
||||
|
||||
|
||||
@@ -1,70 +1,70 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Top header file for SAMD21
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_
|
||||
#define _SAMD21_
|
||||
|
||||
/**
|
||||
* \defgroup SAMD21_definitions SAMD21 Device Definitions
|
||||
* \brief SAMD21 CMSIS Definitions.
|
||||
*/
|
||||
|
||||
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
|
||||
#include "samd21e15a.h"
|
||||
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
|
||||
#include "samd21e16a.h"
|
||||
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
|
||||
#include "samd21e17a.h"
|
||||
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
|
||||
#include "samd21e18a.h"
|
||||
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
|
||||
#include "samd21g15a.h"
|
||||
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
|
||||
#include "samd21g16a.h"
|
||||
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
|
||||
#include "samd21g17a.h"
|
||||
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
|
||||
#include "samd21g17au.h"
|
||||
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
|
||||
#include "samd21g18a.h"
|
||||
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
|
||||
#include "samd21g18au.h"
|
||||
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
|
||||
#include "samd21j15a.h"
|
||||
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
|
||||
#include "samd21j16a.h"
|
||||
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
|
||||
#include "samd21j17a.h"
|
||||
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
|
||||
#include "samd21j18a.h"
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _SAMD21_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Top header file for SAMD21
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD21_
|
||||
#define _SAMD21_
|
||||
|
||||
/**
|
||||
* \defgroup SAMD21_definitions SAMD21 Device Definitions
|
||||
* \brief SAMD21 CMSIS Definitions.
|
||||
*/
|
||||
|
||||
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
|
||||
#include "samd21e15a.h"
|
||||
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
|
||||
#include "samd21e16a.h"
|
||||
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
|
||||
#include "samd21e17a.h"
|
||||
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
|
||||
#include "samd21e18a.h"
|
||||
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
|
||||
#include "samd21g15a.h"
|
||||
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
|
||||
#include "samd21g16a.h"
|
||||
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
|
||||
#include "samd21g17a.h"
|
||||
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
|
||||
#include "samd21g17au.h"
|
||||
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
|
||||
#include "samd21g18a.h"
|
||||
#elif defined(__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
|
||||
#include "samd21g18au.h"
|
||||
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
|
||||
#include "samd21j15a.h"
|
||||
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
|
||||
#include "samd21j16a.h"
|
||||
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
|
||||
#include "samd21j17a.h"
|
||||
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
|
||||
#include "samd21j18a.h"
|
||||
#else
|
||||
#error Library does not support the specified device.
|
||||
#endif
|
||||
|
||||
#endif /* _SAMD21_ */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,48 +1,48 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_SAMD21_H_INCLUDED_
|
||||
#define _SYSTEM_SAMD21_H_INCLUDED_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
void SystemInit(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_SAMD21_H_INCLUDED */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SYSTEM_SAMD21_H_INCLUDED_
|
||||
#define _SYSTEM_SAMD21_H_INCLUDED_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
void SystemInit(void);
|
||||
void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_SAMD21_H_INCLUDED */
|
||||
|
||||
@@ -1,64 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "samd51.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Low-level initialization functions called upon chip startup.
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#include "samd51.h"
|
||||
|
||||
/**
|
||||
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
|
||||
* the source for the main clock at chip startup.
|
||||
*/
|
||||
#define __SYSTEM_CLOCK (48000000)
|
||||
|
||||
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
|
||||
|
||||
/**
|
||||
* Initialize the system
|
||||
*
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the System and update the SystemCoreClock variable.
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
// Keep the default device state after reset
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* Update SystemCoreClock variable
|
||||
*
|
||||
* @brief Updates the SystemCoreClock with current core Clock
|
||||
* retrieved from cpu registers.
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
// Not implemented
|
||||
SystemCoreClock = __SYSTEM_CLOCK;
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -1,64 +1,64 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 1
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version.
|
||||
//
|
||||
#define COMPONENT_VERSION 10001
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 96
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.1"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2018-09-21 03:51:18"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component version header file
|
||||
*
|
||||
* Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _COMPONENT_VERSION_H_INCLUDED
|
||||
#define _COMPONENT_VERSION_H_INCLUDED
|
||||
|
||||
#define COMPONENT_VERSION_MAJOR 1
|
||||
#define COMPONENT_VERSION_MINOR 1
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION define is composed of the major and the minor version number.
|
||||
//
|
||||
// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros.
|
||||
// The rest of the COMPONENT_VERSION is the major version.
|
||||
//
|
||||
#define COMPONENT_VERSION 10001
|
||||
|
||||
//
|
||||
// The build number does not refer to the component, but to the build number
|
||||
// of the device pack that provides the component.
|
||||
//
|
||||
#define BUILD_NUMBER 96
|
||||
|
||||
//
|
||||
// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding.
|
||||
//
|
||||
#define COMPONENT_VERSION_STRING "1.1"
|
||||
|
||||
//
|
||||
// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated.
|
||||
//
|
||||
// The COMPONENT_DATE_STRING is written out using the following strftime pattern.
|
||||
//
|
||||
// "%Y-%m-%d %H:%M:%S"
|
||||
//
|
||||
//
|
||||
#define COMPONENT_DATE_STRING "2018-09-21 03:51:18"
|
||||
|
||||
#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,375 +1,375 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for AES
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_AES_COMPONENT_
|
||||
#define _SAMD51_AES_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AES */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_AES Advanced Encryption Standard */
|
||||
/*@{*/
|
||||
|
||||
#define AES_U2238
|
||||
#define REV_AES 0x220
|
||||
|
||||
/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
|
||||
uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
|
||||
uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
|
||||
uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
|
||||
uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
|
||||
uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
|
||||
uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
|
||||
uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
|
||||
uint32_t :1; /*!< bit: 15 Reserved */
|
||||
uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
|
||||
#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
|
||||
|
||||
#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
|
||||
#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
|
||||
#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
|
||||
#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
|
||||
#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
|
||||
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
|
||||
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
|
||||
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
|
||||
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
|
||||
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
|
||||
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
|
||||
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
|
||||
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
|
||||
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
|
||||
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
|
||||
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
|
||||
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
|
||||
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
|
||||
#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
|
||||
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
|
||||
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
|
||||
#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
|
||||
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
|
||||
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
|
||||
#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
|
||||
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
|
||||
#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
|
||||
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
|
||||
#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
|
||||
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
|
||||
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
|
||||
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
|
||||
#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
|
||||
|
||||
/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
|
||||
uint8_t NEWMSG:1; /*!< bit: 1 New message */
|
||||
uint8_t EOM:1; /*!< bit: 2 End of message */
|
||||
uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
|
||||
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
|
||||
|
||||
#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
|
||||
#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
|
||||
#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
|
||||
#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
|
||||
#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
|
||||
#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
|
||||
#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
|
||||
#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
|
||||
#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
|
||||
|
||||
/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
|
||||
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
|
||||
#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
|
||||
#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
|
||||
#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
|
||||
#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
|
||||
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
|
||||
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
|
||||
#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
|
||||
#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
|
||||
#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
|
||||
#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
|
||||
|
||||
/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
|
||||
__I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
|
||||
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
|
||||
|
||||
#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
|
||||
#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
|
||||
#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
|
||||
#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
|
||||
#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_DATABUFPTR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
|
||||
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
|
||||
|
||||
#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
|
||||
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
|
||||
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
|
||||
#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
|
||||
|
||||
/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_DBGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
|
||||
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
|
||||
|
||||
#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
|
||||
#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
|
||||
#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
|
||||
|
||||
/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_KEYWORD_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
|
||||
#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
|
||||
#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
|
||||
|
||||
/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_INDATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
|
||||
#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
|
||||
#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
|
||||
|
||||
/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_INTVECTV_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
|
||||
#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
|
||||
#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
|
||||
|
||||
/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_HASHKEY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
|
||||
#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
|
||||
#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
|
||||
|
||||
/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_GHASH_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
|
||||
#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
|
||||
#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
|
||||
|
||||
/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_CIPLEN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
|
||||
#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
|
||||
#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
|
||||
|
||||
/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_RANDSEED_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
|
||||
#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
|
||||
#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
|
||||
|
||||
/** \brief AES hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
|
||||
__IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
|
||||
__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
|
||||
__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
|
||||
__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
|
||||
__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
|
||||
__IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
|
||||
RoReg8 Reserved1[0x2];
|
||||
__O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
|
||||
RoReg8 Reserved2[0xC];
|
||||
__IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
|
||||
__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
|
||||
RoReg8 Reserved3[0x10];
|
||||
__IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
|
||||
__IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
|
||||
RoReg8 Reserved4[0x4];
|
||||
__IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
|
||||
__IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
|
||||
} Aes;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_AES_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for AES
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_AES_COMPONENT_
|
||||
#define _SAMD51_AES_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR AES */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_AES Advanced Encryption Standard */
|
||||
/*@{*/
|
||||
|
||||
#define AES_U2238
|
||||
#define REV_AES 0x220
|
||||
|
||||
/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */
|
||||
uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */
|
||||
uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */
|
||||
uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */
|
||||
uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */
|
||||
uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */
|
||||
uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */
|
||||
uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */
|
||||
uint32_t :1; /*!< bit: 15 Reserved */
|
||||
uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */
|
||||
uint32_t :12; /*!< bit: 20..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_CTRLA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */
|
||||
#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */
|
||||
|
||||
#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */
|
||||
#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos)
|
||||
#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */
|
||||
#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos)
|
||||
#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */
|
||||
#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos))
|
||||
#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */
|
||||
#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */
|
||||
#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */
|
||||
#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */
|
||||
#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */
|
||||
#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */
|
||||
#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */
|
||||
#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos)
|
||||
#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */
|
||||
#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos))
|
||||
#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */
|
||||
#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */
|
||||
#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos))
|
||||
#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */
|
||||
#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos)
|
||||
#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */
|
||||
#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */
|
||||
#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */
|
||||
#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos)
|
||||
#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */
|
||||
#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */
|
||||
#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */
|
||||
#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos)
|
||||
#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */
|
||||
#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */
|
||||
#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos)
|
||||
#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */
|
||||
#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */
|
||||
#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos)
|
||||
#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */
|
||||
#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */
|
||||
#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */
|
||||
#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos)
|
||||
#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */
|
||||
#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos)
|
||||
#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos))
|
||||
#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */
|
||||
|
||||
/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */
|
||||
uint8_t NEWMSG:1; /*!< bit: 1 New message */
|
||||
uint8_t EOM:1; /*!< bit: 2 End of message */
|
||||
uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_CTRLB_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */
|
||||
#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */
|
||||
|
||||
#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */
|
||||
#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos)
|
||||
#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */
|
||||
#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos)
|
||||
#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */
|
||||
#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos)
|
||||
#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */
|
||||
#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos)
|
||||
#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */
|
||||
|
||||
/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
|
||||
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTENCLR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */
|
||||
#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */
|
||||
|
||||
#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */
|
||||
#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos)
|
||||
#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */
|
||||
#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos)
|
||||
#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */
|
||||
|
||||
/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */
|
||||
uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTENSET_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */
|
||||
#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */
|
||||
|
||||
#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */
|
||||
#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos)
|
||||
#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */
|
||||
#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos)
|
||||
#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */
|
||||
|
||||
/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union { // __I to avoid read-modify-write on write-to-clear register
|
||||
struct {
|
||||
__I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */
|
||||
__I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */
|
||||
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_INTFLAG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */
|
||||
#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */
|
||||
|
||||
#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */
|
||||
#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos)
|
||||
#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */
|
||||
#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos)
|
||||
#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */
|
||||
|
||||
/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */
|
||||
uint8_t :6; /*!< bit: 2.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_DATABUFPTR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */
|
||||
#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */
|
||||
|
||||
#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */
|
||||
#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos)
|
||||
#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos))
|
||||
#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */
|
||||
|
||||
/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
|
||||
uint8_t :7; /*!< bit: 1.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} AES_DBGCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */
|
||||
#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */
|
||||
|
||||
#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */
|
||||
#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos)
|
||||
#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */
|
||||
|
||||
/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_KEYWORD_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */
|
||||
#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */
|
||||
#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */
|
||||
|
||||
/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_INDATA_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */
|
||||
#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */
|
||||
#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */
|
||||
|
||||
/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_INTVECTV_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */
|
||||
#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */
|
||||
#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */
|
||||
|
||||
/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_HASHKEY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */
|
||||
#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */
|
||||
#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */
|
||||
|
||||
/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_GHASH_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */
|
||||
#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */
|
||||
#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */
|
||||
|
||||
/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_CIPLEN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */
|
||||
#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */
|
||||
#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */
|
||||
|
||||
/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} AES_RANDSEED_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */
|
||||
#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */
|
||||
#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */
|
||||
|
||||
/** \brief AES hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */
|
||||
__IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */
|
||||
__IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */
|
||||
__IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */
|
||||
__IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */
|
||||
__IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */
|
||||
__IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */
|
||||
RoReg8 Reserved1[0x2];
|
||||
__O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */
|
||||
RoReg8 Reserved2[0xC];
|
||||
__IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */
|
||||
__O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */
|
||||
RoReg8 Reserved3[0x10];
|
||||
__IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */
|
||||
__IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */
|
||||
RoReg8 Reserved4[0x4];
|
||||
__IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */
|
||||
__IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */
|
||||
} Aes;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_AES_COMPONENT_ */
|
||||
|
||||
@@ -1,228 +1,228 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for CCL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CCL_COMPONENT_
|
||||
#define _SAMD51_CCL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR CCL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_CCL Configurable Custom Logic */
|
||||
/*@{*/
|
||||
|
||||
#define CCL_U2225
|
||||
#define REV_CCL 0x110
|
||||
|
||||
/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} CCL_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
|
||||
#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
|
||||
|
||||
#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
|
||||
#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
|
||||
#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
|
||||
#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
|
||||
#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
|
||||
#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
|
||||
#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
|
||||
|
||||
/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} CCL_SEQCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
|
||||
#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
|
||||
|
||||
#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
|
||||
#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
|
||||
#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
|
||||
#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
|
||||
#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
|
||||
#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
|
||||
#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
|
||||
#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
|
||||
|
||||
/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
|
||||
uint32_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
|
||||
uint32_t :1; /*!< bit: 6 Reserved */
|
||||
uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
|
||||
uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
|
||||
uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
|
||||
uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
|
||||
uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
|
||||
uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
|
||||
uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CCL_LUTCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
|
||||
#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
|
||||
|
||||
#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
|
||||
#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
|
||||
#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
|
||||
#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
|
||||
#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
|
||||
#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
|
||||
#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
|
||||
#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
|
||||
#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
|
||||
#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
|
||||
#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
|
||||
#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
|
||||
#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
|
||||
#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
|
||||
#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
|
||||
#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
|
||||
#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
|
||||
#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
|
||||
#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
|
||||
#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
|
||||
#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
|
||||
#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
|
||||
#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
|
||||
#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
|
||||
#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
|
||||
#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
|
||||
#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
|
||||
#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
|
||||
#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
|
||||
#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
|
||||
#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
|
||||
#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
|
||||
#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
|
||||
#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
|
||||
#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
|
||||
#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
|
||||
#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
|
||||
#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
|
||||
#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
|
||||
#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
|
||||
#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
|
||||
|
||||
/** \brief CCL hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
RoReg8 Reserved1[0x3];
|
||||
__IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
|
||||
} Ccl;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_CCL_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for CCL
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CCL_COMPONENT_
|
||||
#define _SAMD51_CCL_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR CCL */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_CCL Configurable Custom Logic */
|
||||
/*@{*/
|
||||
|
||||
#define CCL_U2225
|
||||
#define REV_CCL 0x110
|
||||
|
||||
/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
|
||||
uint8_t ENABLE:1; /*!< bit: 1 Enable */
|
||||
uint8_t :4; /*!< bit: 2.. 5 Reserved */
|
||||
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
|
||||
uint8_t :1; /*!< bit: 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} CCL_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */
|
||||
#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */
|
||||
|
||||
#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */
|
||||
#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos)
|
||||
#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */
|
||||
#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos)
|
||||
#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */
|
||||
#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos)
|
||||
#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */
|
||||
|
||||
/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */
|
||||
uint8_t :4; /*!< bit: 4.. 7 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint8_t reg; /*!< Type used for register access */
|
||||
} CCL_SEQCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */
|
||||
#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */
|
||||
|
||||
#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */
|
||||
#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos))
|
||||
#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */
|
||||
#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */
|
||||
#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */
|
||||
#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */
|
||||
#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */
|
||||
#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos)
|
||||
#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */
|
||||
|
||||
/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */
|
||||
uint32_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */
|
||||
uint32_t :1; /*!< bit: 6 Reserved */
|
||||
uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */
|
||||
uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */
|
||||
uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */
|
||||
uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */
|
||||
uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */
|
||||
uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */
|
||||
uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */
|
||||
uint32_t :1; /*!< bit: 23 Reserved */
|
||||
uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CCL_LUTCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */
|
||||
#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */
|
||||
|
||||
#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */
|
||||
#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */
|
||||
#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos))
|
||||
#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */
|
||||
#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */
|
||||
#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */
|
||||
#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos)
|
||||
#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */
|
||||
#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */
|
||||
#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos))
|
||||
#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
|
||||
#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
|
||||
#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
|
||||
#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
|
||||
#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
|
||||
#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
|
||||
#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
|
||||
#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */
|
||||
#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos))
|
||||
#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
|
||||
#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
|
||||
#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
|
||||
#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
|
||||
#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
|
||||
#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
|
||||
#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
|
||||
#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */
|
||||
#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos))
|
||||
#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */
|
||||
#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */
|
||||
#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */
|
||||
#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */
|
||||
#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */
|
||||
#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */
|
||||
#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */
|
||||
#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos)
|
||||
#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */
|
||||
#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos)
|
||||
#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */
|
||||
#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos)
|
||||
#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */
|
||||
#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos)
|
||||
#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */
|
||||
#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos)
|
||||
#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos))
|
||||
#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */
|
||||
|
||||
/** \brief CCL hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
|
||||
RoReg8 Reserved1[0x3];
|
||||
__IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */
|
||||
RoReg8 Reserved2[0x2];
|
||||
__IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */
|
||||
} Ccl;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_CCL_COMPONENT_ */
|
||||
|
||||
@@ -1,357 +1,357 @@
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for CMCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CMCC_COMPONENT_
|
||||
#define _SAMD51_CMCC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR CMCC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */
|
||||
/*@{*/
|
||||
|
||||
#define CMCC_U2015
|
||||
#define REV_CMCC 0x600
|
||||
|
||||
/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
|
||||
uint32_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
|
||||
uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
|
||||
uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
|
||||
uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
|
||||
uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_TYPE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
|
||||
#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
|
||||
|
||||
#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
|
||||
#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
|
||||
#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
|
||||
#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
|
||||
#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
|
||||
#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
|
||||
#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
|
||||
#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
|
||||
#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
|
||||
#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
|
||||
#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
|
||||
#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
|
||||
#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
|
||||
#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
|
||||
|
||||
/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
|
||||
uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
|
||||
uint32_t :1; /*!< bit: 3 Reserved */
|
||||
uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
|
||||
uint32_t :25; /*!< bit: 7..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_CFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
|
||||
#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
|
||||
|
||||
#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
|
||||
#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
|
||||
#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
|
||||
#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
|
||||
#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
|
||||
#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
|
||||
|
||||
/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
|
||||
#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
|
||||
|
||||
#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
|
||||
#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
|
||||
#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
|
||||
|
||||
/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_SR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
|
||||
#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
|
||||
|
||||
#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
|
||||
#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
|
||||
#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
|
||||
|
||||
/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
|
||||
uint32_t :28; /*!< bit: 4..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_LCKWAY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
|
||||
#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
|
||||
|
||||
#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
|
||||
#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
|
||||
#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
|
||||
#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
|
||||
|
||||
/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MAINT0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
|
||||
#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
|
||||
|
||||
#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
|
||||
#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
|
||||
#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
|
||||
|
||||
/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :4; /*!< bit: 0.. 3 Reserved */
|
||||
uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
|
||||
uint32_t :16; /*!< bit: 12..27 Reserved */
|
||||
uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MAINT1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
|
||||
#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
|
||||
|
||||
#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
|
||||
#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
|
||||
#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
|
||||
#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
|
||||
#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
|
||||
#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
|
||||
|
||||
/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
|
||||
uint32_t :30; /*!< bit: 2..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MCFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
|
||||
#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
|
||||
|
||||
#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
|
||||
#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
|
||||
#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
|
||||
#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
|
||||
#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
|
||||
#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
|
||||
|
||||
/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MEN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
|
||||
#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
|
||||
|
||||
#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
|
||||
#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
|
||||
#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
|
||||
|
||||
/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
|
||||
#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
|
||||
|
||||
#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
|
||||
#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
|
||||
#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
|
||||
|
||||
/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MSR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
|
||||
#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
|
||||
|
||||
#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
|
||||
#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
|
||||
#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
|
||||
#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
|
||||
|
||||
/** \brief CMCC APB hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
|
||||
__IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
|
||||
__O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
|
||||
__I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
|
||||
__IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
|
||||
RoReg8 Reserved1[0xC];
|
||||
__O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
|
||||
__O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
|
||||
__IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
|
||||
__IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
|
||||
__O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
|
||||
__I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
|
||||
} Cmcc;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_CMCC_COMPONENT_ */
|
||||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Component description for CMCC
|
||||
*
|
||||
* Copyright (c) 2018 Microchip Technology Inc.
|
||||
*
|
||||
* \asf_license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License"); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the Licence at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \asf_license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _SAMD51_CMCC_COMPONENT_
|
||||
#define _SAMD51_CMCC_COMPONENT_
|
||||
|
||||
/* ========================================================================== */
|
||||
/** SOFTWARE API DEFINITION FOR CMCC */
|
||||
/* ========================================================================== */
|
||||
/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */
|
||||
/*@{*/
|
||||
|
||||
#define CMCC_U2015
|
||||
#define REV_CMCC 0x600
|
||||
|
||||
/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */
|
||||
uint32_t :2; /*!< bit: 2.. 3 Reserved */
|
||||
uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */
|
||||
uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */
|
||||
uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */
|
||||
uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */
|
||||
uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */
|
||||
uint32_t :18; /*!< bit: 14..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_TYPE_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */
|
||||
#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */
|
||||
|
||||
#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */
|
||||
#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)
|
||||
#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */
|
||||
#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)
|
||||
#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */
|
||||
#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))
|
||||
#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */
|
||||
#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */
|
||||
#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */
|
||||
#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)
|
||||
#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */
|
||||
#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)
|
||||
#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */
|
||||
#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */
|
||||
#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)
|
||||
#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */
|
||||
|
||||
/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :1; /*!< bit: 0 Reserved */
|
||||
uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */
|
||||
uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */
|
||||
uint32_t :1; /*!< bit: 3 Reserved */
|
||||
uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */
|
||||
uint32_t :25; /*!< bit: 7..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_CFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */
|
||||
#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */
|
||||
|
||||
#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */
|
||||
#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)
|
||||
#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */
|
||||
#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)
|
||||
#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */
|
||||
#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)
|
||||
#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */
|
||||
|
||||
/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_CTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */
|
||||
#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */
|
||||
|
||||
#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */
|
||||
#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)
|
||||
#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */
|
||||
|
||||
/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_SR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */
|
||||
#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */
|
||||
|
||||
#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */
|
||||
#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)
|
||||
#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */
|
||||
|
||||
/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */
|
||||
uint32_t :28; /*!< bit: 4..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_LCKWAY_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */
|
||||
#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */
|
||||
|
||||
#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */
|
||||
#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)
|
||||
#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))
|
||||
#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */
|
||||
|
||||
/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MAINT0_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */
|
||||
#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */
|
||||
|
||||
#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */
|
||||
#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)
|
||||
#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */
|
||||
|
||||
/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t :4; /*!< bit: 0.. 3 Reserved */
|
||||
uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */
|
||||
uint32_t :16; /*!< bit: 12..27 Reserved */
|
||||
uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MAINT1_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */
|
||||
#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */
|
||||
|
||||
#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */
|
||||
#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)
|
||||
#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))
|
||||
#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */
|
||||
#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))
|
||||
#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */
|
||||
#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)
|
||||
#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */
|
||||
|
||||
/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */
|
||||
uint32_t :30; /*!< bit: 2..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MCFG_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */
|
||||
#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */
|
||||
|
||||
#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */
|
||||
#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))
|
||||
#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */
|
||||
#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */
|
||||
#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */
|
||||
#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)
|
||||
#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */
|
||||
|
||||
/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MEN_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */
|
||||
#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */
|
||||
|
||||
#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */
|
||||
#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)
|
||||
#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */
|
||||
|
||||
/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */
|
||||
uint32_t :31; /*!< bit: 1..31 Reserved */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MCTRL_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */
|
||||
#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */
|
||||
|
||||
#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */
|
||||
#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)
|
||||
#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */
|
||||
|
||||
/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */
|
||||
} bit; /*!< Structure used for bit access */
|
||||
uint32_t reg; /*!< Type used for register access */
|
||||
} CMCC_MSR_Type;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */
|
||||
#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */
|
||||
|
||||
#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */
|
||||
#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)
|
||||
#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))
|
||||
#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */
|
||||
|
||||
/** \brief CMCC APB hardware registers */
|
||||
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
typedef struct {
|
||||
__I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */
|
||||
__IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */
|
||||
__O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */
|
||||
__I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */
|
||||
__IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */
|
||||
RoReg8 Reserved1[0xC];
|
||||
__O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */
|
||||
__O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */
|
||||
__IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */
|
||||
__IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */
|
||||
__O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */
|
||||
__I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */
|
||||
} Cmcc;
|
||||
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/*@}*/
|
||||
|
||||
#endif /* _SAMD51_CMCC_COMPONENT_ */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user