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If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/config/printer-creality-ender3-s1-2021.cfg b/config/printer-creality-ender3-s1-2021.cfg index bda56e7..766dd0f 100644 --- a/config/printer-creality-ender3-s1-2021.cfg +++ b/config/printer-creality-ender3-s1-2021.cfg @@ -1,10 +1,9 @@ # This file contains pin mappings for the stock 2021 Creality Ender 3 -# S1 (and S1 pro). To use this config, check the STM32 Chip on the -# V2.4S1 Board then during "make menuconfig" select either the -# STM32F103 with a "28KiB bootloader" or select the STM32F401 with a -# "64KiB bootloader" and serial (on USART1 PA10/PA9) communication for -# both depending on the STM32 chip installed on your printer's -# motherboard. +# S1. To use this config, check the STM32 Chip on the V2.4S1 Board +# then during "make menuconfig" select either the STM32F103 with a +# "28KiB bootloader" or select the STM32F401 with a "64KiB bootloader" +# and serial (on USB PA10/PA9) communication for both depending on the +# STM32 Chip installed on your printers Motherboard. # If you prefer a direct serial connection, in "make menuconfig" # select "Enable extra low-level configuration options" and select diff --git a/config/printer-creality-ender3-s1pro-2022.cfg b/config/printer-creality-ender3-s1pro-2022.cfg new file mode 100644 index 0000000..9116eb0 --- /dev/null +++ b/config/printer-creality-ender3-s1pro-2022.cfg @@ -0,0 +1,130 @@ +# This file contains pin mappings for the stock 2022 Creality Ender 3 +# S1 Pro. To use this config, check the STM32 Chip on the V2.4S1 Board +# then during "make menuconfig" select either the STM32F103 with a +# "28KiB bootloader" or select the STM32F401 with a "64KiB bootloader" +# and serial (on USB PA10/PA9) communication for both depending on the +# STM32 Chip installed on your printers Motherboard. + +# If you prefer a direct serial connection, in "make menuconfig" +# select "Enable extra low-level configuration options" and select +# Serial (on USART2 PA3/PA2), which is broken out on the 10 pin IDC +# cable used for the LCD module as follows: +# 3: Tx, 4: Rx, 9: GND, 10: VCC + +# Flash this firmware by copying "out/klipper.bin" to a SD card and +# turning on the printer with the card inserted. The firmware +# filename must changed to "firmware.bin" + +# See docs/Config_Reference.md for a description of parameters. + +[stepper_x] +step_pin: PC2 +dir_pin: PB9 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: !PA5 +position_endstop: -10 +position_max: 235 +position_min: -15 +homing_speed: 50 + +[stepper_y] +step_pin: PB8 +dir_pin: PB7 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 40 +endstop_pin: !PA6 +position_endstop: -10 +position_max: 241 +position_min: -15 +homing_speed: 50 + +[stepper_z] +step_pin: PB6 +dir_pin: !PB5 +enable_pin: !PC3 +microsteps: 16 +rotation_distance: 8 +endstop_pin: probe:z_virtual_endstop +position_max: 270 +position_min: -4 + +[extruder] +step_pin: PB4 +dir_pin: PB3 +enable_pin: !PC3 +microsteps: 16 +gear_ratio: 42:12 +rotation_distance: 26.359 +nozzle_diameter: 0.400 +filament_diameter: 1.750 +heater_pin: PA1 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC5 +control: pid +pid_Kp: 23.561 +pid_Ki: 1.208 +pid_Kd: 114.859 +min_temp: 0 +max_temp: 300 + +[heater_bed] +heater_pin: PA7 +sensor_type: EPCOS 100K B57560G104F +sensor_pin: PC4 +control: pid +pid_Kp: 71.867 +pid_Ki: 1.536 +pid_Kd: 840.843 +min_temp: 0 +max_temp: 110 + +[heater_fan hotend_fan] +pin: PC0 + +[fan] +pin: PA0 + +[mcu] +serial: /dev/serial/by-id/usb-1a86_USB_Serial-if00-port0 +restart_method: command + +[printer] +kinematics: cartesian +max_velocity: 300 +max_accel: 2000 +max_z_velocity: 5 +max_z_accel: 100 + +[bltouch] +sensor_pin: ^PC14 +control_pin: PC13 +x_offset: -31.8 +y_offset: -40.5 +z_offset: 0 +probe_with_touch_mode: true +stow_on_each_sample: false + +[bed_mesh] +speed: 120 +mesh_min: 20, 20 +mesh_max: 200, 200 +probe_count: 4,4 +algorithm: bicubic + +[safe_z_home] +home_xy_position: 147, 154 +speed: 75 +z_hop: 5 +z_hop_speed: 5 +move_to_previous: true + +[filament_switch_sensor e0_sensor] +switch_pin: !PC15 +pause_on_runout: true +runout_gcode: PAUSE + +[pause_resume] +recover_velocity: 25 diff --git a/config/printer-creality-sermoonV1-2022.cfg b/config/printer-creality-sermoonV1-2022.cfg index ca8a91a..ef100fb 100644 --- a/config/printer-creality-sermoonV1-2022.cfg +++ b/config/printer-creality-sermoonV1-2022.cfg @@ -2,8 +2,7 @@ # with CR-FDM-v2.4.S1.200 motherboard. # To use this config, during "make menuconfig" select the STM32F401 -# with a "64KiB bootloader" and serial (on USART1 PA10/PA9) -# communication. +# with a "64KiB bootloader" and serial (on USB PA10/PA9) communication. # If you prefer a direct serial connection, in "make menuconfig" # select "Enable extra low-level configuration options" and select diff --git a/docs/Status_Reference.md b/docs/Status_Reference.md index 4c7883c..4cc7512 100644 --- a/docs/Status_Reference.md +++ b/docs/Status_Reference.md @@ -244,17 +244,6 @@ The following information is available for each `[led led_name]`, chain could be accessed at `printer["neopixel "].color_data[1][2]`. -## manual_probe - -The following information is available in the -`manual_probe` object: -- `is_active`: Returns True if a manual probing helper script is currently -active. -- `z_position`: The current height of the nozzle (as the printer currently -understands it). -- `z_position_lower`: Last probe attempt just lower than the current height. -- `z_position_upper`: Last probe attempt just greater than the current height. - ## mcu The following information is available in diff --git a/klippy/__pycache__/msgproto.cpython-37.pyc b/klippy/__pycache__/msgproto.cpython-37.pyc deleted file mode 100644 index 648cb17ae40d3c4aa7821760c99ab4c16fc765ad..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 16000 zcmbtbdu$xXdEeLF?H!L4MbQ*REAm+qZBdqG*$JG~m1WAZ7*|weWz~gAQbWdnlvej6lt0^ZP5Nz6ex=Rxj@qbDT?a90!4wsD4_m+ z-|X%^L?t$Q#C$t5J3EhWzV{3t9Ud-O`28^W@#W6XTh>olNPk6SW|6|r+m@v)WiMM* z^R%nBl%1-Br=#3=ovN$6s;6?*oXS`8s!%N`tLiJKT138t=TMLfyh*ECR(^F@6{{nv zRNeKsrG`}bElZVy(Ji;STMes`x2)UXJ8)Q@gC)jcTfR%0lQ1$)qH9OXS~9OZE- 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gcode.error(msg) # Request a restart - gcode.request_restart('restart') + gcode.request_restart('firmware_restart') + + cmd_SAVE_CONFIG_QD_help = "Overwrite config file and restart" + def cmd_SAVE_CONFIG_QD(self, gcmd): + if not self.autosave.fileconfig.sections(): + return + gcode = self.printer.lookup_object('gcode') + # Create string containing autosave data + autosave_data = self._build_config_string(self.autosave) + lines = [('#*# ' + l).strip() + for l in autosave_data.split('\n')] + lines.insert(0, "\n" + AUTOSAVE_HEADER.rstrip()) + lines.append("") + autosave_data = '\n'.join(lines) + # Read in and validate current config file + cfgname = self.printer.get_start_args()['config_file'] + try: + data = self._read_config_file(cfgname) + regular_data, old_autosave_data = self._find_autosave_data(data) + config = self._build_config_wrapper(regular_data, cfgname) + except error as e: + msg = "Unable to parse existing config on SAVE_CONFIG" + logging.exception(msg) + raise gcode.error(msg) + regular_data = self._strip_duplicates(regular_data, self.autosave) + self._disallow_include_conflicts(regular_data, cfgname, gcode) + data = regular_data.rstrip() + autosave_data + # Determine filenames + datestr = time.strftime("-%Y%m%d_%H%M%S") + backup_name = cfgname + datestr + temp_name = cfgname + "_autosave" + if cfgname.endswith(".cfg"): + backup_name = cfgname[:-4] + datestr + ".cfg" + temp_name = cfgname[:-4] + "_autosave.cfg" + # Create new config file with temporary name and swap with main config + logging.info("SAVE_CONFIG to '%s' (backup in '%s')", + cfgname, backup_name) + try: + f = open(temp_name, 'w') + f.write(data) + f.flush() + f.close() + os.rename(cfgname, backup_name) + os.rename(temp_name, cfgname) + os.system("sync") + except: + msg = "Unable to write config file during SAVE_CONFIG" + logging.exception(msg) + raise gcode.error(msg) diff --git a/klippy/configfile.pyc b/klippy/configfile.pyc deleted file mode 100644 index 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b/klippy/extras/chamber_fan.py new file mode 100644 index 0000000..b87b02d --- /dev/null +++ b/klippy/extras/chamber_fan.py @@ -0,0 +1,52 @@ +from . import fan + +PIN_MIN_TIME = 0.100 + +class ChamberFan: + def __init__(self, config): + self.printer = config.get_printer() + self.printer.register_event_handler("klippy:ready", self.handle_ready) + self.printer.register_event_handler("klippy:connect", + self.handle_connect) + self.printer.load_object(config, 'heaters') + self.heaters = [] + self.fan = fan.Fan(config) + self.fan_speed = config.getfloat('fan_speed', default=1., + minval=0., maxval=1.) + self.idle_speed = config.getfloat( + 'idle_speed', default=self.fan_speed, minval=0., maxval=1.) + self.idle_timeout = config.getint("idle_timeout", default=30, minval=0) + self.heater_names = config.getlist("heater", ()) + self.last_on = self.idle_timeout + self.last_speed = 0. + def handle_connect(self): + # Heater lookup + pheaters = self.printer.lookup_object('heaters') + self.heaters = [pheaters.lookup_heater(n) for n in self.heater_names] + def handle_ready(self): + reactor = self.printer.get_reactor() + reactor.register_timer(self.callback, reactor.monotonic()+PIN_MIN_TIME) + def get_status(self, eventtime): + return self.fan.get_status(eventtime) + def callback(self, eventtime): + speed = 0. + active = False + for heater in self.heaters: + _, target_temp = heater.get_temp(eventtime) + if target_temp: + active = True + if active: + self.last_on = 0 + speed = self.fan_speed + elif self.last_on < self.idle_timeout: + speed = self.idle_speed + self.last_on += 1 + if speed != self.last_speed: + self.last_speed = speed + curtime = self.printer.get_reactor().monotonic() + print_time = self.fan.get_mcu().estimated_print_time(curtime) + self.fan.set_speed(print_time + PIN_MIN_TIME, speed) + return eventtime + 1. + +def load_config_prefix(config): + return ChamberFan(config) diff --git a/klippy/extras/delayed_gcode.pyc b/klippy/extras/delayed_gcode.pyc deleted file mode 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zbS1dPRTJp?mBrHtyy4+b_x6vChcN0BR9n*CDyuQL$&NS+$RzanhGAEJ9R;% dH}zuzChq#g-(yfLDQ+4!ZL{9g&Dz|(e*vqE{|Nv9 diff --git a/klippy/extras/endstop_phase.py b/klippy/extras/endstop_phase.py index a20cdc3..bd34ddb 100644 --- a/klippy/extras/endstop_phase.py +++ b/klippy/extras/endstop_phase.py @@ -6,7 +6,7 @@ import math, logging import stepper -TRINAMIC_DRIVERS = ["tmc2130", "tmc2208", "tmc2209", "tmc2240", "tmc2660", "tmc5160"] +TRINAMIC_DRIVERS = ["tmc2130", "tmc2208", "tmc2209", "tmc2660", "tmc5160"] # Calculate the trigger phase of a stepper motor class PhaseCalc: diff --git a/klippy/extras/exclude_object.pyc b/klippy/extras/exclude_object.pyc deleted file mode 100644 index 7423a5849285ec4b8aa0b641bd18d5af5ec1e252..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 11087 zcmcIq+jAUOUOqiDx{M-OvSitkoy3!bB$M651_DkhC}tB$S=QN%!;!MdYVkIs>6Sdw zs9WySDCz~_TIaQuF(X82;H_@Dm3nn^mwl0`xUd2TdEtsu~Cc2>FB@->0ttAs( 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self._enable = config.getboolean("enable_force_move", False) # Setup iterative solver ffi_main, ffi_lib = chelper.get_ffi() self.trapq = ffi_main.gc(ffi_lib.trapq_alloc(), ffi_lib.trapq_free) @@ -44,8 +45,8 @@ class ForceMove: gcode.register_command('STEPPER_BUZZ', self.cmd_STEPPER_BUZZ, desc=self.cmd_STEPPER_BUZZ_help) gcode.register_command('SET_KINEMATIC_POSITION', - self.cmd_SET_KINEMATIC_POSITION, - desc=self.cmd_SET_KINEMATIC_POSITION_help) + self.cmd_SET_KINEMATIC_POSITION, + desc=self.cmd_SET_KINEMATIC_POSITION_help) if config.getboolean("enable_force_move", False): gcode.register_command('FORCE_MOVE', self.cmd_FORCE_MOVE, desc=self.cmd_FORCE_MOVE_help) @@ -113,16 +114,18 @@ class ForceMove: self._restore_enable(stepper, was_enable) cmd_FORCE_MOVE_help = "Manually move a stepper; invalidates kinematics" def cmd_FORCE_MOVE(self, gcmd): - stepper = self._lookup_stepper(gcmd) - distance = gcmd.get_float('DISTANCE') - speed = gcmd.get_float('VELOCITY', above=0.) - accel = gcmd.get_float('ACCEL', 0., minval=0.) - logging.info("FORCE_MOVE %s distance=%.3f velocity=%.3f accel=%.3f", - stepper.get_name(), distance, speed, accel) - self._force_enable(stepper) - self.manual_move(stepper, distance, speed, accel) + if self._enable: + stepper = self._lookup_stepper(gcmd) + distance = gcmd.get_float('DISTANCE') + speed = gcmd.get_float('VELOCITY', above=0.) + accel = gcmd.get_float('ACCEL', 0., minval=0.) + logging.info("FORCE_MOVE %s distance=%.3f velocity=%.3f accel=%.3f", + stepper.get_name(), distance, speed, accel) + self._force_enable(stepper) + self.manual_move(stepper, distance, speed, accel) cmd_SET_KINEMATIC_POSITION_help = "Force a low-level kinematic position" def cmd_SET_KINEMATIC_POSITION(self, gcmd): +# if self._enable: toolhead = self.printer.lookup_object('toolhead') toolhead.get_last_move_time() curpos = toolhead.get_position() @@ -131,7 +134,6 @@ class ForceMove: z = gcmd.get_float('Z', curpos[2]) logging.info("SET_KINEMATIC_POSITION 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self.name = config.get_name().split()[-1] + self.printer = config.get_printer() + self.gcode = self.printer.lookup_object('gcode') + cmd = config.get('command') + cmd = os.path.expanduser(cmd) + self.command = shlex.split(cmd) + self.timeout = config.getfloat('timeout', 2., above=0.) + self.verbose = config.getboolean('verbose', True) + self.proc_fd = None + self.partial_output = "" + self.gcode.register_mux_command( + "RUN_SHELL_COMMAND", "CMD", self.name, + self.cmd_RUN_SHELL_COMMAND, + desc=self.cmd_RUN_SHELL_COMMAND_help) + + def _process_output(self, eventime): + if self.proc_fd is None: + return + try: + data = os.read(self.proc_fd, 4096) + except Exception: + pass + data = self.partial_output + data.decode() + if '\n' not in data: + self.partial_output = data + return + elif data[-1] != '\n': + split = data.rfind('\n') + 1 + self.partial_output = data[split:] + data = data[:split] + else: + self.partial_output = "" + self.gcode.respond_info(data) + + cmd_RUN_SHELL_COMMAND_help = "Run a linux shell command" + def cmd_RUN_SHELL_COMMAND(self, params): + gcode_params = params.get('PARAMS','') + gcode_params = shlex.split(gcode_params) + reactor = self.printer.get_reactor() + try: + proc = subprocess.Popen( + self.command + gcode_params, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) + except Exception: + logging.exception( + "shell_command: Command {%s} failed" % (self.name)) + raise self.gcode.error("Error running command {%s}" % (self.name)) + if self.verbose: + self.proc_fd = proc.stdout.fileno() + self.gcode.respond_info("Running Command {%s}...:" % (self.name)) + hdl = reactor.register_fd(self.proc_fd, self._process_output) + eventtime = reactor.monotonic() + endtime = eventtime + self.timeout + complete = False + while eventtime < endtime: + eventtime = reactor.pause(eventtime + .05) + if proc.poll() is not None: + complete = True + break + if not complete: + proc.terminate() + if self.verbose: + if self.partial_output: + self.gcode.respond_info(self.partial_output) + self.partial_output = "" + if complete: + msg = "Command {%s} finished\n" % (self.name) + else: + msg = "Command {%s} timed out" % (self.name) + self.gcode.respond_info(msg) + reactor.unregister_fd(hdl) + self.proc_fd = None + + +def load_config_prefix(config): + return ShellCommand(config) diff --git a/klippy/extras/hall_filament_width_sensor.py b/klippy/extras/hall_filament_width_sensor.py index 276dd14..e3f9bb8 100644 --- a/klippy/extras/hall_filament_width_sensor.py +++ b/klippy/extras/hall_filament_width_sensor.py @@ -146,11 +146,11 @@ class HallFilamentWidthSensor: and (self.filament_width >= self.min_diameter)): percentage = round(self.nominal_filament_dia**2 / self.filament_width**2 * 100) - self.gcode.run_script("M221 S" + str(percentage)) - else: - self.gcode.run_script("M221 S100") + # self.gcode.run_script("M221 S" + str(percentage)) + # else: + # self.gcode.run_script("M221 S100") else: - self.gcode.run_script("M221 S100") + # self.gcode.run_script("M221 S100") self.filament_array = [] if self.is_active: @@ -171,7 +171,7 @@ class HallFilamentWidthSensor: self.filament_array = [] gcmd.respond_info("Filament width measurements cleared!") # Set extrude multiplier to 100% - self.gcode.run_script_from_command("M221 S100") + # self.gcode.run_script_from_command("M221 S100") def cmd_M405(self, gcmd): response = "Filament width sensor Turned On" @@ -196,7 +196,7 @@ class HallFilamentWidthSensor: # Clear filament array self.filament_array = [] # Set extrude multiplier to 100% - self.gcode.run_script_from_command("M221 S100") + # self.gcode.run_script_from_command("M221 S100") gcmd.respond_info(response) def cmd_Get_Raw_Values(self, gcmd): diff --git a/klippy/extras/heater_bed.pyc b/klippy/extras/heater_bed.pyc deleted file mode 100644 index 55dde002a0304dbef7d5c81ab8992c7bb5f07fce..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1532 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GIT binary patch literal 0 HcmV?d00001 literal 410 zcmbVIOHRWu5FMuo5YP=PE`XF35qpG?*mnUtHc{$KQ>Xb@_Ec&mScPkG6)wRAc#}|d zkEQqKdH(k7XMXX;-%Cq>$G|=TaSkepK8fBS485iaJXYf>X23HLZ$a-wHPHYzs*yb; z^Z{+CPSi6T>KAf`{52QCA*R|yE&v+-Hh}l$?SKM)M_RjC+8dc-;sX4ad lmD}mk@dQNX#w=3(gcsdloOGmr&eR7yw0*g4_)#YbK)<&MUE}}& diff --git a/klippy/extras/heaters.py b/klippy/extras/heaters.py index b0b2c16..9fdf47b 100644 --- a/klippy/extras/heaters.py +++ b/klippy/extras/heaters.py @@ -241,6 +241,16 @@ class PrinterHeaters: gcode.register_command("M105", self.cmd_M105, when_not_ready=True) gcode.register_command("TEMPERATURE_WAIT", self.cmd_TEMPERATURE_WAIT, desc=self.cmd_TEMPERATURE_WAIT_help) + # Wait heater interupt + webhooks = self.printer.lookup_object('webhooks') + webhooks.register_endpoint("breakheater", self._handle_breakheater) + self.break_flag=False + def _handle_breakheater(self,web_request): + reactor = self.printer.get_reactor() + for heater in self.heaters.values(): + eventtime = reactor.monotonic() + if heater.check_busy(eventtime): + self.break_flag = True def load_config(self, config): self.have_load_sensors = True # Load default temperature sensors @@ -330,7 +340,11 @@ class PrinterHeaters: gcode = self.printer.lookup_object("gcode") reactor = self.printer.get_reactor() eventtime = reactor.monotonic() + self.break_flag = False while not self.printer.is_shutdown() and heater.check_busy(eventtime): + if self.break_flag: + self.break_flag = False + break print_time = toolhead.get_last_move_time() gcode.respond_raw(self._get_temp(eventtime)) eventtime = reactor.pause(eventtime + 1.) @@ -359,7 +373,7 @@ class PrinterHeaters: toolhead = self.printer.lookup_object("toolhead") reactor = self.printer.get_reactor() eventtime = reactor.monotonic() - while not self.printer.is_shutdown(): + while not self.printer.is_shutdown() and not self.break_flag: temp, target = sensor.get_temp(eventtime) if temp >= min_temp and temp <= max_temp: return diff --git a/klippy/extras/heaters.pyc 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prior to movement") + # 2023/12/14 Chengwei + # error to info + gcode = self.printer.lookup_object('gcode') + gcode.respond_info('Probe triggered prior to movement') + ###### + # raise self.printer.command_error( + # "Probe triggered prior to movement") + ###### return epos def cmd_G28(self, gcmd): # Move to origin diff --git a/klippy/extras/homing.pyc b/klippy/extras/homing.pyc deleted file mode 100644 index c253f73cad5c1557909eb0d550706ccba3a7ce35..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 12680 zcmcIq+jAt>SwB6a+eq4#R=1VpwXN8gRqVCb*e+t6Wu5g(_BwdwrL{)!5~XW2-I7L{ zi`3oY)rJ`e**I~kLKTpLA{3WE;fEAO6|X$-2k-_w!3$N+3y<7hQ^4={`?_aFYsVGI zwxm8f=k&RJ=evL3>Ei#K8U6d{-?l0)`zhl8m+&OtLlNT7b2aDgbnBkGnH&qzg;ku3;CBy6~I}$GTk@GVa1D z7oO>Mm0Wn1jXN0Yx%K5~095@y{H*Q#_^q3ht^c@M9l*;<0R=0A zczBKkkh|2m_W%lj_S}BK#fxm>01NAF=k`1T*(tbo!R-~?cbwbCz@q!MW_;IkM;AGK zW%E(jDQ1J(MfV*~;|AQfG2e6E;i}tsk1%rQwW^1*ipN!0BUFTj@Fx$W*bzi4n^Ugi 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self.cmd_Z_OFFSET_APPLY_ENDSTOP, desc=self.cmd_Z_OFFSET_APPLY_ENDSTOP_help) - self.reset_status() def manual_probe_finalize(self, kin_pos): if kin_pos is not None: self.gcode.respond_info("Z position is %.3f" % (kin_pos[2],)) - def reset_status(self): - self.status = { - 'is_active': False, - 'z_position': None, - 'z_position_lower': None, - 'z_position_upper': None - } - def get_status(self, eventtime): - return self.status cmd_MANUAL_PROBE_help = "Start manual probe helper script" def cmd_MANUAL_PROBE(self, gcmd): ManualProbeHelper(self.printer, gcmd, self.manual_probe_finalize) @@ -88,7 +78,6 @@ class ManualProbeHelper: self.finalize_callback = finalize_callback self.gcode = self.printer.lookup_object('gcode') self.toolhead = self.printer.lookup_object('toolhead') - self.manual_probe = self.printer.lookup_object('manual_probe') self.speed = gcmd.get_float("SPEED", 5.) self.past_positions = [] self.last_toolhead_pos = self.last_kinematics_pos = None @@ -141,20 +130,11 @@ class ManualProbeHelper: prev_pos = next_pos - 1 if next_pos < len(pp) and pp[next_pos] == z_pos: next_pos += 1 - prev_pos_val = next_pos_val = None prev_str = next_str = "??????" if prev_pos >= 0: - prev_pos_val = pp[prev_pos] - prev_str = "%.3f" % (prev_pos_val,) + prev_str = "%.3f" % (pp[prev_pos],) if next_pos < len(pp): - next_pos_val = pp[next_pos] - next_str = "%.3f" % (next_pos_val,) - self.manual_probe.status = { - 'is_active': True, - 'z_position': z_pos, - 'z_position_lower': prev_pos_val, - 'z_position_upper': next_pos_val, - } + next_str = "%.3f" % (pp[next_pos],) # Find recent positions self.gcode.respond_info("Z position: %s --> %.3f <-- %s" % (prev_str, z_pos, next_str)) @@ -203,7 +183,6 @@ class ManualProbeHelper: self.move_z(next_z_pos) self.report_z_status(next_z_pos != z_pos, z_pos) def finalize(self, success): - self.manual_probe.reset_status() self.gcode.register_command('ACCEPT', None) self.gcode.register_command('NEXT', None) self.gcode.register_command('ABORT', None) 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- / gc_status['extrude_factor'] - self.last_epos = cur_epos - def set_current_file(self, filename): - self.reset() - self.filename = filename - def note_start(self): - curtime = self.reactor.monotonic() - if self.print_start_time is None: - self.print_start_time = curtime - elif self.last_pause_time is not None: - # Update pause time duration - pause_duration = curtime - self.last_pause_time - self.prev_pause_duration += pause_duration - self.last_pause_time = None - # Reset last e-position - gc_status = self.gcode_move.get_status(curtime) - self.last_epos = gc_status['position'].e - self.state = "printing" - self.error_message = "" - def note_pause(self): - if self.last_pause_time is None: - curtime = self.reactor.monotonic() - self.last_pause_time = curtime - # update filament usage - self._update_filament_usage(curtime) - if self.state != "error": - self.state = "paused" - def note_complete(self): - self._note_finish("complete") - def note_error(self, message): - self._note_finish("error", message) - def note_cancel(self): - self._note_finish("cancelled") - def _note_finish(self, state, error_message = ""): - if self.print_start_time is None: - return - self.state = state - self.error_message = error_message - eventtime = self.reactor.monotonic() - self.total_duration = eventtime - self.print_start_time - if self.filament_used < 0.0000001: - # No positive extusion detected during print - self.init_duration = self.total_duration - \ - self.prev_pause_duration - self.print_start_time = None - def reset(self): - self.filename = self.error_message = "" - self.state = "standby" - self.prev_pause_duration = self.last_epos = 0. - self.filament_used = self.total_duration = 0. - self.print_start_time = self.last_pause_time = None - self.init_duration = 0. - def get_status(self, eventtime): - time_paused = self.prev_pause_duration - if self.print_start_time is not None: - if self.last_pause_time is not None: - # Calculate the total time spent paused during the print - time_paused += eventtime - self.last_pause_time - else: - # Accumulate filament if not paused - self._update_filament_usage(eventtime) - self.total_duration = eventtime - self.print_start_time - if self.filament_used < 0.0000001: - # Track duration prior to extrusion - self.init_duration = self.total_duration - time_paused - print_duration = self.total_duration - self.init_duration - time_paused - return { - 'filename': self.filename, - 'total_duration': self.total_duration, - 'print_duration': print_duration, - 'filament_used': self.filament_used, - 'state': self.state, - 'message': self.error_message - } - -def load_config(config): - return PrintStats(config) +# Virtual SDCard print stat tracking +# +# Copyright (C) 2020 Eric Callahan +# +# This file may be distributed under the terms of the GNU GPLv3 license. + +class PrintStats: + def __init__(self, config): + printer = config.get_printer() + self.gcode_move = printer.load_object(config, 'gcode_move') + self.reactor = printer.get_reactor() + self.reset() + # Register commands + self.gcode = printer.lookup_object('gcode') + self.gcode.register_command( + "SET_PRINT_STATS_INFO", self.cmd_SET_PRINT_STATS_INFO, + desc=self.cmd_SET_PRINT_STATS_INFO_help) + def _update_filament_usage(self, eventtime): + gc_status = self.gcode_move.get_status(eventtime) + cur_epos = gc_status['position'].e + self.filament_used += (cur_epos - self.last_epos) \ + / gc_status['extrude_factor'] + self.last_epos = cur_epos + def set_current_file(self, filename): + self.reset() + self.filename = filename + def note_start(self): + curtime = self.reactor.monotonic() + if self.print_start_time is None: + self.print_start_time = curtime + elif self.last_pause_time is not None: + # Update pause time duration + pause_duration = curtime - self.last_pause_time + self.prev_pause_duration += pause_duration + self.last_pause_time = None + # Reset last e-position + gc_status = self.gcode_move.get_status(curtime) + self.last_epos = gc_status['position'].e + self.state = "printing" + self.error_message = "" + def note_pause(self): + if self.last_pause_time is None: + curtime = self.reactor.monotonic() + self.last_pause_time = curtime + # update filament usage + self._update_filament_usage(curtime) + if self.state != "error": + self.state = "paused" + def note_complete(self): + self._note_finish("complete") + def note_error(self, message): + self._note_finish("error", message) + def note_cancel(self): + self._note_finish("cancelled") + def _note_finish(self, state, error_message = ""): + if self.print_start_time is None: + return + self.state = state + self.error_message = error_message + eventtime = self.reactor.monotonic() + self.total_duration = eventtime - self.print_start_time + if self.filament_used < 0.0000001: + # No positive extusion detected during print + self.init_duration = self.total_duration - \ + self.prev_pause_duration + self.print_start_time = None + cmd_SET_PRINT_STATS_INFO_help = "Pass slicer info like layer act and " \ + "total to klipper" + def cmd_SET_PRINT_STATS_INFO(self, gcmd): + total_layer = gcmd.get_int("TOTAL_LAYER", self.info_total_layer, \ + minval=0) + current_layer = gcmd.get_int("CURRENT_LAYER", self.info_current_layer, \ + minval=0) + if total_layer == 0: + self.info_total_layer = None + self.info_current_layer = None + elif total_layer != self.info_total_layer: + self.info_total_layer = total_layer + self.info_current_layer = 0 + + if self.info_total_layer is not None and \ + current_layer is not None and \ + current_layer != self.info_current_layer: + self.info_current_layer = min(current_layer, self.info_total_layer) + def reset(self): + self.filename = self.error_message = "" + self.state = "standby" + self.prev_pause_duration = self.last_epos = 0. + self.filament_used = self.total_duration = 0. + self.print_start_time = self.last_pause_time = None + self.init_duration = 0. + self.info_total_layer = None + self.info_current_layer = None + def get_status(self, eventtime): + time_paused = self.prev_pause_duration + if self.print_start_time is not None: + if self.last_pause_time is not None: + # Calculate the total time spent paused during the print + time_paused += eventtime - self.last_pause_time + else: + # Accumulate filament if not paused + self._update_filament_usage(eventtime) + self.total_duration = eventtime - self.print_start_time + if self.filament_used < 0.0000001: + # Track duration prior to extrusion + self.init_duration = self.total_duration - time_paused + print_duration = self.total_duration - self.init_duration - time_paused + return { + 'filename': self.filename, + 'total_duration': self.total_duration, + 'print_duration': print_duration, + 'filament_used': self.filament_used, + 'state': self.state, + 'message': self.error_message, + 'info': {'total_layer': self.info_total_layer, + 'current_layer': self.info_current_layer} + } + +def load_config(config): + return PrintStats(config) diff --git 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Retrying...") + last_probe_failed = True retries += 1 positions = [] + self.probe_count += 1 # Retract if len(positions) < sample_count: - self._move(probexy + [pos[2] + sample_retract_dist], lift_speed) + if last_probe_failed: + self._move(probexy + [sample_retract_dist * 2], lift_speed) + if self.probe_count != 0 and self.probe_count % self.vibrate == 0: + gcode.respond_info('Probe ' + str(self.probe_count) + " times, start vibrating") + commands = [ + 'G91', + 'G1 Z20 F300', + 'G90', + 'G1 Z10 F300' + ] + gcode._process_commands(commands, False) + self.vibrate_gcode.run_gcode_from_command() + last_probe_failed = False + else: + self._move(probexy + [pos[2] + sample_retract_dist], lift_speed) if must_notify_multi_probe: self.multi_probe_end() # Calculate and return result @@ -274,8 +302,7 @@ class PrinterProbe: # Move the nozzle over the probe point curpos[0] += self.x_offset curpos[1] += self.y_offset - #PwAddNew - self._move(curpos,80.) + self._move(curpos, self.speed) # Start manual probe manual_probe.ManualProbeHelper(self.printer, gcmd, self.probe_calibrate_finalize) @@ -293,6 +320,14 @@ class PrinterProbe: % (self.name, new_calibrate)) configfile.set(self.name, 'z_offset', "%.3f" % (new_calibrate,)) cmd_Z_OFFSET_APPLY_PROBE_help = "Adjust the probe's z_offset" + def cmd_MKS_SHOW_Z_OFFSET(self, gcmd): + offset = self.gcode_move.get_status()['homing_origin'].z + if offset == 0: + self.gcode.respond_info("Nothing to do: Z Offset is 0") + else: + new_calibrate = self.z_offset - offset + self.gcode.respond_info(" %s: z_offset: %.3f\n" % (self.name, new_calibrate)) + cmd_MKS_SHOW_Z_OFFSET_help = "Show the probe's z_offset" # Endstop wrapper that enables probe specific features class ProbeEndstopWrapper: @@ -382,6 +417,11 @@ class ProbePointsHelper: self.lift_speed = self.speed self.probe_offsets = (0., 0., 0.) self.results = [] + # vibrate + self.vibrate = config.getint('vibrate', 9999999) + gcode_macro = self.printer.load_object(config, 'gcode_macro') + self.vibrate_gcode = gcode_macro.load_template( + config, 'vibrate_gcode', '') def minimum_points(self,n): if len(self.probe_points) < n: raise self.printer.config_error( @@ -434,11 +474,23 @@ class ProbePointsHelper: raise gcmd.error("horizontal_move_z can't be less than" " probe's z_offset") probe.multi_probe_begin() + probe.probe_count = 0 while 1: done = self._move_next() if done: break + if self.gcode.break_flag: + break pos = probe.run_probe(gcmd) + probe.probe_count += 1 + gcode = self.printer.lookup_object('gcode') + if self.vibrate and probe.probe_count % self.vibrate == 0: + commands = [ + 'G90', + 'G1 Z'+ str(self.horizontal_move_z) + ' F300' + ] + gcode._process_commands(commands, False) + self.vibrate_gcode.run_gcode_from_command() self.results.append(pos) probe.multi_probe_end() def _manual_probe_start(self): diff --git a/klippy/extras/probe.pyc b/klippy/extras/probe.pyc deleted file mode 100644 index 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= config.get_printer() + self.position_endstop = config.getfloat('z_offset') + self.stow_on_each_sample = config.getboolean( + 'deactivate_on_each_sample', True) + gcode_macro = self.printer.load_object(config, 'gcode_macro') + self.activate_gcode = gcode_macro.load_template( + config, 'activate_gcode', '') + self.deactivate_gcode = gcode_macro.load_template( + config, 'deactivate_gcode', '') + ppins = self.printer.lookup_object('pins') + pin = config.get('pin') + pin_params = ppins.lookup_pin(pin, can_invert=True, can_pullup=True) + mcu = pin_params['chip'] + self.mcu_endstop = mcu.setup_pin('endstop', pin_params) + self.printer.register_event_handler('klippy:mcu_identify', + self._handle_mcu_identify) + # Wrappers + self.get_mcu = self.mcu_endstop.get_mcu + self.add_stepper = self.mcu_endstop.add_stepper + self.get_steppers = self.mcu_endstop.get_steppers + self.home_start = self.mcu_endstop.home_start + self.home_wait = self.mcu_endstop.home_wait + self.query_endstop = self.mcu_endstop.query_endstop + # multi probes state + self.multi = 'OFF' + def _handle_mcu_identify(self): + kin = self.printer.lookup_object('toolhead').get_kinematics() + for stepper in kin.get_steppers(): + if stepper.is_active_axis('z'): + self.add_stepper(stepper) + def raise_probe(self): + toolhead = self.printer.lookup_object('toolhead') + start_pos = toolhead.get_position() + self.deactivate_gcode.run_gcode_from_command() + if toolhead.get_position()[:3] != start_pos[:3]: + raise self.printer.command_error( + "Toolhead moved during probe activate_gcode script") + def lower_probe(self): + toolhead = self.printer.lookup_object('toolhead') + start_pos = toolhead.get_position() + self.activate_gcode.run_gcode_from_command() + if toolhead.get_position()[:3] != start_pos[:3]: + raise self.printer.command_error( + "Toolhead moved during probe deactivate_gcode script") + def multi_probe_begin(self): + if self.stow_on_each_sample: + return + self.multi = 'FIRST' + def multi_probe_end(self): + if self.stow_on_each_sample: + return + self.raise_probe() + self.multi = 'OFF' + def probe_prepare(self, hmove): + if self.multi == 'OFF' or self.multi == 'FIRST': + self.lower_probe() + if self.multi == 'FIRST': + self.multi = 'ON' + def probe_finish(self, hmove): + if self.multi == 'OFF': + self.raise_probe() + def get_position_endstop(self): + return self.position_endstop + +class MakerBase: + def __init__(self, config): + self.printer = config.get_printer() + self.gcode = self.printer.lookup_object('gcode') + # self.speed = config.getfloat('speed', 5.0, above=0.) + # self.lift_speed = config.getfloat('lift_speed', self.speed, above=0.) + # self.x_offset = config.getfloat('x_offset', 0.) + # self.y_offset = config.getfloat('y_offset', 0.) + # self.z_offset = config.getfloat('z_offset') + self.probe = self.printer.lookup_object('probe') + self.endstop_wrapper = probe.ProbeEndstopWrapper(config) + # self.probe_accel = config.getfloat('probe_accel', 0., minval=0.) + # self.recovery_time = config.getfloat('recovery_time', 0.4, minval=0.) + # Register MakerBase commands + self.gcode.register_command('MKS_PROBE_PIN_1', self.cmd_MKS_PROBE_PIN_1, + desc=self.cmd_MKS_PROBE_PIN_1_help) + self.gcode.register_command('MKS_PROBE_PIN_2', self.cmd_MKS_PROBE_PIN_2, + desc=self.cmd_MKS_PROBE_PIN_2_help) + self.gcode.register_command('QIDI_PROBE_PIN_1', self.cmd_MKS_PROBE_PIN_1, + desc=self.cmd_MKS_PROBE_PIN_1_help) + self.gcode.register_command('QIDI_PROBE_PIN_2', self.cmd_MKS_PROBE_PIN_2, + desc=self.cmd_MKS_PROBE_PIN_2_help) + self.gcode.register_command('MKS_REMOVE', self.cmd_MKS_REMOVE, + desc=self.cmd_MKS_REMOVE_help) + cmd_MKS_PROBE_PIN_2_help = 'ENABLE_PROBE_PIN_2' + def cmd_MKS_PROBE_PIN_2(self, gcmd): + self.probe.mcu_probe.probe_wrapper = self.endstop_wrapper + # Wrappers + self.probe.mcu_probe.get_mcu = self.endstop_wrapper.get_mcu + self.probe.mcu_probe.add_stepper = self.endstop_wrapper.add_stepper + self.probe.mcu_probe.get_steppers = self.endstop_wrapper.get_steppers + self.probe.mcu_probe.home_start = self.endstop_wrapper.home_start + self.probe.mcu_probe.home_wait = self.endstop_wrapper.home_wait + self.probe.mcu_probe.query_endstop = self.endstop_wrapper.query_endstop + self.probe.mcu_probe.multi_probe_begin = self.endstop_wrapper.multi_probe_begin + self.probe.mcu_probe.multi_probe_end = self.endstop_wrapper.multi_probe_end + # gcmd.respond_raw("%s" % (self.cmd_MKS_PROBE_PIN_2_help, )) + cmd_MKS_REMOVE_help = 'MKS_REMOVE' + def cmd_MKS_REMOVE(self, gcmd): + self.printer.remove_object('probe') + self.printer.lookup_object('gcode').remove_command('PROBE') + self.printer.lookup_object('gcode').remove_command('QUERY_PROBE') + self.printer.lookup_object('gcode').remove_command('PROBE_CALIBRATE') + self.printer.lookup_object('gcode').remove_command('PROBE_ACCURACY') + self.printer.lookup_object('gcode').remove_command('Z_OFFSET_APPLY_PROBE') + self.printer.lookup_object('gcode').remove_command('MKS_SHOW_Z_OFFSET') + self.printer.lookup_object('pins').remove_chip('probe') + cmd_MKS_PROBE_PIN_1_help = 'ENABLE_PROBE_PIN_1' + def cmd_MKS_PROBE_PIN_1(self, gcmd): + self.probe.mcu_probe.probe_wrapper = self.probe.mcu_probe.probe_wrapper_2 + # Wrappers + self.probe.mcu_probe.get_mcu = self.probe.mcu_probe.probe_wrapper_2.get_mcu + self.probe.mcu_probe.add_stepper = self.probe.mcu_probe.probe_wrapper_2.add_stepper + self.probe.mcu_probe.get_steppers = self.probe.mcu_probe.probe_wrapper_2.get_steppers + self.probe.mcu_probe.home_start = self.probe.mcu_probe.probe_wrapper_2.home_start + self.probe.mcu_probe.home_wait = self.probe.mcu_probe.probe_wrapper_2.home_wait + self.probe.mcu_probe.query_endstop = self.probe.mcu_probe.probe_wrapper_2.query_endstop + self.probe.mcu_probe.multi_probe_begin = self.probe.mcu_probe.probe_wrapper_2.multi_probe_begin + self.probe.mcu_probe.multi_probe_end = self.probe.mcu_probe.probe_wrapper_2.multi_probe_end + # gcmd.respond_raw("%s" % (self.cmd_MKS_PROBE_PIN_1_help, )) + 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self.probe_wrapper.add_stepper @@ -78,6 +78,16 @@ class SmartEffectorEndstopWrapper: self.gcode.register_command("SET_SMART_EFFECTOR", self.cmd_SET_SMART_EFFECTOR, desc=self.cmd_SET_SMART_EFFECTOR_help) + self.gcode.register_command("CHANGE_PIN", + self.cmd_CHANGE_PIN, + desc=self.cmd_CHANGE_PIN_help) + + self.pin2 = config.get('pin2', None) + self.pin2_enable = 0 + if self.pin2: + self.pin2_enable = 1 + + def probe_prepare(self, hmove): toolhead = self.printer.lookup_object('toolhead') self.probe_wrapper.probe_prepare(hmove) @@ -146,6 +156,9 @@ class SmartEffectorEndstopWrapper: buf = [131, 131] self._send_command(buf) gcmd.respond_info('SmartEffector sensitivity was reset') + cmd_CHANGE_PIN_help = 'print pin' + def cmd_CHANGE_PIN(self, gcmd): + pass def load_config(config): smart_effector = SmartEffectorEndstopWrapper(config) diff --git a/klippy/extras/spi_temperature.py b/klippy/extras/spi_temperature.py index 3972072..1a45a62 100644 --- a/klippy/extras/spi_temperature.py +++ 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b/klippy/extras/tmc.py @@ -93,7 +93,7 @@ class TMCErrorCheck: self.mcu_tmc = mcu_tmc self.fields = mcu_tmc.get_fields() self.check_timer = None - self.last_drv_status = self.last_status = None + self.last_drv_status = self.last_drv_fields = None # Setup for GSTAT query reg_name = self.fields.lookup_register("drv_err") if reg_name is not None: @@ -109,9 +109,6 @@ class TMCErrorCheck: # TMC2130 driver quirks self.clear_gstat = False cs_actual_mask = self.fields.all_fields[reg_name]["cs_actual"] - # elif name_parts[0] == 'tmc2240': - # self.clear_gstat = False - # cs_actual_mask = self.fields.all_fields[reg_name]["cs_actual"] elif name_parts[0] == 'tmc2660': # TMC2660 driver quirks self.irun_field = "cs" @@ -125,6 +122,12 @@ class TMCErrorCheck: if f in err_fields: err_mask |= self.fields.all_fields[reg_name][f] self.drv_status_reg_info = [0, reg_name, mask, err_mask, cs_actual_mask] + # Setup for temperature query + self.adc_temp = None + self.adc_temp_reg = self.fields.lookup_register("adc_temp") + if self.adc_temp_reg is not None: + pheaters = self.printer.load_object(config, 'heaters') + # pheaters.register_monitor(config) def _query_register(self, reg_info, try_clear=False): last_value, reg_name, mask, err_mask, cs_actual_mask = reg_info cleared_flags = 0 @@ -158,17 +161,28 @@ class TMCErrorCheck: if count >= 3: fmt = self.fields.pretty_format(reg_name, val) raise self.printer.command_error("TMC '%s' reports error: %s" - % (self.stepper_name, fmt)) + % (self.stepper_name, fmt)) + if "uv_cp" in fmt: + try_clear = True if try_clear and val & err_mask: try_clear = False cleared_flags |= val & err_mask self.mcu_tmc.set_register(reg_name, val & err_mask) return cleared_flags + def _query_temperature(self): + try: + self.adc_temp = self.mcu_tmc.get_register(self.adc_temp_reg) + except self.printer.command_error as e: + # Ignore comms error for temperature + self.adc_temp = None + return def _do_periodic_check(self, eventtime): try: self._query_register(self.drv_status_reg_info) if self.gstat_reg_info is not None: self._query_register(self.gstat_reg_info) + if self.adc_temp_reg is not None: + self._query_temperature() except self.printer.command_error as e: self.printer.invoke_shutdown(str(e)) return self.printer.get_reactor().NEVER @@ -197,14 +211,16 @@ class TMCErrorCheck: return False def get_status(self, eventtime=None): if self.check_timer is None: - return {'drv_status': None} + return {'drv_status': None, 'temperature': None} + temp = None + if self.adc_temp is not None: + temp = round((self.adc_temp - 2038) / 7.7, 2) last_value, reg_name = self.drv_status_reg_info[:2] if last_value != self.last_drv_status: self.last_drv_status = last_value fields = self.fields.get_reg_fields(reg_name, last_value) - fields = {n: v for n, v in fields.items() if v} - self.last_status = {'drv_status': fields} - return self.last_status + self.last_drv_fields = {n: v for n, v in fields.items() if v} + return {'drv_status': self.last_drv_fields, 'temperature': temp} ###################################################################### @@ -248,7 +264,8 @@ class TMCCommandHelper: desc=self.cmd_SET_TMC_CURRENT_help) def _init_registers(self, print_time=None): # Send registers - for reg_name, val in self.fields.registers.items(): + for reg_name in list(self.fields.registers.keys()): + val = self.fields.registers[reg_name] # Val may change during loop self.mcu_tmc.set_register(reg_name, val, print_time) cmd_INIT_TMC_help = "Initialize TMC stepper driver registers" def cmd_INIT_TMC(self, gcmd): @@ -261,7 +278,18 @@ class TMCCommandHelper: reg_name = self.fields.lookup_register(field_name, None) if reg_name is None: raise gcmd.error("Unknown field name '%s'" % (field_name,)) - value = gcmd.get_int('VALUE') + value = gcmd.get_int('VALUE', None) + velocity = gcmd.get_float('VELOCITY', None, minval=0.) + tmc_frequency = self.mcu_tmc.get_tmc_frequency() + if tmc_frequency is None and velocity is not None: + raise gcmd.error("VELOCITY parameter not supported by this driver") + if (value is None) == (velocity is None): + raise gcmd.error("Specify either VALUE or VELOCITY") + if velocity is not None: + step_dist = self.stepper.get_step_dist() + mres = self.fields.get_field("mres") + value = TMCtstepHelper(step_dist, mres, tmc_frequency, + velocity) reg_val = self.fields.set_field(field_name, value) print_time = self.printer.lookup_object('toolhead').get_last_move_time() self.mcu_tmc.set_register(reg_name, reg_val, print_time) @@ -405,17 +433,32 @@ class TMCCommandHelper: cmd_DUMP_TMC_help = "Read and display TMC stepper driver registers" def cmd_DUMP_TMC(self, gcmd): logging.info("DUMP_TMC %s", self.name) - print_time = self.printer.lookup_object('toolhead').get_last_move_time() - gcmd.respond_info("========== Write-only registers ==========") - for reg_name, val in self.fields.registers.items(): - if reg_name not in self.read_registers: + reg_name = gcmd.get('REGISTER', None) + if reg_name is not None: + reg_name = reg_name.upper() + val = self.fields.registers.get(reg_name) + if (val is not None) and (reg_name not in self.read_registers): + # write-only register + gcmd.respond_info(self.fields.pretty_format(reg_name, val)) + elif reg_name in self.read_registers: + # readable register + val = self.mcu_tmc.get_register(reg_name) + if self.read_translate is not None: + reg_name, val = self.read_translate(reg_name, val) + gcmd.respond_info(self.fields.pretty_format(reg_name, val)) + else: + raise gcmd.error("Unknown register name '%s'" % (reg_name)) + else: + gcmd.respond_info("========== Write-only registers ==========") + for reg_name, val in self.fields.registers.items(): + if reg_name not in self.read_registers: + gcmd.respond_info(self.fields.pretty_format(reg_name, val)) + gcmd.respond_info("========== Queried registers ==========") + for reg_name in self.read_registers: + val = self.mcu_tmc.get_register(reg_name) + if self.read_translate is not None: + reg_name, val = self.read_translate(reg_name, val) gcmd.respond_info(self.fields.pretty_format(reg_name, val)) - gcmd.respond_info("========== Queried registers ==========") - for reg_name in self.read_registers: - val = self.mcu_tmc.get_register(reg_name) - if self.read_translate is not None: - reg_name, val = self.read_translate(reg_name, val) - gcmd.respond_info(self.fields.pretty_format(reg_name, val)) ###################################################################### @@ -440,7 +483,7 @@ class TMCVirtualPinHelper: self.diag_pin_field = None self.mcu_endstop = None self.en_pwm = False - self.pwmthrs = 0 + self.pwmthrs = self.coolthrs = 0 # Register virtual_endstop pin name_parts = config.get_name().split() ppins = self.printer.lookup_object("pins") @@ -455,13 +498,6 @@ class TMCVirtualPinHelper: if self.diag_pin is None: raise ppins.error("tmc virtual endstop requires diag pin config") # Setup for sensorless homing - reg = self.fields.lookup_register("en_pwm_mode", None) - if reg is None: - self.en_pwm = not self.fields.get_field("en_spreadcycle") - self.pwmthrs = self.fields.get_field("tpwmthrs") - else: - self.en_pwm = self.fields.get_field("en_pwm_mode") - self.pwmthrs = 0 self.printer.register_event_handler("homing:homing_move_begin", self.handle_homing_move_begin) self.printer.register_event_handler("homing:homing_move_end", @@ -471,21 +507,24 @@ class TMCVirtualPinHelper: def handle_homing_move_begin(self, hmove): if self.mcu_endstop not in hmove.get_mcu_endstops(): return + self.pwmthrs = self.fields.get_field("tpwmthrs") + self.coolthrs = self.fields.get_field("tcoolthrs") reg = self.fields.lookup_register("en_pwm_mode", None) if reg is None: - logging.info("##############################") # On "stallguard4" drivers, "stealthchop" must be enabled + self.en_pwm = not self.fields.get_field("en_spreadcycle") tp_val = self.fields.set_field("tpwmthrs", 0) self.mcu_tmc.set_register("TPWMTHRS", tp_val) val = self.fields.set_field("en_spreadcycle", 0) else: # On earlier drivers, "stealthchop" must be disabled - logging.info("******************************") + self.en_pwm = self.fields.get_field("en_pwm_mode") self.fields.set_field("en_pwm_mode", 0) val = self.fields.set_field(self.diag_pin_field, 1) self.mcu_tmc.set_register("GCONF", val) - tc_val = self.fields.set_field("tcoolthrs", 0xfffff) - self.mcu_tmc.set_register("TCOOLTHRS", tc_val) + if self.coolthrs == 0: + tc_val = self.fields.set_field("tcoolthrs", 0xfffff) + self.mcu_tmc.set_register("TCOOLTHRS", tc_val) def handle_homing_move_end(self, hmove): if self.mcu_endstop not in hmove.get_mcu_endstops(): return @@ -498,7 +537,7 @@ class TMCVirtualPinHelper: self.fields.set_field("en_pwm_mode", self.en_pwm) val = self.fields.set_field(self.diag_pin_field, 0) self.mcu_tmc.set_register("GCONF", val) - tc_val = self.fields.set_field("tcoolthrs", 0) + tc_val = self.fields.set_field("tcoolthrs", self.coolthrs) self.mcu_tmc.set_register("TCOOLTHRS", tc_val) @@ -506,10 +545,35 @@ class TMCVirtualPinHelper: # Config reading helpers ###################################################################### +# Helper to initialize the wave table from config or defaults +def TMCWaveTableHelper(config, mcu_tmc): + set_config_field = mcu_tmc.get_fields().set_config_field + set_config_field(config, "mslut0", 0xAAAAB554) + set_config_field(config, "mslut1", 0x4A9554AA) + set_config_field(config, "mslut2", 0x24492929) + set_config_field(config, "mslut3", 0x10104222) + set_config_field(config, "mslut4", 0xFBFFFFFF) + set_config_field(config, "mslut5", 0xB5BB777D) + set_config_field(config, "mslut6", 0x49295556) + set_config_field(config, "mslut7", 0x00404222) + set_config_field(config, "w0", 2) + set_config_field(config, "w1", 1) + set_config_field(config, "w2", 1) + set_config_field(config, "w3", 1) + set_config_field(config, "x1", 128) + set_config_field(config, "x2", 255) + set_config_field(config, "x3", 255) + set_config_field(config, "start_sin", 0) + set_config_field(config, "start_sin90", 247) + # Helper to configure and query the microstep settings def TMCMicrostepHelper(config, mcu_tmc): fields = mcu_tmc.get_fields() stepper_name = " ".join(config.get_name().split()[1:]) + if not config.has_section(stepper_name): + raise config.error( + "Could not find config section '[%s]' required by tmc driver" + % (stepper_name,)) stepper_config = ms_config = config.getsection(stepper_name) if (stepper_config.get('microsteps', None, note_valid=False) is None and config.get('microsteps', None, note_valid=False) is not None): @@ -520,41 +584,36 @@ def TMCMicrostepHelper(config, mcu_tmc): fields.set_field("mres", mres) fields.set_field("intpol", config.getboolean("interpolate", True)) -# Helper to configure "stealthchop" mode +# Helper for calculating TSTEP based values from velocity +def TMCtstepHelper(step_dist, mres, tmc_freq, velocity): + if velocity > 0.: + step_dist_256 = step_dist / (1 << mres) + threshold = int(tmc_freq * step_dist_256 / velocity + .5) + return max(0, min(0xfffff, threshold)) + else: + return 0xfffff + +# Helper to configure stealthChop-spreadCycle transition velocity def TMCStealthchopHelper(config, mcu_tmc, tmc_freq): fields = mcu_tmc.get_fields() en_pwm_mode = False - velocity = config.getfloat('stealthchop_threshold', 0., minval=0.) - if velocity: + velocity = config.getfloat('stealthchop_threshold', None, minval=0.) + tpwmthrs = 0xfffff + + if velocity is not None: + en_pwm_mode = True + stepper_name = " ".join(config.get_name().split()[1:]) sconfig = config.getsection(stepper_name) rotation_dist, steps_per_rotation = stepper.parse_step_distance(sconfig) step_dist = rotation_dist / steps_per_rotation - step_dist_256 = step_dist / (1 << fields.get_field("mres")) - threshold = int(tmc_freq * step_dist_256 / velocity + .5) - fields.set_field("tpwmthrs", max(0, min(0xfffff, threshold))) - en_pwm_mode = True + mres = fields.get_field("mres") + tpwmthrs = TMCtstepHelper(step_dist, mres, tmc_freq, velocity) + fields.set_field("tpwmthrs", tpwmthrs) + reg = fields.lookup_register("en_pwm_mode", None) if reg is not None: fields.set_field("en_pwm_mode", en_pwm_mode) else: # TMC2208 uses en_spreadCycle fields.set_field("en_spreadcycle", not en_pwm_mode) - -# Helper to configure "stealthchop" mode -def TMC2240StealthchopHelper(config, mcu_tmc, tmc_freq): - fields = mcu_tmc.get_fields() - en_pwm_mode = True - velocity = config.getfloat('stealthchop_threshold', 0., minval=0.) - if velocity: - stepper_name = " ".join(config.get_name().split()[1:]) - sconfig = config.getsection(stepper_name) - rotation_dist, steps_per_rotation = stepper.parse_step_distance(sconfig) - step_dist = rotation_dist / steps_per_rotation - step_dist_256 = step_dist / (1 << fields.get_field("mres")) - threshold = int(tmc_freq * step_dist_256 / velocity + .5) - fields.set_field("tpwmthrs", max(0, min(0xfffff, threshold))) - en_pwm_mode = False - reg = fields.lookup_register("en_pwm_mode", None) - if reg is not None: - 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z%R?gW??&+1VO`xw-PsY9$#)fR%6&Jw&K^(|(QI(tgF2np=|jp10JBGw98*$J@&P5% zSGEMhHtit6lP8}!@f~FN0g<5;|L;wP!yAv}B)}rLX3qU7ol2$k?-ThYAG;hgX(yRv zLH4K~EF7h)-v;POQ Cg1z -# -# This file may be distributed under the terms of the GNU GPLv3 license. -import math, logging -from . import bus, tmc - -TMC_FREQUENCY=13200000. - -Registers = { - "GCONF": 0x00, "GSTAT": 0x01, "IOIN": 0x04, "IHOLD_IRUN": 0x10, - "TPOWERDOWN": 0x11, "TSTEP": 0x12, "TPWMTHRS": 0x13, "TCOOLTHRS": 0x14, - "THIGH": 0x15, "XDIRECT": 0x2d, "MSLUT0": 0x60, "MSLUTSEL": 0x68, - "MSLUTSTART": 0x69, "MSCNT": 0x6a, "MSCURACT": 0x6b, "CHOPCONF": 0x6c, - "COOLCONF": 0x6d, "DCCTRL": 0x6e, "DRV_STATUS": 0x6f, "PWMCONF": 0x70, - "PWM_SCALE": 0x71, "ENCM_CTRL": 0x72, "LOST_STEPS": 0x73, -} - -ReadRegisters = [ - "GCONF", "GSTAT", "IOIN", "TSTEP", "XDIRECT", "MSCNT", "MSCURACT", - "CHOPCONF", "DRV_STATUS", "PWM_SCALE", "LOST_STEPS", -] - -Fields = {} -Fields["GCONF"] = { - "i_scale_analog": 1<<0, "internal_rsense": 1<<1, "en_pwm_mode": 1<<2, - "enc_commutation": 1<<3, "shaft": 1<<4, "diag0_error": 1<<5, - "diag0_otpw": 1<<6, "diag0_stall": 1<<7, "diag1_stall": 1<<8, - "diag1_index": 1<<9, "diag1_onstate": 1<<10, "diag1_steps_skipped": 1<<11, - "diag0_int_pushpull": 1<<12, "diag1_pushpull": 1<<13, - "small_hysteresis": 1<<14, "stop_enable": 1<<15, "direct_mode": 1<<16, - "test_mode": 1<<17 -} -Fields["GSTAT"] = { "reset": 1<<0, "drv_err": 1<<1, "uv_cp": 1<<2 } -Fields["IOIN"] = { - "step": 1<<0, "dir": 1<<1, "dcen_cfg4": 1<<2, "dcin_cfg5": 1<<3, - "drv_enn_cfg6": 1<<4, "dco": 1<<5, "version": 0xff << 24 -} -Fields["IHOLD_IRUN"] = { - "ihold": 0x1f << 0, "irun": 0x1f << 8, "iholddelay": 0x0f << 16 -} -Fields["TPOWERDOWN"] = { "tpowerdown": 0xff } -Fields["TSTEP"] = { "tstep": 0xfffff } -Fields["TPWMTHRS"] = { "tpwmthrs": 0xfffff } -Fields["TCOOLTHRS"] = { "tcoolthrs": 0xfffff } -Fields["THIGH"] = { "thigh": 0xfffff } -Fields["MSCNT"] = { "mscnt": 0x3ff } -Fields["MSCURACT"] = { "cur_a": 0x1ff, "cur_b": 0x1ff << 16 } -Fields["CHOPCONF"] = { - "toff": 0x0f, "hstrt": 0x07 << 4, "hend": 0x0f << 7, "fd3": 1<<11, - "disfdcc": 1<<12, "rndtf": 1<<13, "chm": 1<<14, "tbl": 0x03 << 15, - "vsense": 1<<17, "vhighfs": 1<<18, "vhighchm": 1<<19, "sync": 0x0f << 20, - "mres": 0x0f << 24, "intpol": 1<<28, "dedge": 1<<29, "diss2g": 1<<30 -} -Fields["COOLCONF"] = { - "semin": 0x0f, "seup": 0x03 << 5, "semax": 0x0f << 8, "sedn": 0x03 << 13, - "seimin": 1<<15, "sgt": 0x7f << 16, "sfilt": 1<<24 -} -Fields["DRV_STATUS"] = { - "sg_result": 0x3ff, "fsactive": 1<<15, "cs_actual": 0x1f << 16, - "stallguard": 1<<24, "ot": 1<<25, "otpw": 1<<26, "s2ga": 1<<27, - "s2gb": 1<<28, "ola": 1<<29, "olb": 1<<30, "stst": 1<<31 -} -Fields["PWMCONF"] = { - "pwm_ampl": 0xff, "pwm_grad": 0xff << 8, "pwm_freq": 0x03 << 16, - "pwm_autoscale": 1<<18, "pwm_symmetric": 1<<19, "freewheel": 0x03 << 20 -} -Fields["PWM_SCALE"] = { "pwm_scale": 0xff } -Fields["LOST_STEPS"] = { "lost_steps": 0xfffff } - -SignedFields = ["cur_a", "cur_b", "sgt"] - -FieldFormatters = { - "i_scale_analog": (lambda v: "1(ExtVREF)" if v else ""), - "shaft": (lambda v: "1(Reverse)" if v else ""), - "reset": (lambda v: "1(Reset)" if v else ""), - "drv_err": (lambda v: "1(ErrorShutdown!)" if v else ""), - "uv_cp": (lambda v: "1(Undervoltage!)" if v else ""), - "version": (lambda v: "%#x" % v), - "mres": (lambda v: "%d(%dusteps)" % (v, 0x100 >> v)), - "otpw": (lambda v: "1(OvertempWarning!)" if v else ""), - "ot": (lambda v: "1(OvertempError!)" if v else ""), - "s2ga": (lambda v: "1(ShortToGND_A!)" if v else ""), - "s2gb": (lambda v: "1(ShortToGND_B!)" if v else ""), - "ola": (lambda v: "1(OpenLoad_A!)" if v else ""), - "olb": (lambda v: "1(OpenLoad_B!)" if v else ""), - "cs_actual": (lambda v: ("%d" % v) if v else "0(Reset?)"), -} - - -###################################################################### -# TMC stepper current config helper -###################################################################### - -MAX_CURRENT = 2.000 - -class TMCCurrentHelper: - def __init__(self, config, mcu_tmc): - self.printer = config.get_printer() - self.name = config.get_name().split()[-1] - self.mcu_tmc = mcu_tmc - self.fields = mcu_tmc.get_fields() - run_current = config.getfloat('run_current', - above=0., maxval=MAX_CURRENT) - hold_current = config.getfloat('hold_current', MAX_CURRENT, - above=0., maxval=MAX_CURRENT) - self.req_hold_current = hold_current - self.sense_resistor = config.getfloat('sense_resistor', 0.110, above=0.) - vsense, irun, ihold = self._calc_current(run_current, hold_current) - self.fields.set_field("vsense", vsense) - self.fields.set_field("ihold", ihold) - self.fields.set_field("irun", irun) - def _calc_current_bits(self, current, vsense): - sense_resistor = self.sense_resistor + 0.020 - vref = 0.32 - if vsense: - vref = 0.18 - cs = int(32. * sense_resistor * current * math.sqrt(2.) / vref + .5) - 1 - return max(0, min(31, cs)) - def _calc_current_from_bits(self, cs, vsense): - sense_resistor = self.sense_resistor + 0.020 - vref = 0.32 - if vsense: - vref = 0.18 - return (cs + 1) * vref / (32. * sense_resistor * math.sqrt(2.)) - def _calc_current(self, run_current, hold_current): - vsense = True - irun = self._calc_current_bits(run_current, True) - if irun == 31: - cur = self._calc_current_from_bits(irun, True) - if cur < run_current: - irun2 = self._calc_current_bits(run_current, False) - cur2 = self._calc_current_from_bits(irun2, False) - if abs(run_current - cur2) < abs(run_current - cur): - vsense = False - irun = irun2 - ihold = self._calc_current_bits(min(hold_current, run_current), vsense) - return vsense, irun, ihold - def get_current(self): - irun = self.fields.get_field("irun") - ihold = self.fields.get_field("ihold") - vsense = self.fields.get_field("vsense") - run_current = self._calc_current_from_bits(irun, vsense) - hold_current = self._calc_current_from_bits(ihold, vsense) - return run_current, hold_current, self.req_hold_current, MAX_CURRENT - def set_current(self, run_current, hold_current, print_time): - self.req_hold_current = hold_current - vsense, irun, ihold = self._calc_current(run_current, hold_current) - if vsense != self.fields.get_field("vsense"): - val = self.fields.set_field("vsense", vsense) - self.mcu_tmc.set_register("CHOPCONF", val, print_time) - self.fields.set_field("ihold", ihold) - val = self.fields.set_field("irun", irun) - self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) - - -###################################################################### -# TMC2130 SPI -###################################################################### - -class MCU_TMC_SPI_chain: - def __init__(self, config, chain_len=1): - self.printer = config.get_printer() - self.chain_len = chain_len - self.mutex = self.printer.get_reactor().mutex() - share = None - if chain_len > 1: - share = "tmc_spi_cs" - self.spi = bus.MCU_SPI_from_config(config, 3, default_speed=4000000, - share_type=share) - self.taken_chain_positions = [] - def _build_cmd(self, data, chain_pos): - return ([0x00] * ((self.chain_len - chain_pos) * 5) + - data + [0x00] * ((chain_pos - 1) * 5)) - def reg_read(self, reg, chain_pos): - cmd = self._build_cmd([reg, 0x00, 0x00, 0x00, 0x00], chain_pos) - self.spi.spi_send(cmd) - if self.printer.get_start_args().get('debugoutput') is not None: - return 0 - params = self.spi.spi_transfer(cmd) - pr = bytearray(params['response']) - pr = pr[(self.chain_len - chain_pos) * 5 : - (self.chain_len - chain_pos + 1) * 5] - return (pr[1] << 24) | (pr[2] << 16) | (pr[3] << 8) | pr[4] - def reg_write(self, reg, val, chain_pos, print_time=None): - minclock = 0 - if print_time is not None: - minclock = self.spi.get_mcu().print_time_to_clock(print_time) - data = [(reg | 0x80) & 0xff, (val >> 24) & 0xff, (val >> 16) & 0xff, - (val >> 8) & 0xff, val & 0xff] - if self.printer.get_start_args().get('debugoutput') is not None: - self.spi.spi_send(self._build_cmd(data, chain_pos), minclock) - return val - write_cmd = self._build_cmd(data, chain_pos) - dummy_read = self._build_cmd([0x00, 0x00, 0x00, 0x00, 0x00], chain_pos) - params = self.spi.spi_transfer_with_preface(write_cmd, dummy_read, - minclock=minclock) - pr = bytearray(params['response']) - pr = pr[(self.chain_len - chain_pos) * 5 : - (self.chain_len - chain_pos + 1) * 5] - return (pr[1] << 24) | (pr[2] << 16) | (pr[3] << 8) | pr[4] - -# Helper to setup an spi daisy chain bus from settings in a config section -def lookup_tmc_spi_chain(config): - chain_len = config.getint('chain_length', None, minval=2) - if chain_len is None: - # Simple, non daisy chained SPI connection - return MCU_TMC_SPI_chain(config, 1), 1 - - # Shared SPI bus - lookup existing MCU_TMC_SPI_chain - ppins = config.get_printer().lookup_object("pins") - cs_pin_params = ppins.lookup_pin(config.get('cs_pin'), - share_type="tmc_spi_cs") - tmc_spi = cs_pin_params.get('class') - if tmc_spi is None: - tmc_spi = cs_pin_params['class'] = MCU_TMC_SPI_chain(config, chain_len) - if chain_len != tmc_spi.chain_len: - raise config.error("TMC SPI chain must have same length") - chain_pos = config.getint('chain_position', minval=1, maxval=chain_len) - if chain_pos in tmc_spi.taken_chain_positions: - raise config.error("TMC SPI chain can not have duplicate position") - tmc_spi.taken_chain_positions.append(chain_pos) - return tmc_spi, chain_pos - -# Helper code for working with TMC devices via SPI -class MCU_TMC_SPI: - def __init__(self, config, name_to_reg, fields): - self.printer = config.get_printer() - self.name = config.get_name().split()[-1] - self.tmc_spi, self.chain_pos = lookup_tmc_spi_chain(config) - self.mutex = self.tmc_spi.mutex - self.name_to_reg = name_to_reg - self.fields = fields - def get_fields(self): - return self.fields - def get_register(self, reg_name): - reg = self.name_to_reg[reg_name] - with self.mutex: - read = self.tmc_spi.reg_read(reg, self.chain_pos) - return read - def set_register(self, reg_name, val, print_time=None): - reg = self.name_to_reg[reg_name] - with self.mutex: - for retry in range(5): - v = self.tmc_spi.reg_write(reg, val, self.chain_pos, print_time) - if v == val: - return - raise self.printer.command_error( - "Unable to write tmc spi '%s' register %s" % (self.name, reg_name)) - - -###################################################################### -# TMC2130 printer object -###################################################################### - -class TMC2130: - def __init__(self, config): - # Setup mcu communication - self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = MCU_TMC_SPI(config, Registers, self.fields) - # Allow virtual pins to be created - tmc.TMCVirtualPinHelper(config, self.mcu_tmc) - # Register commands - current_helper = TMCCurrentHelper(config, self.mcu_tmc) - cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) - cmdhelper.setup_register_dump(ReadRegisters) - self.get_phase_offset = cmdhelper.get_phase_offset - self.get_status = cmdhelper.get_status - # Setup basic register values - tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - # Allow other registers to be set from the config - set_config_field = self.fields.set_config_field - set_config_field(config, "toff", 4) - set_config_field(config, "hstrt", 0) - set_config_field(config, "hend", 7) - set_config_field(config, "tbl", 1) - set_config_field(config, "iholddelay", 8) - set_config_field(config, "tpowerdown", 0) - set_config_field(config, "pwm_ampl", 128) - set_config_field(config, "pwm_grad", 4) - set_config_field(config, "pwm_freq", 1) - set_config_field(config, "pwm_autoscale", True) - set_config_field(config, "sgt", 0) - -def load_config_prefix(config): - return TMC2130(config) +# TMC2130 configuration +# +# Copyright (C) 2018-2019 Kevin O'Connor +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import math, logging +from . import bus, tmc + +TMC_FREQUENCY=13200000. + +Registers = { + "GCONF": 0x00, "GSTAT": 0x01, "IOIN": 0x04, "IHOLD_IRUN": 0x10, + "TPOWERDOWN": 0x11, "TSTEP": 0x12, "TPWMTHRS": 0x13, "TCOOLTHRS": 0x14, + "THIGH": 0x15, "XDIRECT": 0x2d, "MSLUT0": 0x60, "MSLUT1": 0x61, + "MSLUT2": 0x62, "MSLUT3": 0x63, "MSLUT4": 0x64, "MSLUT5": 0x65, + "MSLUT6": 0x66, "MSLUT7": 0x67, "MSLUTSEL": 0x68, "MSLUTSTART": 0x69, + "MSCNT": 0x6a, "MSCURACT": 0x6b, "CHOPCONF": 0x6c, "COOLCONF": 0x6d, + "DCCTRL": 0x6e, "DRV_STATUS": 0x6f, "PWMCONF": 0x70, "PWM_SCALE": 0x71, + "ENCM_CTRL": 0x72, "LOST_STEPS": 0x73, +} + +ReadRegisters = [ + "GCONF", "GSTAT", "IOIN", "TSTEP", "XDIRECT", "MSCNT", "MSCURACT", + "CHOPCONF", "DRV_STATUS", "PWM_SCALE", "LOST_STEPS", +] + +Fields = {} +Fields["GCONF"] = { + "i_scale_analog": 1<<0, "internal_rsense": 1<<1, "en_pwm_mode": 1<<2, + "enc_commutation": 1<<3, "shaft": 1<<4, "diag0_error": 1<<5, + "diag0_otpw": 1<<6, "diag0_stall": 1<<7, "diag1_stall": 1<<8, + "diag1_index": 1<<9, "diag1_onstate": 1<<10, "diag1_steps_skipped": 1<<11, + "diag0_int_pushpull": 1<<12, "diag1_pushpull": 1<<13, + "small_hysteresis": 1<<14, "stop_enable": 1<<15, "direct_mode": 1<<16, + "test_mode": 1<<17 +} +Fields["GSTAT"] = { "reset": 1<<0, "drv_err": 1<<1, "uv_cp": 1<<2 } +Fields["IOIN"] = { + "step": 1<<0, "dir": 1<<1, "dcen_cfg4": 1<<2, "dcin_cfg5": 1<<3, + "drv_enn_cfg6": 1<<4, "dco": 1<<5, "version": 0xff << 24 +} +Fields["IHOLD_IRUN"] = { + "ihold": 0x1f << 0, "irun": 0x1f << 8, "iholddelay": 0x0f << 16 +} +Fields["TPOWERDOWN"] = { "tpowerdown": 0xff } +Fields["TSTEP"] = { "tstep": 0xfffff } +Fields["TPWMTHRS"] = { "tpwmthrs": 0xfffff } +Fields["TCOOLTHRS"] = { "tcoolthrs": 0xfffff } +Fields["THIGH"] = { "thigh": 0xfffff } +Fields["MSLUT0"] = { "mslut0": 0xffffffff } +Fields["MSLUT1"] = { "mslut1": 0xffffffff } +Fields["MSLUT2"] = { "mslut2": 0xffffffff } +Fields["MSLUT3"] = { "mslut3": 0xffffffff } +Fields["MSLUT4"] = { "mslut4": 0xffffffff } +Fields["MSLUT5"] = { "mslut5": 0xffffffff } +Fields["MSLUT6"] = { "mslut6": 0xffffffff } +Fields["MSLUT7"] = { "mslut7": 0xffffffff } +Fields["MSLUTSEL"] = { + "x3": 0xFF << 24, + "x2": 0xFF << 16, + "x1": 0xFF << 8, + "w3": 0x03 << 6, + "w2": 0x03 << 4, + "w1": 0x03 << 2, + "w0": 0x03 << 0, +} +Fields["MSLUTSTART"] = { + "start_sin": 0xFF << 0, + "start_sin90": 0xFF << 16, +} +Fields["MSCNT"] = { "mscnt": 0x3ff } +Fields["MSCURACT"] = { "cur_a": 0x1ff, "cur_b": 0x1ff << 16 } +Fields["CHOPCONF"] = { + "toff": 0x0f, "hstrt": 0x07 << 4, "hend": 0x0f << 7, "fd3": 1<<11, + "disfdcc": 1<<12, "rndtf": 1<<13, "chm": 1<<14, "tbl": 0x03 << 15, + "vsense": 1<<17, "vhighfs": 1<<18, "vhighchm": 1<<19, "sync": 0x0f << 20, + "mres": 0x0f << 24, "intpol": 1<<28, "dedge": 1<<29, "diss2g": 1<<30 +} +Fields["COOLCONF"] = { + "semin": 0x0f, "seup": 0x03 << 5, "semax": 0x0f << 8, "sedn": 0x03 << 13, + "seimin": 1<<15, "sgt": 0x7f << 16, "sfilt": 1<<24 +} +Fields["DRV_STATUS"] = { + "sg_result": 0x3ff, "fsactive": 1<<15, "cs_actual": 0x1f << 16, + "stallguard": 1<<24, "ot": 1<<25, "otpw": 1<<26, "s2ga": 1<<27, + "s2gb": 1<<28, "ola": 1<<29, "olb": 1<<30, "stst": 1<<31 +} +Fields["PWMCONF"] = { + "pwm_ampl": 0xff, "pwm_grad": 0xff << 8, "pwm_freq": 0x03 << 16, + "pwm_autoscale": 1<<18, "pwm_symmetric": 1<<19, "freewheel": 0x03 << 20 +} +Fields["PWM_SCALE"] = { "pwm_scale": 0xff } +Fields["LOST_STEPS"] = { "lost_steps": 0xfffff } + +SignedFields = ["cur_a", "cur_b", "sgt"] + +FieldFormatters = { + "i_scale_analog": (lambda v: "1(ExtVREF)" if v else ""), + "shaft": (lambda v: "1(Reverse)" if v else ""), + "reset": (lambda v: "1(Reset)" if v else ""), + "drv_err": (lambda v: "1(ErrorShutdown!)" if v else ""), + "uv_cp": (lambda v: "1(Undervoltage!)" if v else ""), + "version": (lambda v: "%#x" % v), + "mres": (lambda v: "%d(%dusteps)" % (v, 0x100 >> v)), + "otpw": (lambda v: "1(OvertempWarning!)" if v else ""), + "ot": (lambda v: "1(OvertempError!)" if v else ""), + "s2ga": (lambda v: "1(ShortToGND_A!)" if v else ""), + "s2gb": (lambda v: "1(ShortToGND_B!)" if v else ""), + "ola": (lambda v: "1(OpenLoad_A!)" if v else ""), + "olb": (lambda v: "1(OpenLoad_B!)" if v else ""), + "cs_actual": (lambda v: ("%d" % v) if v else "0(Reset?)"), +} + + +###################################################################### +# TMC stepper current config helper +###################################################################### + +MAX_CURRENT = 2.000 + +class TMCCurrentHelper: + def __init__(self, config, mcu_tmc): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.mcu_tmc = mcu_tmc + self.fields = mcu_tmc.get_fields() + run_current = config.getfloat('run_current', + above=0., maxval=MAX_CURRENT) + hold_current = config.getfloat('hold_current', MAX_CURRENT, + above=0., maxval=MAX_CURRENT) + self.req_hold_current = hold_current + self.sense_resistor = config.getfloat('sense_resistor', 0.110, above=0.) + vsense, irun, ihold = self._calc_current(run_current, hold_current) + self.fields.set_field("vsense", vsense) + self.fields.set_field("ihold", ihold) + self.fields.set_field("irun", irun) + def _calc_current_bits(self, current, vsense): + sense_resistor = self.sense_resistor + 0.020 + vref = 0.32 + if vsense: + vref = 0.18 + cs = int(32. * sense_resistor * current * math.sqrt(2.) / vref + .5) - 1 + return max(0, min(31, cs)) + def _calc_current_from_bits(self, cs, vsense): + sense_resistor = self.sense_resistor + 0.020 + vref = 0.32 + if vsense: + vref = 0.18 + return (cs + 1) * vref / (32. * sense_resistor * math.sqrt(2.)) + def _calc_current(self, run_current, hold_current): + vsense = True + irun = self._calc_current_bits(run_current, True) + if irun == 31: + cur = self._calc_current_from_bits(irun, True) + if cur < run_current: + irun2 = self._calc_current_bits(run_current, False) + cur2 = self._calc_current_from_bits(irun2, False) + if abs(run_current - cur2) < abs(run_current - cur): + vsense = False + irun = irun2 + ihold = self._calc_current_bits(min(hold_current, run_current), vsense) + return vsense, irun, ihold + def get_current(self): + irun = self.fields.get_field("irun") + ihold = self.fields.get_field("ihold") + vsense = self.fields.get_field("vsense") + run_current = self._calc_current_from_bits(irun, vsense) + hold_current = self._calc_current_from_bits(ihold, vsense) + return run_current, hold_current, self.req_hold_current, MAX_CURRENT + def set_current(self, run_current, hold_current, print_time): + self.req_hold_current = hold_current + vsense, irun, ihold = self._calc_current(run_current, hold_current) + if vsense != self.fields.get_field("vsense"): + val = self.fields.set_field("vsense", vsense) + self.mcu_tmc.set_register("CHOPCONF", val, print_time) + self.fields.set_field("ihold", ihold) + val = self.fields.set_field("irun", irun) + self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) + + +###################################################################### +# TMC2130 SPI +###################################################################### + +class MCU_TMC_SPI_chain: + def __init__(self, config, chain_len=1): + self.printer = config.get_printer() + self.chain_len = chain_len + self.mutex = self.printer.get_reactor().mutex() + share = None + if chain_len > 1: + share = "tmc_spi_cs" + self.spi = bus.MCU_SPI_from_config(config, 3, default_speed=4000000, + share_type=share) + self.taken_chain_positions = [] + def _build_cmd(self, data, chain_pos): + return ([0x00] * ((self.chain_len - chain_pos) * 5) + + data + [0x00] * ((chain_pos - 1) * 5)) + def reg_read(self, reg, chain_pos): + cmd = self._build_cmd([reg, 0x00, 0x00, 0x00, 0x00], chain_pos) + self.spi.spi_send(cmd) + if self.printer.get_start_args().get('debugoutput') is not None: + return 0 + params = self.spi.spi_transfer(cmd) + pr = bytearray(params['response']) + pr = pr[(self.chain_len - chain_pos) * 5 : + (self.chain_len - chain_pos + 1) * 5] + return (pr[1] << 24) | (pr[2] << 16) | (pr[3] << 8) | pr[4] + def reg_write(self, reg, val, chain_pos, print_time=None): + minclock = 0 + if print_time is not None: + minclock = self.spi.get_mcu().print_time_to_clock(print_time) + data = [(reg | 0x80) & 0xff, (val >> 24) & 0xff, (val >> 16) & 0xff, + (val >> 8) & 0xff, val & 0xff] + if self.printer.get_start_args().get('debugoutput') is not None: + self.spi.spi_send(self._build_cmd(data, chain_pos), minclock) + return val + write_cmd = self._build_cmd(data, chain_pos) + dummy_read = self._build_cmd([0x00, 0x00, 0x00, 0x00, 0x00], chain_pos) + params = self.spi.spi_transfer_with_preface(write_cmd, dummy_read, + minclock=minclock) + pr = bytearray(params['response']) + pr = pr[(self.chain_len - chain_pos) * 5 : + (self.chain_len - chain_pos + 1) * 5] + return (pr[1] << 24) | (pr[2] << 16) | (pr[3] << 8) | pr[4] + +# Helper to setup an spi daisy chain bus from settings in a config section +def lookup_tmc_spi_chain(config): + chain_len = config.getint('chain_length', None, minval=2) + if chain_len is None: + # Simple, non daisy chained SPI connection + return MCU_TMC_SPI_chain(config, 1), 1 + + # Shared SPI bus - lookup existing MCU_TMC_SPI_chain + ppins = config.get_printer().lookup_object("pins") + cs_pin_params = ppins.lookup_pin(config.get('cs_pin'), + share_type="tmc_spi_cs") + tmc_spi = cs_pin_params.get('class') + if tmc_spi is None: + tmc_spi = cs_pin_params['class'] = MCU_TMC_SPI_chain(config, chain_len) + if chain_len != tmc_spi.chain_len: + raise config.error("TMC SPI chain must have same length") + chain_pos = config.getint('chain_position', minval=1, maxval=chain_len) + if chain_pos in tmc_spi.taken_chain_positions: + raise config.error("TMC SPI chain can not have duplicate position") + tmc_spi.taken_chain_positions.append(chain_pos) + return tmc_spi, chain_pos + +# Helper code for working with TMC devices via SPI +class MCU_TMC_SPI: + def __init__(self, config, name_to_reg, fields, tmc_frequency): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.tmc_spi, self.chain_pos = lookup_tmc_spi_chain(config) + self.mutex = self.tmc_spi.mutex + self.name_to_reg = name_to_reg + self.fields = fields + self.tmc_frequency = tmc_frequency + def get_fields(self): + return self.fields + def get_register(self, reg_name): + reg = self.name_to_reg[reg_name] + with self.mutex: + read = self.tmc_spi.reg_read(reg, self.chain_pos) + return read + def set_register(self, reg_name, val, print_time=None): + reg = self.name_to_reg[reg_name] + with self.mutex: + for retry in range(5): + v = self.tmc_spi.reg_write(reg, val, self.chain_pos, print_time) + if v == val: + return + raise self.printer.command_error( + "Unable to write tmc spi '%s' register %s" % (self.name, reg_name)) + def get_tmc_frequency(self): + return self.tmc_frequency + + +###################################################################### +# TMC2130 printer object +###################################################################### + +class TMC2130: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) + self.mcu_tmc = MCU_TMC_SPI(config, Registers, self.fields, + TMC_FREQUENCY) + # Allow virtual pins to be created + tmc.TMCVirtualPinHelper(config, self.mcu_tmc) + # Register commands + current_helper = TMCCurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + # Setup basic register values + tmc.TMCWaveTableHelper(config, self.mcu_tmc) + tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) + # Allow other registers to be set from the config + set_config_field = self.fields.set_config_field + # CHOPCONF + set_config_field(config, "toff", 4) + set_config_field(config, "hstrt", 0) + set_config_field(config, "hend", 7) + set_config_field(config, "tbl", 1) + # COOLCONF + set_config_field(config, "sgt", 0) + # IHOLDIRUN + set_config_field(config, "iholddelay", 8) + # PWMCONF + set_config_field(config, "pwm_ampl", 128) + set_config_field(config, "pwm_grad", 4) + set_config_field(config, "pwm_freq", 1) + set_config_field(config, "pwm_autoscale", True) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 0) + +def load_config_prefix(config): + return TMC2130(config) diff --git a/klippy/extras/tmc2130.pyc b/klippy/extras/tmc2130.pyc deleted file mode 100644 index 250e2ec54e3d17b0542179da8841d0620184fc3a..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 14134 zcmcIr37lP5S^w^PGn1LgOt#4~>5@!nV_&EtOKFS#O14ST1d=!DeUm25uX_9DojdQ{ z%-eGBeUnU0AZ=0+L{TVEC{jzomc=Tvs8|$11=&Qc6jYG1xFL$gx}x>}|IWSdO%lrQ zmub_8VX;%)dvPj!hH{Bxu#a-^MhGXrXVZkQ(|rb{g1`C zh(0Z*V2kIW7z_H0m~qfQE9M}g&xyGe(dWe+Li8tM4kP-4nA;HjshHbs(>~ktpNaWN z(EnVFhv;!Jci7_jD8`;25mU5;K}(nrQ?i7GZGy3c#chIb2}5ndq$Mn~gtC~5C9DPk zfC$WXAu2^n0pZYqnMwzP1mC7d@)$vt3dy@n4dxPPhwt;=sRLwgXo{d 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tmc2130 - -TMC_FREQUENCY=12000000. - -Registers = { - "GCONF": 0x00, "GSTAT": 0x01, "IFCNT": 0x02, "SLAVECONF": 0x03, - "OTP_PROG": 0x04, "OTP_READ": 0x05, "IOIN": 0x06, "FACTORY_CONF": 0x07, - "IHOLD_IRUN": 0x10, "TPOWERDOWN": 0x11, "TSTEP": 0x12, "TPWMTHRS": 0x13, - "VACTUAL": 0x22, "MSCNT": 0x6a, "MSCURACT": 0x6b, "CHOPCONF": 0x6c, - "DRV_STATUS": 0x6f, "PWMCONF": 0x70, "PWM_SCALE": 0x71, "PWM_AUTO": 0x72 -} - -ReadRegisters = [ - "GCONF", "GSTAT", "IFCNT", "OTP_READ", "IOIN", "FACTORY_CONF", "TSTEP", - "MSCNT", "MSCURACT", "CHOPCONF", "DRV_STATUS", - "PWMCONF", "PWM_SCALE", "PWM_AUTO" -] - -Fields = {} - -Fields["GCONF"] = { - "i_scale_analog": 0x01, - "internal_rsense": 0x01 << 1, - "en_spreadcycle": 0x01 << 2, - "shaft": 0x01 << 3, - "index_otpw": 0x01 << 4, - "index_step": 0x01 << 5, - "pdn_disable": 0x01 << 6, - "mstep_reg_select": 0x01 << 7, - "multistep_filt": 0x01 << 8, - "test_mode": 0x01 << 9 -} -Fields["GSTAT"] = { - "reset": 0x01, - "drv_err": 0x01 << 1, - "uv_cp": 0x01 << 2 -} -Fields["IFCNT"] = { - "ifcnt": 0xff -} -Fields["SLAVECONF"] = { - "senddelay": 0x0f << 8 -} -Fields["OTP_PROG"] = { - "otpbit": 0x07, - "otpbyte": 0x03 << 4, - "otpmagic": 0xff << 8 -} -Fields["OTP_READ"] = { - "otp_fclktrim": 0x1f, - "otp_ottrim": 0x01 << 5, - "otp_internalrsense": 0x01 << 6, - "otp_tbl": 0x01 << 7, - "otp_pwm_grad": 0x0f << 8, - "otp_pwm_autograd": 0x01 << 12, - "otp_tpwmthrs": 0x07 << 13, - "otp_pwm_ofs": 0x01 << 16, - "otp_pwm_reg": 0x01 << 17, - "otp_pwm_freq": 0x01 << 18, - "otp_iholddelay": 0x03 << 19, - "otp_ihold": 0x03 << 21, - "otp_en_spreadcycle": 0x01 << 23 -} -# IOIN mapping depends on the driver type (SEL_A field) -# TMC222x (SEL_A == 0) -Fields["IOIN@TMC222x"] = { - "pdn_uart": 0x01 << 1, - "spread": 0x01 << 2, - "dir": 0x01 << 3, - "enn": 0x01 << 4, - "step": 0x01 << 5, - "ms1": 0x01 << 6, - "ms2": 0x01 << 7, - "sel_a": 0x01 << 8, - "version": 0xff << 24 -} -# TMC220x (SEL_A == 1) -Fields["IOIN@TMC220x"] = { - "enn": 0x01, - "ms1": 0x01 << 2, - "ms2": 0x01 << 3, - "diag": 0x01 << 4, - "pdn_uart": 0x01 << 6, - "step": 0x01 << 7, - "sel_a": 0x01 << 8, - "dir": 0x01 << 9, - "version": 0xff << 24, -} -Fields["FACTORY_CONF"] = { - "fclktrim": 0x1f, - "ottrim": 0x03 << 8 -} -Fields["IHOLD_IRUN"] = { - "ihold": 0x1f, - "irun": 0x1f << 8, - "iholddelay": 0x0f << 16 -} -Fields["TPOWERDOWN"] = { - "tpowerdown": 0xff -} -Fields["TSTEP"] = { - "tstep": 0xfffff -} -Fields["TPWMTHRS"] = { - "tpwmthrs": 0xfffff -} -Fields["VACTUAL"] = { - "vactual": 0xffffff -} -Fields["MSCNT"] = { - "mscnt": 0x3ff -} -Fields["MSCURACT"] = { - "cur_a": 0x1ff, - "cur_b": 0x1ff << 16 -} -Fields["CHOPCONF"] = { - "toff": 0x0f, - "hstrt": 0x07 << 4, - "hend": 0x0f << 7, - "tbl": 0x03 << 15, - "vsense": 0x01 << 17, - "mres": 0x0f << 24, - "intpol": 0x01 << 28, - "dedge": 0x01 << 29, - "diss2g": 0x01 << 30, - "diss2vs": 0x01 << 31 -} -Fields["DRV_STATUS"] = { - "otpw": 0x01, - "ot": 0x01 << 1, - "s2ga": 0x01 << 2, - "s2gb": 0x01 << 3, - "s2vsa": 0x01 << 4, - "s2vsb": 0x01 << 5, - "ola": 0x01 << 6, - "olb": 0x01 << 7, - "t120": 0x01 << 8, - "t143": 0x01 << 9, - "t150": 0x01 << 10, - "t157": 0x01 << 11, - "cs_actual": 0x1f << 16, - "stealth": 0x01 << 30, - "stst": 0x01 << 31 -} -Fields["PWMCONF"] = { - "pwm_ofs": 0xff, - "pwm_grad": 0xff << 8, - "pwm_freq": 0x03 << 16, - "pwm_autoscale": 0x01 << 18, - "pwm_autograd": 0x01 << 19, - "freewheel": 0x03 << 20, - "pwm_reg": 0xf << 24, - "pwm_lim": 0xf << 28 -} -Fields["PWM_SCALE"] = { - "pwm_scale_sum": 0xff, - "pwm_scale_auto": 0x1ff << 16 -} -Fields["PWM_AUTO"] = { - "pwm_ofs_auto": 0xff, - "pwm_grad_auto": 0xff << 16 -} - -SignedFields = ["cur_a", "cur_b", "pwm_scale_auto"] - -FieldFormatters = dict(tmc2130.FieldFormatters) -FieldFormatters.update({ - "sel_a": (lambda v: "%d(%s)" % (v, ["TMC222x", "TMC220x"][v])), - "s2vsa": (lambda v: "1(LowSideShort_A!)" if v else ""), - "s2vsb": (lambda v: "1(LowSideShort_B!)" if v else ""), -}) - - -###################################################################### -# TMC2208 printer object -###################################################################### - -class TMC2208: - def __init__(self, config): - # Setup mcu communication - self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields) - self.fields.set_field("pdn_disable", True) - # Register commands - current_helper = tmc2130.TMCCurrentHelper(config, self.mcu_tmc) - cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) - cmdhelper.setup_register_dump(ReadRegisters, self.read_translate) - self.get_phase_offset = cmdhelper.get_phase_offset - self.get_status = cmdhelper.get_status - # Setup basic register values - self.fields.set_field("mstep_reg_select", True) - self.fields.set_field("multistep_filt", True) - tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - # Allow other registers to be set from the config - set_config_field = self.fields.set_config_field - set_config_field(config, "toff", 3) - set_config_field(config, "hstrt", 5) - set_config_field(config, "hend", 0) - set_config_field(config, "tbl", 2) - set_config_field(config, "iholddelay", 8) - set_config_field(config, "tpowerdown", 20) - set_config_field(config, "pwm_ofs", 36) - set_config_field(config, "pwm_grad", 14) - set_config_field(config, "pwm_freq", 1) - set_config_field(config, "pwm_autoscale", True) - set_config_field(config, "pwm_autograd", True) - set_config_field(config, "pwm_reg", 8) - set_config_field(config, "pwm_lim", 12) - def read_translate(self, reg_name, val): - if reg_name == "IOIN": - drv_type = self.fields.get_field("sel_a", val) - reg_name = "IOIN@TMC220x" if drv_type else "IOIN@TMC222x" - return reg_name, val - -def load_config_prefix(config): - return TMC2208(config) +# TMC2208 UART communication and configuration +# +# Copyright (C) 2018-2019 Kevin O'Connor +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import logging +from . import tmc, tmc_uart, tmc2130 + +TMC_FREQUENCY=12000000. + +Registers = { + "GCONF": 0x00, "GSTAT": 0x01, "IFCNT": 0x02, "SLAVECONF": 0x03, + "OTP_PROG": 0x04, "OTP_READ": 0x05, "IOIN": 0x06, "FACTORY_CONF": 0x07, + "IHOLD_IRUN": 0x10, "TPOWERDOWN": 0x11, "TSTEP": 0x12, "TPWMTHRS": 0x13, + "VACTUAL": 0x22, "MSCNT": 0x6a, "MSCURACT": 0x6b, "CHOPCONF": 0x6c, + "DRV_STATUS": 0x6f, "PWMCONF": 0x70, "PWM_SCALE": 0x71, "PWM_AUTO": 0x72 +} + +ReadRegisters = [ + "GCONF", "GSTAT", "IFCNT", "OTP_READ", "IOIN", "FACTORY_CONF", "TSTEP", + "MSCNT", "MSCURACT", "CHOPCONF", "DRV_STATUS", + "PWMCONF", "PWM_SCALE", "PWM_AUTO" +] + +Fields = {} + +Fields["GCONF"] = { + "i_scale_analog": 0x01, + "internal_rsense": 0x01 << 1, + "en_spreadcycle": 0x01 << 2, + "shaft": 0x01 << 3, + "index_otpw": 0x01 << 4, + "index_step": 0x01 << 5, + "pdn_disable": 0x01 << 6, + "mstep_reg_select": 0x01 << 7, + "multistep_filt": 0x01 << 8, + "test_mode": 0x01 << 9 +} +Fields["GSTAT"] = { + "reset": 0x01, + "drv_err": 0x01 << 1, + "uv_cp": 0x01 << 2 +} +Fields["IFCNT"] = { + "ifcnt": 0xff +} +Fields["SLAVECONF"] = { + "senddelay": 0x0f << 8 +} +Fields["OTP_PROG"] = { + "otpbit": 0x07, + "otpbyte": 0x03 << 4, + "otpmagic": 0xff << 8 +} +Fields["OTP_READ"] = { + "otp_fclktrim": 0x1f, + "otp_ottrim": 0x01 << 5, + "otp_internalrsense": 0x01 << 6, + "otp_tbl": 0x01 << 7, + "otp_pwm_grad": 0x0f << 8, + "otp_pwm_autograd": 0x01 << 12, + "otp_tpwmthrs": 0x07 << 13, + "otp_pwm_ofs": 0x01 << 16, + "otp_pwm_reg": 0x01 << 17, + "otp_pwm_freq": 0x01 << 18, + "otp_iholddelay": 0x03 << 19, + "otp_ihold": 0x03 << 21, + "otp_en_spreadcycle": 0x01 << 23 +} +# IOIN mapping depends on the driver type (SEL_A field) +# TMC222x (SEL_A == 0) +Fields["IOIN@TMC222x"] = { + "pdn_uart": 0x01 << 1, + "spread": 0x01 << 2, + "dir": 0x01 << 3, + "enn": 0x01 << 4, + "step": 0x01 << 5, + "ms1": 0x01 << 6, + "ms2": 0x01 << 7, + "sel_a": 0x01 << 8, + "version": 0xff << 24 +} +# TMC220x (SEL_A == 1) +Fields["IOIN@TMC220x"] = { + "enn": 0x01, + "ms1": 0x01 << 2, + "ms2": 0x01 << 3, + "diag": 0x01 << 4, + "pdn_uart": 0x01 << 6, + "step": 0x01 << 7, + "sel_a": 0x01 << 8, + "dir": 0x01 << 9, + "version": 0xff << 24, +} +Fields["FACTORY_CONF"] = { + "fclktrim": 0x1f, + "ottrim": 0x03 << 8 +} +Fields["IHOLD_IRUN"] = { + "ihold": 0x1f, + "irun": 0x1f << 8, + "iholddelay": 0x0f << 16 +} +Fields["TPOWERDOWN"] = { + "tpowerdown": 0xff +} +Fields["TSTEP"] = { + "tstep": 0xfffff +} +Fields["TPWMTHRS"] = { + "tpwmthrs": 0xfffff +} +Fields["VACTUAL"] = { + "vactual": 0xffffff +} +Fields["MSCNT"] = { + "mscnt": 0x3ff +} +Fields["MSCURACT"] = { + "cur_a": 0x1ff, + "cur_b": 0x1ff << 16 +} +Fields["CHOPCONF"] = { + "toff": 0x0f, + "hstrt": 0x07 << 4, + "hend": 0x0f << 7, + "tbl": 0x03 << 15, + "vsense": 0x01 << 17, + "mres": 0x0f << 24, + "intpol": 0x01 << 28, + "dedge": 0x01 << 29, + "diss2g": 0x01 << 30, + "diss2vs": 0x01 << 31 +} +Fields["DRV_STATUS"] = { + "otpw": 0x01, + "ot": 0x01 << 1, + "s2ga": 0x01 << 2, + "s2gb": 0x01 << 3, + "s2vsa": 0x01 << 4, + "s2vsb": 0x01 << 5, + "ola": 0x01 << 6, + "olb": 0x01 << 7, + "t120": 0x01 << 8, + "t143": 0x01 << 9, + "t150": 0x01 << 10, + "t157": 0x01 << 11, + "cs_actual": 0x1f << 16, + "stealth": 0x01 << 30, + "stst": 0x01 << 31 +} +Fields["PWMCONF"] = { + "pwm_ofs": 0xff, + "pwm_grad": 0xff << 8, + "pwm_freq": 0x03 << 16, + "pwm_autoscale": 0x01 << 18, + "pwm_autograd": 0x01 << 19, + "freewheel": 0x03 << 20, + "pwm_reg": 0xf << 24, + "pwm_lim": 0xf << 28 +} +Fields["PWM_SCALE"] = { + "pwm_scale_sum": 0xff, + "pwm_scale_auto": 0x1ff << 16 +} +Fields["PWM_AUTO"] = { + "pwm_ofs_auto": 0xff, + "pwm_grad_auto": 0xff << 16 +} + +SignedFields = ["cur_a", "cur_b", "pwm_scale_auto"] + +FieldFormatters = dict(tmc2130.FieldFormatters) +FieldFormatters.update({ + "sel_a": (lambda v: "%d(%s)" % (v, ["TMC222x", "TMC220x"][v])), + "s2vsa": (lambda v: "1(ShortToSupply_A!)" if v else ""), + "s2vsb": (lambda v: "1(ShortToSupply_B!)" if v else ""), +}) + + +###################################################################### +# TMC2208 printer object +###################################################################### + +class TMC2208: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) + self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 0, + TMC_FREQUENCY) + self.fields.set_field("pdn_disable", True) + # Register commands + current_helper = tmc2130.TMCCurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters, self.read_translate) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + # Setup basic register values + self.fields.set_field("mstep_reg_select", True) + tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) + # Allow other registers to be set from the config + set_config_field = self.fields.set_config_field + # GCONF + set_config_field(config, "multistep_filt", True) + # CHOPCONF + set_config_field(config, "toff", 3) + set_config_field(config, "hstrt", 5) + set_config_field(config, "hend", 0) + set_config_field(config, "tbl", 2) + # IHOLDIRUN + set_config_field(config, "iholddelay", 8) + # PWMCONF + set_config_field(config, "pwm_ofs", 36) + set_config_field(config, "pwm_grad", 14) + set_config_field(config, "pwm_freq", 1) + set_config_field(config, "pwm_autoscale", True) + set_config_field(config, "pwm_autograd", True) + set_config_field(config, "pwm_reg", 8) + set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 20) + def read_translate(self, reg_name, val): + if reg_name == "IOIN": + drv_type = self.fields.get_field("sel_a", val) + reg_name = "IOIN@TMC220x" if drv_type else "IOIN@TMC222x" + return reg_name, val + +def load_config_prefix(config): + return TMC2208(config) diff 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terms of the GNU GPLv3 license. -from . import tmc2208, tmc2130, tmc, tmc_uart - -TMC_FREQUENCY=12000000. - -Registers = dict(tmc2208.Registers) -Registers.update({ - "TCOOLTHRS": 0x14, - "COOLCONF": 0x42, - "SGTHRS": 0x40, - "SG_RESULT": 0x41 -}) - -ReadRegisters = tmc2208.ReadRegisters + ["SG_RESULT"] - -Fields = dict(tmc2208.Fields) -Fields["COOLCONF"] = { - "semin": 0x0F << 0, - "seup": 0x03 << 5, - "semax": 0x0F << 8, - "sedn": 0x03 << 13, - "seimin": 0x01 << 15 -} -Fields["IOIN"] = { - "enn": 0x01 << 0, - "ms1": 0x01 << 2, - "ms2": 0x01 << 3, - "diag": 0x01 << 4, - "pdn_uart": 0x01 << 6, - "step": 0x01 << 7, - "spread_en": 0x01 << 8, - "dir": 0x01 << 9, - "version": 0xff << 24 -} -Fields["SGTHRS"] = { - "sgthrs": 0xFF << 0 -} -Fields["SG_RESULT"] = { - "sg_result": 0x3FF << 0 -} -Fields["TCOOLTHRS"] = { - "tcoolthrs": 0xfffff -} - -FieldFormatters = dict(tmc2208.FieldFormatters) - - -###################################################################### -# TMC2209 printer object -###################################################################### - -class TMC2209: - def __init__(self, config): - # Setup mcu communication - self.fields = tmc.FieldHelper(Fields, tmc2208.SignedFields, - FieldFormatters) - self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 3) - # Setup fields for UART - self.fields.set_field("pdn_disable", True) - self.fields.set_field("senddelay", 2) # Avoid tx errors on shared uart - # Allow virtual pins to be created - tmc.TMCVirtualPinHelper(config, self.mcu_tmc) - # Register commands - current_helper = tmc2130.TMCCurrentHelper(config, self.mcu_tmc) - cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) - cmdhelper.setup_register_dump(ReadRegisters) - self.get_phase_offset = cmdhelper.get_phase_offset - self.get_status = cmdhelper.get_status - # Setup basic register values - self.fields.set_field("pdn_disable", True) - self.fields.set_field("mstep_reg_select", True) - self.fields.set_field("multistep_filt", True) - tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - # Allow other registers to be set from the config - set_config_field = self.fields.set_config_field - set_config_field(config, "toff", 3) - set_config_field(config, "hstrt", 5) - set_config_field(config, "hend", 0) - set_config_field(config, "tbl", 2) - set_config_field(config, "iholddelay", 8) - set_config_field(config, "tpowerdown", 20) - set_config_field(config, "pwm_ofs", 36) - set_config_field(config, "pwm_grad", 14) - set_config_field(config, "pwm_freq", 1) - set_config_field(config, "pwm_autoscale", True) - set_config_field(config, "pwm_autograd", True) - set_config_field(config, "pwm_reg", 8) - set_config_field(config, "pwm_lim", 12) - set_config_field(config, "sgthrs", 0) - -def load_config_prefix(config): - return TMC2209(config) +# TMC2209 configuration +# +# Copyright (C) 2019 Stephan Oelze +# +# This file may be distributed under the terms of the GNU GPLv3 license. +from . import tmc2208, tmc2130, tmc, tmc_uart + +TMC_FREQUENCY=12000000. + +Registers = dict(tmc2208.Registers) +Registers.update({ + "TCOOLTHRS": 0x14, + "COOLCONF": 0x42, + "SGTHRS": 0x40, + "SG_RESULT": 0x41 +}) + +ReadRegisters = tmc2208.ReadRegisters + ["SG_RESULT"] + +Fields = dict(tmc2208.Fields) +Fields["COOLCONF"] = { + "semin": 0x0F << 0, + "seup": 0x03 << 5, + "semax": 0x0F << 8, + "sedn": 0x03 << 13, + "seimin": 0x01 << 15 +} +Fields["IOIN"] = { + "enn": 0x01 << 0, + "ms1": 0x01 << 2, + "ms2": 0x01 << 3, + "diag": 0x01 << 4, + "pdn_uart": 0x01 << 6, + "step": 0x01 << 7, + "spread_en": 0x01 << 8, + "dir": 0x01 << 9, + "version": 0xff << 24 +} +Fields["SGTHRS"] = { + "sgthrs": 0xFF << 0 +} +Fields["SG_RESULT"] = { + "sg_result": 0x3FF << 0 +} +Fields["TCOOLTHRS"] = { + "tcoolthrs": 0xfffff +} + +FieldFormatters = dict(tmc2208.FieldFormatters) + + +###################################################################### +# TMC2209 printer object +###################################################################### + +class TMC2209: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, tmc2208.SignedFields, + FieldFormatters) + self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 3, + TMC_FREQUENCY) + # Setup fields for UART + self.fields.set_field("pdn_disable", True) + self.fields.set_field("senddelay", 2) # Avoid tx errors on shared uart + # Allow virtual pins to be created + tmc.TMCVirtualPinHelper(config, self.mcu_tmc) + # Register commands + current_helper = tmc2130.TMCCurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + # Setup basic register values + self.fields.set_field("mstep_reg_select", True) + tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) + # Allow other registers to be set from the config + set_config_field = self.fields.set_config_field + # GCONF + set_config_field(config, "multistep_filt", True) + # CHOPCONF + set_config_field(config, "toff", 3) + set_config_field(config, "hstrt", 5) + set_config_field(config, "hend", 0) + set_config_field(config, "tbl", 2) + # IHOLDIRUN + set_config_field(config, "iholddelay", 8) + # PWMCONF + set_config_field(config, "pwm_ofs", 36) + set_config_field(config, "pwm_grad", 14) + set_config_field(config, "pwm_freq", 1) + set_config_field(config, "pwm_autoscale", True) + set_config_field(config, "pwm_autograd", True) + set_config_field(config, "pwm_reg", 8) + set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 20) + # SGTHRS + set_config_field(config, "sgthrs", 0) + +def load_config_prefix(config): + return TMC2209(config) diff --git a/klippy/extras/tmc2209.pyc b/klippy/extras/tmc2209.pyc deleted file mode 100644 index 95ab6f9ed84e085d58039d76ba14057df0cd080d..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 2830 zcmbVOZF3Yw5boW(+$EQU1d@<|q86ocq7Vog2}WK#2~Y)z?gcIKWm#_K?k4QZxjQFN z1yxqXzvW-?i$B315TEYZa3>ZYFv-qLKRw;k({Gc?-?NQB^q)^URQ^;k-^5q^>=7ya zc@z^R9_@LQ__XI!QlY&HB~{w1lBWPokgk#TXunPe*jFcAr~OGXRZo44R# z97EJ(ciTD-NoQ^C($&}N%U3Shio@-so5Nw0+aA{R_^<9Qv&iTahTYcA&i&oHLEC)C z5btKBwX?ltZZcBC(7q!(_+$}k-wA`;?T7bw%^VwixVvvNtG&gg`s1# zKld-_6*Pc7KLTI+Y{n~C0;`UbJ;B-PF|i=WW5jw<)-uAlx0o{VU+Zu+XE2|-G&4MEn;l{aqbmk^a3}H zF?xxc#TdOTHyE9_@&NxOLl$*?VTWT&y@3|FRzp2XTEqfV95 zarDB~$vn0s1#%uK+6xOE>yAZC0dl?yqibR-32w7)S4y>C*xZh)v=5c8j=AdWlh`&e zn|>CTCrJe}W(V0bovZ9w>Y50b(BN4TX5GSk%zWO-KrfG!VKZJM-CX}7oy&3q;62gM zW<@8$y=KM`mXxC6Ex6O`b&Mv#8-ryGO|IZTIt4pv%jj6$)$u^*Qo%wO0XQ5Ac-8b$ ztsH8(ZOL*g%ah1jv;Yz6vXUYYAF$Aa*255$E&WAYALt%?v@H6hGYrvt%b?g$#Kq6M z`B2*hXn^!jCbz>V{=uZqynu_}a@4?V4f9;5wlw?*%#tKZk8Z% z4A9?3HnDh5+i=j23XO<#Atr%ju&|LG7Ix8{+qODF_v-YsL3uXEgzvf)-2U<5?d{eh zF%cTVPL_5}&)u%c&8lqdaaWw?*phJ_cbl;9;=o+d%l*E^cl?n^4 zgCVJ;OveUmO!2Ee9H_|Z;2Miv;9->q_GEAe!^ji=CnAzZn=ZuH`Lu$geAcfalcv17 c{7zTqK~+ks?j7?-Yq!H;jLTP - -import math, logging -from . import bus, tmc, tmc_uart, tmc2130 - -TMC_FREQUENCY=10000000. - -Registers = { - "GCONF": 0x00, - "GSTAT": 0x01, - "IFCNT": 0x02, - "SLAVECONF": 0x03, - "IOIN": 0x04, - "DRV_CONF": 0x0A, - "GLOBALSCALER": 0x0B, - "IHOLD_IRUN": 0x10, - "TPOWERDOWN": 0x11, - "TSTEP": 0x12, - "TPWMTHRS": 0x13, - "TCOOLTHRS": 0x14, - "THIGH": 0x15, - "DIRECT_MODE": 0x2d, - "ENCMODE": 0x38, - "X_ENC": 0x39, - "ENC_CONST": 0x3a, - "ENC_STATUS": 0x3b, - "ENC_LATCH": 0x3c, - "ADC_VSUPPLY_AIN": 0x50, - "ADC_TEMP": 0x51, - "OTW_OV_VTH": 0x52, - "MSLUT_0": 0x60, - "MSLUT_1": 0x61, - "MSLUT_2": 0x62, - "MSLUT_3": 0x63, - "MSLUT_4": 0x64, - "MSLUT_5": 0x65, - "MSLUT_6": 0x66, - "MSLUT_7": 0x67, - "MSLUTSEL": 0x68, - "MSLUTSTART": 0x69, - "MSCNT": 0x6a, - "MSCURACT": 0x6b, - "CHOPCONF": 0x6c, - "COOLCONF": 0x6d, - "DRV_STATUS": 0x6f, - "PWMCONF": 0x70, - "PWM_SCALE": 0x71, - "PWM_AUTO": 0x72, - # "SG4_THRS": 0x74, - "SGTHRS": 0x74, - "SG4_RESULT": 0x75, - "SG4_IND": 0x76 -} - -ReadRegisters = [ - "GCONF", "CHOPCONF", "GSTAT", "DRV_STATUS", "IOIN", - "MSCNT", "MSCURACT", "PWM_SCALE", "PWM_AUTO", "IFCNT" -] - -Fields = {} - -Fields["GCONF"] = { - "fast_standstill": 0x01 << 1, - "en_pwm_mode": 0x01 << 2, - "multistep_filt": 0x01 << 3, - "shaft": 0x01 << 4, - "diag0_error": 0x01 << 5, - "diag0_otpw": 0x01 << 6, - "diag0_stall": 0x01 << 7, - "diag1_stall": 0x01 << 8, - "diag1_index": 0x01 << 9, - "diag1_onstate": 0x01 << 10, - "diag0_pushpull": 0x01 << 12, - "diag1_pushpull": 0x01 << 13, - "small_hysteresis": 0x01 << 14, - "stop_enable": 0x01 << 15, - "direct_mode": 0x01 << 16, -} - -Fields["GSTAT"] = { - "reset": 0x01 << 0, - "drv_err": 0x01 << 1, - "uv_cp": 0x01 << 2, - "register_reset": 0x01 << 3, - "vm_uvlo": 0x01 << 4 -} - -Fields["IOIN"] = { - "step": 0x01 << 0, - "dir": 0x01 << 1, - "encb": 0x01 << 2, - "enca": 0x01 << 3, - "drv_enn": 0x01 << 4, - "encn": 0x01 << 5, - "uart_en": 0x01 << 6, - "reserved": 0x01 << 7, - "comp_a": 0x01 << 8, - "comp_b": 0x01 << 9, - "comp_a1_a2": 0x01 << 10, - "comp_b1_b2": 0x01 << 11, - "version": 0xff << 24 -} - -Fields["GLOBALSCALER"] = { - "globalscaler": 0xff << 0 -} - -Fields["IHOLD_IRUN"] = { - "ihold": 0x1f << 0, - "irun": 0x1f << 8, - "iholddelay": 0x0f << 16, - "irundelay": 0x0f << 24 -} - -Fields["TPOWERDOWN"] = { - "tpowerdown": 0xff -} - -Fields["TSTEP"] = { - "tstep": 0xfffff << 0 -} - -Fields["TPWMTHRS"] = { - "tpwmthrs": 0xfffff << 0 -} - -Fields["TCOOLTHRS"] = { - "tcoolthrs": 0xfffff << 0 -} - -Fields["THIGH"] = { - "thigh": 0xfffff << 0 -} - -Fields["DIRECT_MODE"] = { - "direct_coil_a": 0x1ff << 0, - "direct_coil_b": 0x1ff << 16 -} - -Fields["ENCMODE"] = { - "pol_a": 0x01 << 0, - "pol_b": 0x01 << 1, - "pol_n": 0x01 << 2, - "ignore_ab": 0x01 << 3, - "clr_cont": 0x01 << 4, - "clr_once": 0x01 << 5, - "pos_neg_edge": 0x03 << 6, - "clr_enc_x": 0x01 << 8, - "enc_sel_decimal": 0x01 << 10 -} - -Fields["X_ENC"] = { - "x_enc": 0xffffffff << 0 -} - -Fields["ENC_CONST"] = { - "enc_const": 0xffffffff << 0 -} - -Fields["ENC_STATUS"] = { - "n_event": 0x01 << 0 -} - -Fields["ENC_LATCH"] = { - "enc_latch": 0xffffffff << 0 -} - -Fields["MSLUT_0"] = { - "mslut_0": 0xffffffff << 0 -} - -Fields["MSLUT_1"] = { - "mslut_1": 0xffffffff << 0 -} - -Fields["MSLUT_2"] = { - "mslut_2": 0xffffffff << 0 -} - -Fields["MSLUT_3"] = { - "mslut_3": 0xffffffff << 0 -} - -Fields["MSLUT_4"] = { - "mslut_4": 0xffffffff << 0 -} - -Fields["MSLUT_5"] = { - "mslut_5": 0xffffffff << 0 -} - -Fields["MSLUT_6"] = { - "mslut_6": 0xffffffff << 0 -} - -Fields["MSLUT_7"] = { - "mslut_7": 0xffffffff << 0 -} - -Fields["MSLUTSEL"] = { - "w0": 0x03 << 0, - "w1": 0x03 << 2, - "w2": 0x03 << 4, - "w3": 0x03 << 6, - "x1": 0xff << 8, - "x2": 0xff << 16, - "x3": 0xff << 24 -} - -Fields["MSLUTSTART"] = { - "start_sin": 0xff << 0, - "start_sin90": 0xff << 16, - "offset_sin90": 0xff << 24 -} - -Fields["MSCNT"] = { - "mscnt": 0x3ff << 0 -} - -Fields["MSCURACT"] = { - "cur_b": 0x1ff << 0, - "cur_a": 0x1ff << 16 -} - -Fields["CHOPCONF"] = { - "toff": 0x0F << 0, - "hstrt": 0x07 << 4, - "hend": 0x0F << 7, - "fd3": 0x01 << 11, - "disfdcc": 0x01 << 12, - "chm": 0x01 << 14, - "tbl": 0x03 << 15, - "vhighfs": 0x01 << 18, - "vhighchm": 0x01 << 19, - "tpfd": 0x0F << 20, # midrange resonances - "mres": 0x0F << 24, - "intpol": 0x01 << 28, - "dedge": 0x01 << 29, - "diss2g": 0x01 << 30, - "diss2vs": 0x01 << 31 -} - -Fields["COOLCONF"] = { - "semin": 0x0f << 0, - "seup": 0x03 << 5, - "semax": 0x0f << 8, - "sedn": 0x03 << 13, - "seimin": 0x01 << 15, - "sgt": 0x7f << 16, - "sfilt": 0x01 << 24 -} - -Fields["DRV_STATUS"] = { - "sg_result": 0x3FF << 0, - "s2vsa": 0x01 << 12, - "s2vsb": 0x01 << 13, - "stealth": 0x01 << 14, - "fsactive": 0x01 << 15, - "csactual": 0xFF << 16, - "stallguard": 0x01 << 24, - "ot": 0x01 << 25, - "otpw": 0x01 << 26, - "s2ga": 0x01 << 27, - "s2gb": 0x01 << 28, - "ola": 0x01 << 29, - "olb": 0x01 << 30, - "stst": 0x01 << 31 -} - -Fields["PWMCONF"] = { - "pwm_ofs": 0xFF << 0, - "pwm_grad": 0xFF << 8, - "pwm_freq": 0x03 << 16, - "pwm_autoscale": 0x01 << 18, - "pwm_autograd": 0x01 << 19, - "freewheel": 0x03 << 20, - "pwm_meas_sd_enable": 0x01 << 22, - "pwm_dis_reg_stst": 0x01 << 23, - "pwm_reg": 0x0F << 24, - "pwm_lim": 0x0F << 28 -} - -Fields["PWM_SCALE"] = { - "pwm_scale_sum": 0xff << 0, - "pwm_scale_auto": 0x1ff << 16 -} - -Fields["IFCNT"] = { - "ifcnt": 0xff -} - -''' -Fields["SG4_THRS"] = { - "sg4_thrs": 0xff, - "sg4_filt_en": 0x01 << 8, - "sg4_angle_offset": 0x01 << 9 -} -''' - -Fields["SGTHRS"] = { - "sgthrs": 0xff, - "sg4_filt_en": 0x01 << 8, - "sg4_angle_offset": 0x01 << 9 -} - -Fields["SG4_RESULT"] = { - "sg4_result": 0x3ff << 9 -} - -Fields["DRV_CONF"] = { - "current_range": 0x03 << 0, - "slope_control": 0x03 << 4, -} - -Fields["OTW_OV_VTH"] = { - "overtempperwarning_vth": 0x1ff << 16 -} - -SignedFields = ["cur_a", "cur_b", "sgt", - "pwm_scale_auto"] -FieldFormatters = dict(tmc2130.FieldFormatters) - -###################################################################### -# TMC stepper current config helper -###################################################################### - -MAX_CURRENT = 2.000 - -class TMC2240CurrentHelper: - def __init__(self, config, mcu_tmc): - self.printer = config.get_printer() - self.name = config.get_name().split()[-1] - self.mcu_tmc = mcu_tmc - self.fields = mcu_tmc.get_fields() - run_current = config.getfloat('run_current', - above=0., maxval=MAX_CURRENT) - hold_current = config.getfloat('hold_current', MAX_CURRENT, - above=0., maxval=MAX_CURRENT) - self.req_hold_current = hold_current - self._set_globalscaler(run_current) - irun, ihold = self._calc_current(run_current, hold_current) - self.fields.set_field("ihold", ihold) - self.fields.set_field("irun", irun) - # self.fields.set_field("irun", 31) - def _set_globalscaler(self, current): - globalscaler = int((current * 256. * math.sqrt(2.) - / 2.0 + .5)) - globalscaler = max(32, globalscaler) - if globalscaler >= 256: - globalscaler = 0 - self.fields.set_field("globalscaler", globalscaler) - # self.fields.set_field("globalscaler", 0) - def _calc_current_bits(self, current): - globalscaler = self.fields.get_field("globalscaler") - if not globalscaler: - globalscaler = 256 - cs = int((current * 256. * 32. * math.sqrt(2.)) / (3. * globalscaler) -1. + .5) - return max(0, min(31, cs)) - def _calc_current(self, run_current, hold_current): - irun = self._calc_current_bits(run_current) - ihold = self._calc_current_bits(min(hold_current, run_current)) - return irun, ihold - def _calc_current_from_field(self, field_name): - globalscaler = self.fields.get_field("globalscaler") - if not globalscaler: - globalscaler = 256 - bits = self.fields.get_field(field_name) - return (globalscaler * (bits + 1) * 0.325 - / (256. * 32. * math.sqrt(2.))) - def get_current(self): - run_current = self._calc_current_from_field("irun") - hold_current = self._calc_current_from_field("ihold") - return run_current, hold_current, self.req_hold_current, MAX_CURRENT - def set_current(self, run_current, hold_current, print_time): - self.req_hold_current = hold_current - irun, ihold = self._calc_current(run_current, hold_current) - self.fields.set_field("ihold", ihold) - val = self.fields.set_field("irun", irun) - # self.printer.command_error("val = %d, print_time = ", val, print_time) - self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) - -###################################################################### -# TMC2240 printer object -###################################################################### - -class TMC2240: - def __init__(self, config): - # Setup mcu communication - self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields) - # self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, 4) - # Setup fields for UART - # self.fields.set_field("uart_en", True) - - # Allow virtual pins to be created - tmc.TMCVirtualPinHelper(config, self.mcu_tmc) - # Register commands - current_helper = TMC2240CurrentHelper(config, self.mcu_tmc) - cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) - cmdhelper.setup_register_dump(ReadRegisters) - self.get_phase_offset = cmdhelper.get_phase_offset - self.get_status = cmdhelper.get_status - # Setup basic register values - # tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - tmc.TMC2240StealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - set_config_field = self.fields.set_config_field - - # set_config_field(config, "en_pwm_mode", 1) - set_config_field(config, "reset", 1) - set_config_field(config, "drv_err", 1) - set_config_field(config, "uv_cp", 1) - set_config_field(config, "register_reset", 1) - set_config_field(config, "vm_uvlo", 1) - # set_config_field(config, "tpwmthrs", 100) - # set_config_field(config, "intpol", 0) - # set_config_field(config, "dedge", 0) - # set_config_field(config, "disfdcc", 1) - set_config_field(config, "toff", 3) - set_config_field(config, "hstrt", 5) - set_config_field(config, "hend", 2) - set_config_field(config, "fd3", 0) - set_config_field(config, "disfdcc", 0) - set_config_field(config, "chm", 0) - set_config_field(config, "tbl", 2) - set_config_field(config, "vhighfs", 0) - set_config_field(config, "vhighchm", 0) - set_config_field(config, "tpfd", 4) - set_config_field(config, "diss2g", 0) - set_config_field(config, "diss2vs", 0) - set_config_field(config, "semin", 0) - set_config_field(config, "seup", 0) - set_config_field(config, "semax", 0) - set_config_field(config, "sedn", 0) - set_config_field(config, "seimin", 0) - set_config_field(config, "sgt", 0) - set_config_field(config, "sfilt", 0) - set_config_field(config, "iholddelay", 6) - set_config_field(config, "pwm_ofs", 30) - set_config_field(config, "pwm_grad", 0) - set_config_field(config, "pwm_freq", 0) - set_config_field(config, "pwm_autoscale", True) - set_config_field(config, "pwm_autograd", True) - set_config_field(config, "freewheel", 0) - set_config_field(config, "pwm_reg", 4) - set_config_field(config, "pwm_lim", 12) - set_config_field(config, "tpowerdown", 10) - set_config_field(config, "current_range", 2) - set_config_field(config, "overtempperwarning_vth", 0x1ff) - - -def load_config_prefix(config): - return TMC2240(config) +# TMC2240 configuration +# +# Copyright (C) 2018-2023 Kevin O'Connor +# Copyright (C) 2023 Alex Voinea +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import math, logging +from . import bus, tmc, tmc2130, tmc_uart + +TMC_FREQUENCY=12500000. + +Registers = { + "GCONF": 0x00, + "GSTAT": 0x01, + "IFCNT": 0x02, + "NODECONF": 0x03, + "IOIN": 0x04, + "DRV_CONF": 0x0A, + "GLOBALSCALER": 0x0B, + "IHOLD_IRUN": 0x10, + "TPOWERDOWN": 0x11, + "TSTEP": 0x12, + "TPWMTHRS": 0x13, + "TCOOLTHRS": 0x14, + "THIGH": 0x15, + "DIRECT_MODE": 0x2D, + "ENCMODE": 0x38, + "X_ENC": 0x39, + "ENC_CONST": 0x3A, + "ENC_STATUS": 0x3B, + "ENC_LATCH": 0x3C, + "ADC_VSUPPLY_AIN": 0x50, + "ADC_TEMP": 0x51, + "OTW_OV_VTH": 0x52, + "MSLUT0": 0x60, + "MSLUT1": 0x61, + "MSLUT2": 0x62, + "MSLUT3": 0x63, + "MSLUT4": 0x64, + "MSLUT5": 0x65, + "MSLUT6": 0x66, + "MSLUT7": 0x67, + "MSLUTSEL": 0x68, + "MSLUTSTART": 0x69, + "MSCNT": 0x6A, + "MSCURACT": 0x6B, + "CHOPCONF": 0x6C, + "COOLCONF": 0x6D, + "DRV_STATUS": 0x6F, + "PWMCONF": 0x70, + "PWM_SCALE": 0x71, + "PWM_AUTO": 0x72, + "SG4_THRS": 0x74, + "SG4_RESULT": 0x75, + "SG4_IND": 0x76, +} + +ReadRegisters = [ + "GCONF", "GSTAT", "IOIN", "DRV_CONF", "GLOBALSCALER", "IHOLD_IRUN", + "TPOWERDOWN", "TSTEP", "TPWMTHRS", "TCOOLTHRS", "THIGH", "ADC_VSUPPLY_AIN", + "ADC_TEMP", "MSCNT", "MSCURACT", "CHOPCONF", "COOLCONF", "DRV_STATUS", + "PWMCONF", "PWM_SCALE", "PWM_AUTO", "SG4_THRS", "SG4_RESULT", "SG4_IND" +] + +Fields = {} +Fields["COOLCONF"] = { + "semin": 0x0F << 0, + "seup": 0x03 << 5, + "semax": 0x0F << 8, + "sedn": 0x03 << 13, + "seimin": 0x01 << 15, + "sgt": 0x7F << 16, + "sfilt": 0x01 << 24 +} +Fields["CHOPCONF"] = { + "toff": 0x0F << 0, + "hstrt": 0x07 << 4, + "hend": 0x0F << 7, + "fd3": 0x01 << 11, + "disfdcc": 0x01 << 12, + "chm": 0x01 << 14, + "tbl": 0x03 << 15, + "vhighfs": 0x01 << 18, + "vhighchm": 0x01 << 19, + "tpfd": 0x0F << 20, # midrange resonances + "mres": 0x0F << 24, + "intpol": 0x01 << 28, + "dedge": 0x01 << 29, + "diss2g": 0x01 << 30, + "diss2vs": 0x01 << 31 +} +Fields["DRV_STATUS"] = { + "sg_result": 0x3FF << 0, + "s2vsa": 0x01 << 12, + "s2vsb": 0x01 << 13, + "stealth": 0x01 << 14, + "fsactive": 0x01 << 15, + "csactual": 0x1F << 16, + "stallguard": 0x01 << 24, + "ot": 0x01 << 25, + "otpw": 0x01 << 26, + "s2ga": 0x01 << 27, + "s2gb": 0x01 << 28, + "ola": 0x01 << 29, + "olb": 0x01 << 30, + "stst": 0x01 << 31 +} +Fields["GCONF"] = { + "faststandstill": 0x01 << 1, + "en_pwm_mode": 0x01 << 2, + "multistep_filt": 0x01 << 3, + "shaft": 0x01 << 4, + "diag0_error": 0x01 << 5, + "diag0_otpw": 0x01 << 6, + "diag0_stall": 0x01 << 7, + "diag1_stall": 0x01 << 8, + "diag1_index": 0x01 << 9, + "diag1_onstate": 0x01 << 10, + "diag0_pushpull": 0x01 << 12, + "diag1_pushpull": 0x01 << 13, + "small_hysteresis": 0x01 << 14, + "stop_enable": 0x01 << 15, + "direct_mode": 0x01 << 16 +} +Fields["GSTAT"] = { + "reset": 0x01 << 0, + "drv_err": 0x01 << 1, + "uv_cp": 0x01 << 2, + "register_reset": 0x01 << 3, + "vm_uvlo": 0x01 << 4 +} +Fields["GLOBALSCALER"] = { + "globalscaler": 0xFF << 0 +} +Fields["IHOLD_IRUN"] = { + "ihold": 0x1F << 0, + "irun": 0x1F << 8, + "iholddelay": 0x0F << 16, + "irundelay": 0x0F << 24 +} +Fields["IOIN"] = { + "step": 0x01 << 0, + "dir": 0x01 << 1, + "encb": 0x01 << 2, + "enca": 0x01 << 3, + "drv_enn": 0x01 << 4, + "encn": 0x01 << 5, + "uart_en": 0x01 << 6, + "comp_a": 0x01 << 8, + "comp_b": 0x01 << 9, + "comp_a1_a2": 0x01 << 10, + "comp_b1_b2": 0x01 << 11, + "output": 0x01 << 12, + "ext_res_det": 0x01 << 13, + "ext_clk": 0x01 << 14, + "adc_err": 0x01 << 15, + "silicon_rv": 0x07 << 16, + "version": 0xFF << 24 +} +Fields["MSLUT0"] = { "mslut0": 0xffffffff } +Fields["MSLUT1"] = { "mslut1": 0xffffffff } +Fields["MSLUT2"] = { "mslut2": 0xffffffff } +Fields["MSLUT3"] = { "mslut3": 0xffffffff } +Fields["MSLUT4"] = { "mslut4": 0xffffffff } +Fields["MSLUT5"] = { "mslut5": 0xffffffff } +Fields["MSLUT6"] = { "mslut6": 0xffffffff } +Fields["MSLUT7"] = { "mslut7": 0xffffffff } +Fields["MSLUTSEL"] = { + "x3": 0xFF << 24, + "x2": 0xFF << 16, + "x1": 0xFF << 8, + "w3": 0x03 << 6, + "w2": 0x03 << 4, + "w1": 0x03 << 2, + "w0": 0x03 << 0, +} +Fields["MSLUTSTART"] = { + "start_sin": 0xFF << 0, + "start_sin90": 0xFF << 16, + "offset_sin90": 0xFF << 24, +} +Fields["MSCNT"] = { + "mscnt": 0x3ff << 0 +} +Fields["MSCURACT"] = { + "cur_a": 0x1ff << 0, + "cur_b": 0x1ff << 16 +} +Fields["PWM_AUTO"] = { + "pwm_ofs_auto": 0xff << 0, + "pwm_grad_auto": 0xff << 16 +} +Fields["PWMCONF"] = { + "pwm_ofs": 0xFF << 0, + "pwm_grad": 0xFF << 8, + "pwm_freq": 0x03 << 16, + "pwm_autoscale": 0x01 << 18, + "pwm_autograd": 0x01 << 19, + "freewheel": 0x03 << 20, + "pwm_meas_sd_enable": 0x01 << 22, + "pwm_dis_reg_stst": 0x01 << 23, + "pwm_reg": 0x0F << 24, + "pwm_lim": 0x0F << 28 +} +Fields["PWM_SCALE"] = { + "pwm_scale_sum": 0x3ff << 0, + "pwm_scale_auto": 0x1ff << 16 +} +Fields["TPOWERDOWN"] = { + "tpowerdown": 0xff << 0 +} +Fields["TPWMTHRS"] = { + "tpwmthrs": 0xfffff << 0 +} +Fields["TCOOLTHRS"] = { + "tcoolthrs": 0xfffff << 0 +} +Fields["TSTEP"] = { + "tstep": 0xfffff << 0 +} +Fields["THIGH"] = { + "thigh": 0xfffff << 0 +} +Fields["DRV_CONF"] = { + "current_range": 0x03 << 0, + "slope_control": 0x03 << 4 +} +Fields["ADC_VSUPPLY_AIN"] = { + "adc_vsupply": 0x1fff << 0, + "adc_ain": 0x1fff << 16 +} +Fields["ADC_TEMP"] = { + "adc_temp": 0x1fff << 0 +} +Fields["OTW_OV_VTH"] = { + "overvoltage_vth": 0x1fff << 0, + "overtempprewarning_vth": 0x1fff << 16 +} +Fields["SG4_THRS"] = { + "sg4_thrs": 0xFF << 0, + "sg4_filt_en": 0x01 << 8, + "sg4_angle_offset": 0x01 << 9 +} +Fields["SG4_RESULT"] = { + "sg4_result": 0x3FF << 0 +} +Fields["SG4_IND"] = { + "sg4_ind_0": 0xFF << 0, + "sg4_ind_1": 0xFF << 8, + "sg4_ind_2": 0xFF << 16, + "sg4_ind_3": 0xFF << 24 +} + + +SignedFields = ["cur_a", "cur_b", "sgt", "pwm_scale_auto", "offset_sin90"] + +FieldFormatters = dict(tmc2130.FieldFormatters) +FieldFormatters.update({ + "s2vsa": (lambda v: "1(ShortToSupply_A!)" if v else ""), + "s2vsb": (lambda v: "1(ShortToSupply_B!)" if v else ""), + "adc_temp": (lambda v: "0x%04x(%.1fC)" % (v, ((v - 2038) / 7.7))), +}) + + +###################################################################### +# TMC stepper current config helper +###################################################################### + +class TMC2240CurrentHelper: + def __init__(self, config, mcu_tmc): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.mcu_tmc = mcu_tmc + self.fields = mcu_tmc.get_fields() + self.Rref = config.getfloat('rref', 12000., + minval=12000., maxval=60000.) + max_cur = self._get_ifs_rms(3) + run_current = config.getfloat('run_current', above=0., maxval=max_cur) + hold_current = config.getfloat('hold_current', max_cur, + above=0., maxval=max_cur) + self.req_hold_current = hold_current + current_range = self._calc_current_range(run_current) + self.fields.set_field("current_range", current_range) + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + self.fields.set_field("globalscaler", gscaler) + self.fields.set_field("ihold", ihold) + self.fields.set_field("irun", irun) + def _get_ifs_rms(self, current_range=None): + if current_range is None: + current_range = self.fields.get_field("current_range") + KIFS = [11750., 24000., 36000., 36000.] + return (KIFS[current_range] / self.Rref) / math.sqrt(2.) + def _calc_current_range(self, current): + for current_range in range(4): + if current <= self._get_ifs_rms(current_range): + break + return current_range + def _calc_globalscaler(self, current): + ifs_rms = self._get_ifs_rms() + globalscaler = int(((current * 256.) / ifs_rms) + .5) + globalscaler = max(32, globalscaler) + if globalscaler >= 256: + globalscaler = 0 + return globalscaler + def _calc_current_bits(self, current, globalscaler): + ifs_rms = self._get_ifs_rms() + if not globalscaler: + globalscaler = 256 + cs = int((current * 256. * 32.) / (globalscaler * ifs_rms) - 1. + .5) + return max(0, min(31, cs)) + def _calc_current(self, run_current, hold_current): + gscaler = self._calc_globalscaler(run_current) + irun = self._calc_current_bits(run_current, gscaler) + ihold = self._calc_current_bits(min(hold_current, run_current), gscaler) + return gscaler, irun, ihold + def _calc_current_from_field(self, field_name): + ifs_rms = self._get_ifs_rms() + globalscaler = self.fields.get_field("globalscaler") + if not globalscaler: + globalscaler = 256 + bits = self.fields.get_field(field_name) + return globalscaler * (bits + 1) * ifs_rms / (256. * 32.) + def get_current(self): + ifs_rms = self._get_ifs_rms() + run_current = self._calc_current_from_field("irun") + hold_current = self._calc_current_from_field("ihold") + return (run_current, hold_current, self.req_hold_current, ifs_rms) + def set_current(self, run_current, hold_current, print_time): + self.req_hold_current = hold_current + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + val = self.fields.set_field("globalscaler", gscaler) + self.mcu_tmc.set_register("GLOBALSCALER", val, print_time) + self.fields.set_field("ihold", ihold) + val = self.fields.set_field("irun", irun) + self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) + + +###################################################################### +# TMC2240 printer object +###################################################################### + +class TMC2240: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) + if config.get("uart_pin", None) is not None: + # use UART for communication + self.mcu_tmc = tmc_uart.MCU_TMC_uart(config, Registers, self.fields, + 3, TMC_FREQUENCY) + else: + # Use SPI bus for communication + self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields, + TMC_FREQUENCY) + # Allow virtual pins to be created + tmc.TMCVirtualPinHelper(config, self.mcu_tmc) + # Register commands + current_helper = TMC2240CurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + # Setup basic register values + tmc.TMCWaveTableHelper(config, self.mcu_tmc) + self.fields.set_config_field(config, "offset_sin90", 0) + tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) + set_config_field = self.fields.set_config_field + # GCONF + set_config_field(config, "multistep_filt", True) + # CHOPCONF + set_config_field(config, "toff", 3) + set_config_field(config, "hstrt", 5) + set_config_field(config, "hend", 2) + set_config_field(config, "fd3", 0) + set_config_field(config, "disfdcc", 0) + set_config_field(config, "chm", 0) + set_config_field(config, "tbl", 2) + set_config_field(config, "vhighfs", 0) + set_config_field(config, "vhighchm", 0) + set_config_field(config, "tpfd", 4) + set_config_field(config, "diss2g", 0) + set_config_field(config, "diss2vs", 0) + # COOLCONF + set_config_field(config, "semin", 0) + set_config_field(config, "seup", 0) + set_config_field(config, "semax", 0) + set_config_field(config, "sedn", 0) + set_config_field(config, "seimin", 0) + set_config_field(config, "sgt", 0) + set_config_field(config, "sfilt", 0) + # IHOLDIRUN + set_config_field(config, "iholddelay", 6) + set_config_field(config, "irundelay", 4) + # PWMCONF + set_config_field(config, "pwm_ofs", 29) + set_config_field(config, "pwm_grad", 0) + set_config_field(config, "pwm_freq", 0) + set_config_field(config, "pwm_autoscale", True) + set_config_field(config, "pwm_autograd", True) + set_config_field(config, "freewheel", 0) + set_config_field(config, "pwm_reg", 4) + set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 10) + # SG4_THRS + set_config_field(config, "sg4_angle_offset", 1) + +def load_config_prefix(config): + return TMC2240(config) diff --git a/klippy/extras/tmc2660.py b/klippy/extras/tmc2660.py index e873c60..8405767 100644 --- a/klippy/extras/tmc2660.py +++ b/klippy/extras/tmc2660.py @@ -1,274 +1,276 @@ -# TMC2660 configuration -# -# Copyright (C) 2018-2019 Florian Heilmann -# Copyright (C) 2019-2021 Kevin O'Connor -# -# This file may be distributed under the terms of the GNU GPLv3 license. -import math, logging -from . import bus, tmc, tmc2130 - -Registers = { - "DRVCONF": 0xE, "SGCSCONF": 0xC, "SMARTEN": 0xA, - "CHOPCONF": 0x8, "DRVCTRL": 0x0 -} - -ReadRegisters = [ "READRSP@RDSEL0", "READRSP@RDSEL1", "READRSP@RDSEL2" ] - -Fields = {} - -Fields["DRVCTRL"] = { - "mres": 0x0f, - "dedge": 0x01 << 8, - "intpol": 0x01 << 9, -} - -Fields["CHOPCONF"] = { - "toff": 0x0f, - "hstrt": 0x7 << 4, - "hend": 0x0f << 7, - "hdec": 0x03 << 11, - "rndtf": 0x01 << 13, - "chm": 0x01 << 14, - "tbl": 0x03 << 15 -} - -Fields["SMARTEN"] = { - "semin" : 0x0f, - "seup": 0x03 << 5, - "semax": 0x0f << 8, - "sedn": 0x03 << 13, - "seimin": 0x01 << 15 -} - -Fields["SGCSCONF"] = { - "cs": 0x1f, - "sgt": 0x7F << 8, - "sfilt": 0x01 << 16 -} - -Fields["DRVCONF"] = { - "rdsel": 0x03 << 4, - "vsense": 0x01 << 6, - "sdoff": 0x01 << 7, - "ts2g": 0x03 << 8, - "diss2g": 0x01 << 10, - "slpl": 0x03 << 12, - "slph": 0x03 << 14, - "tst": 0x01 << 16 -} - -Fields["READRSP@RDSEL0"] = { - "stallguard": 0x01 << 4, - "ot": 0x01 << 5, - "otpw": 0x01 << 6, - "s2ga": 0x01 << 7, - "s2gb": 0x01 << 8, - "ola": 0x01 << 9, - "olb": 0x01 << 10, - "stst": 0x01 << 11, - "mstep": 0x3ff << 14 -} - -Fields["READRSP@RDSEL1"] = { - "stallguard": 0x01 << 4, - "ot": 0x01 << 5, - "otpw": 0x01 << 6, - "s2ga": 0x01 << 7, - "s2gb": 0x01 << 8, - "ola": 0x01 << 9, - "olb": 0x01 << 10, - "stst": 0x01 << 11, - "sg_result": 0x3ff << 14 -} - -Fields["READRSP@RDSEL2"] = { - "stallguard": 0x01 << 4, - "ot": 0x01 << 5, - "otpw": 0x01 << 6, - "s2ga": 0x01 << 7, - "s2gb": 0x01 << 8, - "ola": 0x01 << 9, - "olb": 0x01 << 10, - "stst": 0x01 << 11, - "se": 0x1f << 14, - "sg_result@rdsel2": 0x1f << 19 -} - -SignedFields = ["sgt"] - -FieldFormatters = dict(tmc2130.FieldFormatters) -FieldFormatters.update({ - "chm": (lambda v: "1(constant toff)" if v else "0(spreadCycle)"), - "vsense": (lambda v: "1(165mV)" if v else "0(305mV)"), - "sdoff": (lambda v: "1(Step/Dir disabled!)" if v else ""), - "diss2g": (lambda v: "1(Short to GND disabled!)" if v else ""), - "se": (lambda v: ("%d" % v) if v else "0(Reset?)"), -}) - - -###################################################################### -# TMC stepper current config helper -###################################################################### - -MAX_CURRENT = 2.400 - -class TMC2660CurrentHelper: - def __init__(self, config, mcu_tmc): - self.printer = config.get_printer() - self.name = config.get_name().split()[-1] - self.mcu_tmc = mcu_tmc - self.fields = mcu_tmc.get_fields() - self.current = config.getfloat('run_current', minval=0.1, - maxval=MAX_CURRENT) - self.sense_resistor = config.getfloat('sense_resistor') - vsense, cs = self._calc_current(self.current) - self.fields.set_field("cs", cs) - self.fields.set_field("vsense", vsense) - - # Register ready/printing handlers - self.idle_current_percentage = config.getint( - 'idle_current_percent', default=100, minval=0, maxval=100) - if self.idle_current_percentage < 100: - self.printer.register_event_handler("idle_timeout:printing", - self._handle_printing) - self.printer.register_event_handler("idle_timeout:ready", - self._handle_ready) - - def _calc_current_bits(self, current, vsense): - vref = 0.165 if vsense else 0.310 - sr = self.sense_resistor - cs = int(32. * sr * current * math.sqrt(2.) / vref + .5) - 1 - return max(0, min(31, cs)) - - def _calc_current_from_bits(self, cs, vsense): - vref = 0.165 if vsense else 0.310 - return (cs + 1) * vref / (32. * self.sense_resistor * math.sqrt(2.)) - - def _calc_current(self, run_current): - vsense = True - irun = self._calc_current_bits(run_current, True) - if irun == 31: - cur = self._calc_current_from_bits(irun, True) - if cur < run_current: - irun2 = self._calc_current_bits(run_current, False) - cur2 = self._calc_current_from_bits(irun2, False) - if abs(run_current - cur2) < abs(run_current - cur): - vsense = False - irun = irun2 - return vsense, irun - - def _handle_printing(self, print_time): - print_time -= 0.100 # Schedule slightly before deadline - self.printer.get_reactor().register_callback( - (lambda ev: self._update_current(self.current, print_time))) - - def _handle_ready(self, print_time): - current = self.current * float(self.idle_current_percentage) / 100. - self.printer.get_reactor().register_callback( - (lambda ev: self._update_current(current, print_time))) - - def _update_current(self, current, print_time): - vsense, cs = self._calc_current(current) - val = self.fields.set_field("cs", cs) - self.mcu_tmc.set_register("SGCSCONF", val, print_time) - # Only update VSENSE if we need to - if vsense != self.fields.get_field("vsense"): - val = self.fields.set_field("vsense", vsense) - self.mcu_tmc.set_register("DRVCONF", val, print_time) - - def get_current(self): - return self.current, None, None, MAX_CURRENT - - def set_current(self, run_current, hold_current, print_time): - self.current = run_current - self._update_current(run_current, print_time) - - -###################################################################### -# TMC2660 SPI -###################################################################### - -# Helper code for working with TMC2660 devices via SPI -class MCU_TMC2660_SPI: - def __init__(self, config, name_to_reg, fields): - self.printer = config.get_printer() - self.mutex = self.printer.get_reactor().mutex() - self.spi = bus.MCU_SPI_from_config(config, 0, default_speed=4000000) - self.name_to_reg = name_to_reg - self.fields = fields - def get_fields(self): - return self.fields - def get_register(self, reg_name): - new_rdsel = ReadRegisters.index(reg_name) - reg = self.name_to_reg["DRVCONF"] - if self.printer.get_start_args().get('debugoutput') is not None: - return 0 - with self.mutex: - old_rdsel = self.fields.get_field("rdsel") - val = self.fields.set_field("rdsel", new_rdsel) - msg = [((val >> 16) | reg) & 0xff, (val >> 8) & 0xff, val & 0xff] - if new_rdsel != old_rdsel: - # Must set RDSEL value first - self.spi.spi_send(msg) - params = self.spi.spi_transfer(msg) - pr = bytearray(params['response']) - return (pr[0] << 16) | (pr[1] << 8) | pr[2] - def set_register(self, reg_name, val, print_time=None): - minclock = 0 - if print_time is not None: - minclock = self.spi.get_mcu().print_time_to_clock(print_time) - reg = self.name_to_reg[reg_name] - msg = [((val >> 16) | reg) & 0xff, (val >> 8) & 0xff, val & 0xff] - with self.mutex: - self.spi.spi_send(msg, minclock) - - -###################################################################### -# TMC2660 printer object -###################################################################### - -class TMC2660: - def __init__(self, config): - # Setup mcu communication - self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.fields.set_field("sdoff", 0) # Access DRVCTRL in step/dir mode - self.mcu_tmc = MCU_TMC2660_SPI(config, Registers, self.fields) - # Register commands - current_helper = TMC2660CurrentHelper(config, self.mcu_tmc) - cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) - cmdhelper.setup_register_dump(ReadRegisters) - self.get_phase_offset = cmdhelper.get_phase_offset - self.get_status = cmdhelper.get_status - - # CHOPCONF - set_config_field = self.fields.set_config_field - set_config_field(config, "tbl", 2) - set_config_field(config, "rndtf", 0) - set_config_field(config, "hdec", 0) - set_config_field(config, "chm", 0) - set_config_field(config, "hend", 3) - set_config_field(config, "hstrt", 3) - set_config_field(config, "toff", 4) - if not self.fields.get_field("chm"): - if (self.fields.get_field("hstrt") + - self.fields.get_field("hend")) > 15: - raise config.error("driver_HEND + driver_HSTRT must be <= 15") - # SMARTEN - set_config_field(config, "seimin", 0) - set_config_field(config, "sedn", 0) - set_config_field(config, "semax", 0) - set_config_field(config, "seup", 0) - set_config_field(config, "semin", 0) - - # SGSCONF - set_config_field(config, "sfilt", 0) - set_config_field(config, "sgt", 0) - - # DRVCONF - set_config_field(config, "slph", 0) - set_config_field(config, "slpl", 0) - set_config_field(config, "diss2g", 0) - set_config_field(config, "ts2g", 3) - -def load_config_prefix(config): - return TMC2660(config) +# TMC2660 configuration +# +# Copyright (C) 2018-2019 Florian Heilmann +# Copyright (C) 2019-2021 Kevin O'Connor +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import math, logging +from . import bus, tmc, tmc2130 + +Registers = { + "DRVCONF": 0xE, "SGCSCONF": 0xC, "SMARTEN": 0xA, + "CHOPCONF": 0x8, "DRVCTRL": 0x0 +} + +ReadRegisters = [ "READRSP@RDSEL0", "READRSP@RDSEL1", "READRSP@RDSEL2" ] + +Fields = {} + +Fields["DRVCTRL"] = { + "mres": 0x0f, + "dedge": 0x01 << 8, + "intpol": 0x01 << 9, +} + +Fields["CHOPCONF"] = { + "toff": 0x0f, + "hstrt": 0x7 << 4, + "hend": 0x0f << 7, + "hdec": 0x03 << 11, + "rndtf": 0x01 << 13, + "chm": 0x01 << 14, + "tbl": 0x03 << 15 +} + +Fields["SMARTEN"] = { + "semin" : 0x0f, + "seup": 0x03 << 5, + "semax": 0x0f << 8, + "sedn": 0x03 << 13, + "seimin": 0x01 << 15 +} + +Fields["SGCSCONF"] = { + "cs": 0x1f, + "sgt": 0x7F << 8, + "sfilt": 0x01 << 16 +} + +Fields["DRVCONF"] = { + "rdsel": 0x03 << 4, + "vsense": 0x01 << 6, + "sdoff": 0x01 << 7, + "ts2g": 0x03 << 8, + "diss2g": 0x01 << 10, + "slpl": 0x03 << 12, + "slph": 0x03 << 14, + "tst": 0x01 << 16 +} + +Fields["READRSP@RDSEL0"] = { + "stallguard": 0x01 << 4, + "ot": 0x01 << 5, + "otpw": 0x01 << 6, + "s2ga": 0x01 << 7, + "s2gb": 0x01 << 8, + "ola": 0x01 << 9, + "olb": 0x01 << 10, + "stst": 0x01 << 11, + "mstep": 0x3ff << 14 +} + +Fields["READRSP@RDSEL1"] = { + "stallguard": 0x01 << 4, + "ot": 0x01 << 5, + "otpw": 0x01 << 6, + "s2ga": 0x01 << 7, + "s2gb": 0x01 << 8, + "ola": 0x01 << 9, + "olb": 0x01 << 10, + "stst": 0x01 << 11, + "sg_result": 0x3ff << 14 +} + +Fields["READRSP@RDSEL2"] = { + "stallguard": 0x01 << 4, + "ot": 0x01 << 5, + "otpw": 0x01 << 6, + "s2ga": 0x01 << 7, + "s2gb": 0x01 << 8, + "ola": 0x01 << 9, + "olb": 0x01 << 10, + "stst": 0x01 << 11, + "se": 0x1f << 14, + "sg_result@rdsel2": 0x1f << 19 +} + +SignedFields = ["sgt"] + +FieldFormatters = dict(tmc2130.FieldFormatters) +FieldFormatters.update({ + "chm": (lambda v: "1(constant toff)" if v else "0(spreadCycle)"), + "vsense": (lambda v: "1(165mV)" if v else "0(305mV)"), + "sdoff": (lambda v: "1(Step/Dir disabled!)" if v else ""), + "diss2g": (lambda v: "1(Short to GND disabled!)" if v else ""), + "se": (lambda v: ("%d" % v) if v else "0(Reset?)"), +}) + + +###################################################################### +# TMC stepper current config helper +###################################################################### + +MAX_CURRENT = 2.400 + +class TMC2660CurrentHelper: + def __init__(self, config, mcu_tmc): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.mcu_tmc = mcu_tmc + self.fields = mcu_tmc.get_fields() + self.current = config.getfloat('run_current', minval=0.1, + maxval=MAX_CURRENT) + self.sense_resistor = config.getfloat('sense_resistor') + vsense, cs = self._calc_current(self.current) + self.fields.set_field("cs", cs) + self.fields.set_field("vsense", vsense) + + # Register ready/printing handlers + self.idle_current_percentage = config.getint( + 'idle_current_percent', default=100, minval=0, maxval=100) + if self.idle_current_percentage < 100: + self.printer.register_event_handler("idle_timeout:printing", + self._handle_printing) + self.printer.register_event_handler("idle_timeout:ready", + self._handle_ready) + + def _calc_current_bits(self, current, vsense): + vref = 0.165 if vsense else 0.310 + sr = self.sense_resistor + cs = int(32. * sr * current * math.sqrt(2.) / vref + .5) - 1 + return max(0, min(31, cs)) + + def _calc_current_from_bits(self, cs, vsense): + vref = 0.165 if vsense else 0.310 + return (cs + 1) * vref / (32. * self.sense_resistor * math.sqrt(2.)) + + def _calc_current(self, run_current): + vsense = True + irun = self._calc_current_bits(run_current, True) + if irun == 31: + cur = self._calc_current_from_bits(irun, True) + if cur < run_current: + irun2 = self._calc_current_bits(run_current, False) + cur2 = self._calc_current_from_bits(irun2, False) + if abs(run_current - cur2) < abs(run_current - cur): + vsense = False + irun = irun2 + return vsense, irun + + def _handle_printing(self, print_time): + print_time -= 0.100 # Schedule slightly before deadline + self.printer.get_reactor().register_callback( + (lambda ev: self._update_current(self.current, print_time))) + + def _handle_ready(self, print_time): + current = self.current * float(self.idle_current_percentage) / 100. + self.printer.get_reactor().register_callback( + (lambda ev: self._update_current(current, print_time))) + + def _update_current(self, current, print_time): + vsense, cs = self._calc_current(current) + val = self.fields.set_field("cs", cs) + self.mcu_tmc.set_register("SGCSCONF", val, print_time) + # Only update VSENSE if we need to + if vsense != self.fields.get_field("vsense"): + val = self.fields.set_field("vsense", vsense) + self.mcu_tmc.set_register("DRVCONF", val, print_time) + + def get_current(self): + return self.current, None, None, MAX_CURRENT + + def set_current(self, run_current, hold_current, print_time): + self.current = run_current + self._update_current(run_current, print_time) + + +###################################################################### +# TMC2660 SPI +###################################################################### + +# Helper code for working with TMC2660 devices via SPI +class MCU_TMC2660_SPI: + def __init__(self, config, name_to_reg, fields): + self.printer = config.get_printer() + self.mutex = self.printer.get_reactor().mutex() + self.spi = bus.MCU_SPI_from_config(config, 0, default_speed=4000000) + self.name_to_reg = name_to_reg + self.fields = fields + def get_fields(self): + return self.fields + def get_register(self, reg_name): + new_rdsel = ReadRegisters.index(reg_name) + reg = self.name_to_reg["DRVCONF"] + if self.printer.get_start_args().get('debugoutput') is not None: + return 0 + with self.mutex: + old_rdsel = self.fields.get_field("rdsel") + val = self.fields.set_field("rdsel", new_rdsel) + msg = [((val >> 16) | reg) & 0xff, (val >> 8) & 0xff, val & 0xff] + if new_rdsel != old_rdsel: + # Must set RDSEL value first + self.spi.spi_send(msg) + params = self.spi.spi_transfer(msg) + pr = bytearray(params['response']) + return (pr[0] << 16) | (pr[1] << 8) | pr[2] + def set_register(self, reg_name, val, print_time=None): + minclock = 0 + if print_time is not None: + minclock = self.spi.get_mcu().print_time_to_clock(print_time) + reg = self.name_to_reg[reg_name] + msg = [((val >> 16) | reg) & 0xff, (val >> 8) & 0xff, val & 0xff] + with self.mutex: + self.spi.spi_send(msg, minclock) + def get_tmc_frequency(self): + return None + + +###################################################################### +# TMC2660 printer object +###################################################################### + +class TMC2660: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) + self.fields.set_field("sdoff", 0) # Access DRVCTRL in step/dir mode + self.mcu_tmc = MCU_TMC2660_SPI(config, Registers, self.fields) + # Register commands + current_helper = TMC2660CurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + + # CHOPCONF + set_config_field = self.fields.set_config_field + set_config_field(config, "tbl", 2) + set_config_field(config, "rndtf", 0) + set_config_field(config, "hdec", 0) + set_config_field(config, "chm", 0) + set_config_field(config, "hend", 3) + set_config_field(config, "hstrt", 3) + set_config_field(config, "toff", 4) + if not self.fields.get_field("chm"): + if (self.fields.get_field("hstrt") + + self.fields.get_field("hend")) > 15: + raise config.error("driver_HEND + driver_HSTRT must be <= 15") + # SMARTEN + set_config_field(config, "seimin", 0) + set_config_field(config, "sedn", 0) + set_config_field(config, "semax", 0) + set_config_field(config, "seup", 0) + set_config_field(config, "semin", 0) + + # SGSCONF + set_config_field(config, "sfilt", 0) + set_config_field(config, "sgt", 0) + + # DRVCONF + set_config_field(config, "slph", 0) + set_config_field(config, "slpl", 0) + set_config_field(config, "diss2g", 0) + set_config_field(config, "ts2g", 3) + +def load_config_prefix(config): + return TMC2660(config) diff --git a/klippy/extras/tmc5160.py b/klippy/extras/tmc5160.py index 4d97027..9950f66 100644 --- a/klippy/extras/tmc5160.py +++ b/klippy/extras/tmc5160.py @@ -1,340 +1,383 @@ -# TMC5160 configuration -# -# Copyright (C) 2018-2019 Kevin O'Connor -# -# This file may be distributed under the terms of the GNU GPLv3 license. -import math, logging -from . import bus, tmc, tmc2130 - -TMC_FREQUENCY=12000000. - -Registers = { - "GCONF": 0x00, - "GSTAT": 0x01, - "IFCNT": 0x02, - "SLAVECONF": 0x03, - "IOIN": 0x04, - "X_COMPARE": 0x05, - "OTP_READ": 0x07, - "FACTORY_CONF": 0x08, - "SHORT_CONF": 0x09, - "DRV_CONF": 0x0A, - "GLOBALSCALER": 0x0B, - "OFFSET_READ": 0x0C, - "IHOLD_IRUN": 0x10, - "TPOWERDOWN": 0x11, - "TSTEP": 0x12, - "TPWMTHRS": 0x13, - "TCOOLTHRS": 0x14, - "THIGH": 0x15, - "RAMPMODE": 0x20, - "XACTUAL": 0x21, - "VACTUAL": 0x22, - "VSTART": 0x23, - "A1": 0x24, - "V1": 0x25, - "AMAX": 0x26, - "VMAX": 0x27, - "DMAX": 0x28, - "D1": 0x2A, - "VSTOP": 0x2B, - "TZEROWAIT": 0x2C, - "XTARGET": 0x2D, - "VDCMIN": 0x33, - "SW_MODE": 0x34, - "RAMP_STAT": 0x35, - "XLATCH": 0x36, - "ENCMODE": 0x38, - "X_ENC": 0x39, - "ENC_CONST": 0x3A, - "ENC_STATUS": 0x3B, - "ENC_LATCH": 0x3C, - "ENC_DEVIATION": 0x3D, - "MSLUT0": 0x60, - "MSLUT1": 0x61, - "MSLUT2": 0x62, - "MSLUT3": 0x63, - "MSLUT4": 0x64, - "MSLUT5": 0x65, - "MSLUT6": 0x66, - "MSLUT7": 0x67, - "MSLUTSEL": 0x68, - "MSLUTSTART": 0x69, - "MSCNT": 0x6A, - "MSCURACT": 0x6B, - "CHOPCONF": 0x6C, - "COOLCONF": 0x6D, - "DCCTRL": 0x6E, - "DRV_STATUS": 0x6F, - "PWMCONF": 0x70, - "PWM_SCALE": 0x71, - "PWM_AUTO": 0x72, - "LOST_STEPS": 0x73, -} - -ReadRegisters = [ - "GCONF", "CHOPCONF", "GSTAT", "DRV_STATUS", "FACTORY_CONF", "IOIN", - "LOST_STEPS", "MSCNT", "MSCURACT", "OTP_READ", "PWM_SCALE", - "PWM_AUTO", "TSTEP" -] - -Fields = {} -Fields["COOLCONF"] = { - "semin": 0x0F << 0, - "seup": 0x03 << 5, - "semax": 0x0F << 8, - "sedn": 0x03 << 13, - "seimin": 0x01 << 15, - "sgt": 0x7F << 16, - "sfilt": 0x01 << 24 -} -Fields["CHOPCONF"] = { - "toff": 0x0F << 0, - "hstrt": 0x07 << 4, - "hend": 0x0F << 7, - "fd3": 0x01 << 11, - "disfdcc": 0x01 << 12, - "chm": 0x01 << 14, - "tbl": 0x03 << 15, - "vhighfs": 0x01 << 18, - "vhighchm": 0x01 << 19, - "tpfd": 0x0F << 20, # midrange resonances - "mres": 0x0F << 24, - "intpol": 0x01 << 28, - "dedge": 0x01 << 29, - "diss2g": 0x01 << 30, - "diss2vs": 0x01 << 31 -} -Fields["DRV_STATUS"] = { - "sg_result": 0x3FF << 0, - "s2vsa": 0x01 << 12, - "s2vsb": 0x01 << 13, - "stealth": 0x01 << 14, - "fsactive": 0x01 << 15, - "csactual": 0xFF << 16, - "stallguard": 0x01 << 24, - "ot": 0x01 << 25, - "otpw": 0x01 << 26, - "s2ga": 0x01 << 27, - "s2gb": 0x01 << 28, - "ola": 0x01 << 29, - "olb": 0x01 << 30, - "stst": 0x01 << 31 -} -Fields["FACTORY_CONF"] = { - "factory_conf": 0x1F << 0 -} -Fields["GCONF"] = { - "recalibrate": 0x01 << 0, - "faststandstill": 0x01 << 1, - "en_pwm_mode": 0x01 << 2, - "multistep_filt": 0x01 << 3, - "shaft": 0x01 << 4, - "diag0_error": 0x01 << 5, - "diag0_otpw": 0x01 << 6, - "diag0_stall": 0x01 << 7, - "diag1_stall": 0x01 << 8, - "diag1_index": 0x01 << 9, - "diag1_onstate": 0x01 << 10, - "diag1_steps_skipped": 0x01 << 11, - "diag0_int_pushpull": 0x01 << 12, - "diag1_poscomp_pushpull": 0x01 << 13, - "small_hysteresis": 0x01 << 14, - "stop_enable": 0x01 << 15, - "direct_mode": 0x01 << 16, - "test_mode": 0x01 << 17 -} -Fields["GSTAT"] = { - "reset": 0x01 << 0, - "drv_err": 0x01 << 1, - "uv_cp": 0x01 << 2 -} -Fields["GLOBALSCALER"] = { - "globalscaler": 0xFF << 0 -} -Fields["IHOLD_IRUN"] = { - "ihold": 0x1F << 0, - "irun": 0x1F << 8, - "iholddelay": 0x0F << 16 -} -Fields["IOIN"] = { - "refl_step": 0x01 << 0, - "refr_dir": 0x01 << 1, - "encb_dcen_cfg4": 0x01 << 2, - "enca_dcin_cfg5": 0x01 << 3, - "drv_enn": 0x01 << 4, - "enc_n_dco_cfg6": 0x01 << 5, - "sd_mode": 0x01 << 6, - "swcomp_in": 0x01 << 7, - "version": 0xFF << 24 -} -Fields["LOST_STEPS"] = { - "lost_steps": 0xfffff << 0 -} -Fields["MSCNT"] = { - "mscnt": 0x3ff << 0 -} -Fields["MSCURACT"] = { - "cur_a": 0x1ff << 0, - "cur_b": 0x1ff << 16 -} -Fields["OTP_READ"] = { - "otp_fclktrim": 0x1f << 0, - "otp_s2_level": 0x01 << 5, - "otp_bbm": 0x01 << 6, - "otp_tbl": 0x01 << 7 -} -Fields["PWM_AUTO"] = { - "pwm_ofs_auto": 0xff << 0, - "pwm_grad_auto": 0xff << 16 -} -Fields["PWMCONF"] = { - "pwm_ofs": 0xFF << 0, - "pwm_grad": 0xFF << 8, - "pwm_freq": 0x03 << 16, - "pwm_autoscale": 0x01 << 18, - "pwm_autograd": 0x01 << 19, - "freewheel": 0x03 << 20, - "pwm_reg": 0x0F << 24, - "pwm_lim": 0x0F << 28 -} -Fields["PWM_SCALE"] = { - "pwm_scale_sum": 0xff << 0, - "pwm_scale_auto": 0x1ff << 16 -} -Fields["TPOWERDOWN"] = { - "tpowerdown": 0xff << 0 -} -Fields["TPWMTHRS"] = { - "tpwmthrs": 0xfffff << 0 -} -Fields["TCOOLTHRS"] = { - "tcoolthrs": 0xfffff << 0 -} -Fields["TSTEP"] = { - "tstep": 0xfffff << 0 -} - -SignedFields = ["cur_a", "cur_b", "sgt", "xactual", "vactual", "pwm_scale_auto"] - -FieldFormatters = dict(tmc2130.FieldFormatters) - - -###################################################################### -# TMC stepper current config helper -###################################################################### - -VREF = 0.325 -MAX_CURRENT = 3.000 - -class TMC5160CurrentHelper: - def __init__(self, config, mcu_tmc): - self.printer = config.get_printer() - self.name = config.get_name().split()[-1] - self.mcu_tmc = mcu_tmc - self.fields = mcu_tmc.get_fields() - run_current = config.getfloat('run_current', - above=0., maxval=MAX_CURRENT) - hold_current = config.getfloat('hold_current', MAX_CURRENT, - above=0., maxval=MAX_CURRENT) - self.req_hold_current = hold_current - self.sense_resistor = config.getfloat('sense_resistor', 0.075, above=0.) - self._set_globalscaler(run_current) - irun, ihold = self._calc_current(run_current, hold_current) - self.fields.set_field("ihold", ihold) - self.fields.set_field("irun", irun) - def _set_globalscaler(self, current): - globalscaler = int((current * 256. * math.sqrt(2.) - * self.sense_resistor / VREF) + .5) - globalscaler = max(32, globalscaler) - if globalscaler >= 256: - globalscaler = 0 - self.fields.set_field("globalscaler", globalscaler) - def _calc_current_bits(self, current): - globalscaler = self.fields.get_field("globalscaler") - if not globalscaler: - globalscaler = 256 - cs = int((current * 256. * 32. * math.sqrt(2.) * self.sense_resistor) - / (globalscaler * VREF) - - 1. + .5) - return max(0, min(31, cs)) - def _calc_current(self, run_current, hold_current): - irun = self._calc_current_bits(run_current) - ihold = self._calc_current_bits(min(hold_current, run_current)) - return irun, ihold - def _calc_current_from_field(self, field_name): - globalscaler = self.fields.get_field("globalscaler") - if not globalscaler: - globalscaler = 256 - bits = self.fields.get_field(field_name) - return (globalscaler * (bits + 1) * VREF - / (256. * 32. * math.sqrt(2.) * self.sense_resistor)) - def get_current(self): - run_current = self._calc_current_from_field("irun") - hold_current = self._calc_current_from_field("ihold") - return run_current, hold_current, self.req_hold_current, MAX_CURRENT - def set_current(self, run_current, hold_current, print_time): - self.req_hold_current = hold_current - irun, ihold = self._calc_current(run_current, hold_current) - self.fields.set_field("ihold", ihold) - val = self.fields.set_field("irun", irun) - self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) - - -###################################################################### -# TMC5160 printer object -###################################################################### - -class TMC5160: - def __init__(self, config): - # Setup mcu communication - self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) - self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields) - # Allow virtual pins to be created - tmc.TMCVirtualPinHelper(config, self.mcu_tmc) - # Register commands - current_helper = TMC5160CurrentHelper(config, self.mcu_tmc) - cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) - cmdhelper.setup_register_dump(ReadRegisters) - self.get_phase_offset = cmdhelper.get_phase_offset - self.get_status = cmdhelper.get_status - # Setup basic register values - tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) - # CHOPCONF - set_config_field = self.fields.set_config_field - set_config_field(config, "toff", 3) - set_config_field(config, "hstrt", 5) - set_config_field(config, "hend", 2) - set_config_field(config, "fd3", 0) - set_config_field(config, "disfdcc", 0) - set_config_field(config, "chm", 0) - set_config_field(config, "tbl", 2) - set_config_field(config, "vhighfs", 0) - set_config_field(config, "vhighchm", 0) - set_config_field(config, "tpfd", 4) - set_config_field(config, "diss2g", 0) - set_config_field(config, "diss2vs", 0) - # COOLCONF - set_config_field(config, "semin", 0) # page 52 - set_config_field(config, "seup", 0) - set_config_field(config, "semax", 0) - set_config_field(config, "sedn", 0) - set_config_field(config, "seimin", 0) - set_config_field(config, "sgt", 0) - set_config_field(config, "sfilt", 0) - # IHOLDIRUN - set_config_field(config, "iholddelay", 6) - # PWMCONF - set_config_field(config, "pwm_ofs", 30) - set_config_field(config, "pwm_grad", 0) - set_config_field(config, "pwm_freq", 0) - set_config_field(config, "pwm_autoscale", True) - set_config_field(config, "pwm_autograd", True) - set_config_field(config, "freewheel", 0) - set_config_field(config, "pwm_reg", 4) - set_config_field(config, "pwm_lim", 12) - # TPOWERDOWN - set_config_field(config, "tpowerdown", 10) - -def load_config_prefix(config): - return TMC5160(config) +# TMC5160 configuration +# +# Copyright (C) 2018-2019 Kevin O'Connor +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import math, logging +from . import bus, tmc, tmc2130 + +TMC_FREQUENCY=12000000. + +Registers = { + "GCONF": 0x00, + "GSTAT": 0x01, + "IFCNT": 0x02, + "SLAVECONF": 0x03, + "IOIN": 0x04, + "X_COMPARE": 0x05, + "OTP_READ": 0x07, + "FACTORY_CONF": 0x08, + "SHORT_CONF": 0x09, + "DRV_CONF": 0x0A, + "GLOBALSCALER": 0x0B, + "OFFSET_READ": 0x0C, + "IHOLD_IRUN": 0x10, + "TPOWERDOWN": 0x11, + "TSTEP": 0x12, + "TPWMTHRS": 0x13, + "TCOOLTHRS": 0x14, + "THIGH": 0x15, + "RAMPMODE": 0x20, + "XACTUAL": 0x21, + "VACTUAL": 0x22, + "VSTART": 0x23, + "A1": 0x24, + "V1": 0x25, + "AMAX": 0x26, + "VMAX": 0x27, + "DMAX": 0x28, + "D1": 0x2A, + "VSTOP": 0x2B, + "TZEROWAIT": 0x2C, + "XTARGET": 0x2D, + "VDCMIN": 0x33, + "SW_MODE": 0x34, + "RAMP_STAT": 0x35, + "XLATCH": 0x36, + "ENCMODE": 0x38, + "X_ENC": 0x39, + "ENC_CONST": 0x3A, + "ENC_STATUS": 0x3B, + "ENC_LATCH": 0x3C, + "ENC_DEVIATION": 0x3D, + "MSLUT0": 0x60, + "MSLUT1": 0x61, + "MSLUT2": 0x62, + "MSLUT3": 0x63, + "MSLUT4": 0x64, + "MSLUT5": 0x65, + "MSLUT6": 0x66, + "MSLUT7": 0x67, + "MSLUTSEL": 0x68, + "MSLUTSTART": 0x69, + "MSCNT": 0x6A, + "MSCURACT": 0x6B, + "CHOPCONF": 0x6C, + "COOLCONF": 0x6D, + "DCCTRL": 0x6E, + "DRV_STATUS": 0x6F, + "PWMCONF": 0x70, + "PWM_SCALE": 0x71, + "PWM_AUTO": 0x72, + "LOST_STEPS": 0x73, +} + +ReadRegisters = [ + "GCONF", "CHOPCONF", "GSTAT", "DRV_STATUS", "FACTORY_CONF", "IOIN", + "LOST_STEPS", "MSCNT", "MSCURACT", "OTP_READ", "PWM_SCALE", + "PWM_AUTO", "TSTEP" +] + +Fields = {} +Fields["COOLCONF"] = { + "semin": 0x0F << 0, + "seup": 0x03 << 5, + "semax": 0x0F << 8, + "sedn": 0x03 << 13, + "seimin": 0x01 << 15, + "sgt": 0x7F << 16, + "sfilt": 0x01 << 24 +} +Fields["CHOPCONF"] = { + "toff": 0x0F << 0, + "hstrt": 0x07 << 4, + "hend": 0x0F << 7, + "fd3": 0x01 << 11, + "disfdcc": 0x01 << 12, + "chm": 0x01 << 14, + "tbl": 0x03 << 15, + "vhighfs": 0x01 << 18, + "vhighchm": 0x01 << 19, + "tpfd": 0x0F << 20, # midrange resonances + "mres": 0x0F << 24, + "intpol": 0x01 << 28, + "dedge": 0x01 << 29, + "diss2g": 0x01 << 30, + "diss2vs": 0x01 << 31 +} +Fields["DRV_CONF"] = { + "bbmtime": 0x1F << 0, + "bbmclks": 0x0F << 8, + "otselect": 0x03 << 16, + "drvstrength": 0x03 << 18, + "filt_isense": 0x03 << 20, +} +Fields["DRV_STATUS"] = { + "sg_result": 0x3FF << 0, + "s2vsa": 0x01 << 12, + "s2vsb": 0x01 << 13, + "stealth": 0x01 << 14, + "fsactive": 0x01 << 15, + "csactual": 0xFF << 16, + "stallguard": 0x01 << 24, + "ot": 0x01 << 25, + "otpw": 0x01 << 26, + "s2ga": 0x01 << 27, + "s2gb": 0x01 << 28, + "ola": 0x01 << 29, + "olb": 0x01 << 30, + "stst": 0x01 << 31 +} +Fields["FACTORY_CONF"] = { + "factory_conf": 0x1F << 0 +} +Fields["GCONF"] = { + "recalibrate": 0x01 << 0, + "faststandstill": 0x01 << 1, + "en_pwm_mode": 0x01 << 2, + "multistep_filt": 0x01 << 3, + "shaft": 0x01 << 4, + "diag0_error": 0x01 << 5, + "diag0_otpw": 0x01 << 6, + "diag0_stall": 0x01 << 7, + "diag1_stall": 0x01 << 8, + "diag1_index": 0x01 << 9, + "diag1_onstate": 0x01 << 10, + "diag1_steps_skipped": 0x01 << 11, + "diag0_int_pushpull": 0x01 << 12, + "diag1_poscomp_pushpull": 0x01 << 13, + "small_hysteresis": 0x01 << 14, + "stop_enable": 0x01 << 15, + "direct_mode": 0x01 << 16, + "test_mode": 0x01 << 17 +} +Fields["GSTAT"] = { + "reset": 0x01 << 0, + "drv_err": 0x01 << 1, + "uv_cp": 0x01 << 2 +} +Fields["GLOBALSCALER"] = { + "globalscaler": 0xFF << 0 +} +Fields["IHOLD_IRUN"] = { + "ihold": 0x1F << 0, + "irun": 0x1F << 8, + "iholddelay": 0x0F << 16 +} +Fields["IOIN"] = { + "refl_step": 0x01 << 0, + "refr_dir": 0x01 << 1, + "encb_dcen_cfg4": 0x01 << 2, + "enca_dcin_cfg5": 0x01 << 3, + "drv_enn": 0x01 << 4, + "enc_n_dco_cfg6": 0x01 << 5, + "sd_mode": 0x01 << 6, + "swcomp_in": 0x01 << 7, + "version": 0xFF << 24 +} +Fields["LOST_STEPS"] = { + "lost_steps": 0xfffff << 0 +} +Fields["MSLUT0"] = { "mslut0": 0xffffffff } +Fields["MSLUT1"] = { "mslut1": 0xffffffff } +Fields["MSLUT2"] = { "mslut2": 0xffffffff } +Fields["MSLUT3"] = { "mslut3": 0xffffffff } +Fields["MSLUT4"] = { "mslut4": 0xffffffff } +Fields["MSLUT5"] = { "mslut5": 0xffffffff } +Fields["MSLUT6"] = { "mslut6": 0xffffffff } +Fields["MSLUT7"] = { "mslut7": 0xffffffff } +Fields["MSLUTSEL"] = { + "x3": 0xFF << 24, + "x2": 0xFF << 16, + "x1": 0xFF << 8, + "w3": 0x03 << 6, + "w2": 0x03 << 4, + "w1": 0x03 << 2, + "w0": 0x03 << 0, +} +Fields["MSLUTSTART"] = { + "start_sin": 0xFF << 0, + "start_sin90": 0xFF << 16, +} +Fields["MSCNT"] = { + "mscnt": 0x3ff << 0 +} +Fields["MSCURACT"] = { + "cur_a": 0x1ff << 0, + "cur_b": 0x1ff << 16 +} +Fields["OTP_READ"] = { + "otp_fclktrim": 0x1f << 0, + "otp_s2_level": 0x01 << 5, + "otp_bbm": 0x01 << 6, + "otp_tbl": 0x01 << 7 +} +Fields["PWM_AUTO"] = { + "pwm_ofs_auto": 0xff << 0, + "pwm_grad_auto": 0xff << 16 +} +Fields["PWMCONF"] = { + "pwm_ofs": 0xFF << 0, + "pwm_grad": 0xFF << 8, + "pwm_freq": 0x03 << 16, + "pwm_autoscale": 0x01 << 18, + "pwm_autograd": 0x01 << 19, + "freewheel": 0x03 << 20, + "pwm_reg": 0x0F << 24, + "pwm_lim": 0x0F << 28 +} +Fields["PWM_SCALE"] = { + "pwm_scale_sum": 0xff << 0, + "pwm_scale_auto": 0x1ff << 16 +} +Fields["TPOWERDOWN"] = { + "tpowerdown": 0xff << 0 +} +Fields["TPWMTHRS"] = { + "tpwmthrs": 0xfffff << 0 +} +Fields["TCOOLTHRS"] = { + "tcoolthrs": 0xfffff << 0 +} +Fields["TSTEP"] = { + "tstep": 0xfffff << 0 +} + +SignedFields = ["cur_a", "cur_b", "sgt", "xactual", "vactual", "pwm_scale_auto"] + +FieldFormatters = dict(tmc2130.FieldFormatters) +FieldFormatters.update({ + "s2vsa": (lambda v: "1(ShortToSupply_A!)" if v else ""), + "s2vsb": (lambda v: "1(ShortToSupply_B!)" if v else ""), +}) + + +###################################################################### +# TMC stepper current config helper +###################################################################### + +VREF = 0.325 +MAX_CURRENT = 10.000 # Maximum dependent on board, but 10 is safe sanity check + +class TMC5160CurrentHelper: + def __init__(self, config, mcu_tmc): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.mcu_tmc = mcu_tmc + self.fields = mcu_tmc.get_fields() + run_current = config.getfloat('run_current', + above=0., maxval=MAX_CURRENT) + hold_current = config.getfloat('hold_current', MAX_CURRENT, + above=0., maxval=MAX_CURRENT) + self.req_hold_current = hold_current + self.sense_resistor = config.getfloat('sense_resistor', 0.075, above=0.) + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + self.fields.set_field("globalscaler", gscaler) + self.fields.set_field("ihold", ihold) + self.fields.set_field("irun", irun) + def _calc_globalscaler(self, current): + globalscaler = int((current * 256. * math.sqrt(2.) + * self.sense_resistor / VREF) + .5) + globalscaler = max(32, globalscaler) + if globalscaler >= 256: + globalscaler = 0 + return globalscaler + def _calc_current_bits(self, current, globalscaler): + if not globalscaler: + globalscaler = 256 + cs = int((current * 256. * 32. * math.sqrt(2.) * self.sense_resistor) + / (globalscaler * VREF) + - 1. + .5) + return max(0, min(31, cs)) + def _calc_current(self, run_current, hold_current): + gscaler = self._calc_globalscaler(run_current) + irun = self._calc_current_bits(run_current, gscaler) + ihold = self._calc_current_bits(min(hold_current, run_current), gscaler) + return gscaler, irun, ihold + def _calc_current_from_field(self, field_name): + globalscaler = self.fields.get_field("globalscaler") + if not globalscaler: + globalscaler = 256 + bits = self.fields.get_field(field_name) + return (globalscaler * (bits + 1) * VREF + / (256. * 32. * math.sqrt(2.) * self.sense_resistor)) + def get_current(self): + run_current = self._calc_current_from_field("irun") + hold_current = self._calc_current_from_field("ihold") + return run_current, hold_current, self.req_hold_current, MAX_CURRENT + def set_current(self, run_current, hold_current, print_time): + self.req_hold_current = hold_current + gscaler, irun, ihold = self._calc_current(run_current, hold_current) + val = self.fields.set_field("globalscaler", gscaler) + self.mcu_tmc.set_register("GLOBALSCALER", val, print_time) + self.fields.set_field("ihold", ihold) + val = self.fields.set_field("irun", irun) + self.mcu_tmc.set_register("IHOLD_IRUN", val, print_time) + + +###################################################################### +# TMC5160 printer object +###################################################################### + +class TMC5160: + def __init__(self, config): + # Setup mcu communication + self.fields = tmc.FieldHelper(Fields, SignedFields, FieldFormatters) + self.mcu_tmc = tmc2130.MCU_TMC_SPI(config, Registers, self.fields, + TMC_FREQUENCY) + # Allow virtual pins to be created + tmc.TMCVirtualPinHelper(config, self.mcu_tmc) + # Register commands + current_helper = TMC5160CurrentHelper(config, self.mcu_tmc) + cmdhelper = tmc.TMCCommandHelper(config, self.mcu_tmc, current_helper) + cmdhelper.setup_register_dump(ReadRegisters) + self.get_phase_offset = cmdhelper.get_phase_offset + self.get_status = cmdhelper.get_status + # Setup basic register values + tmc.TMCWaveTableHelper(config, self.mcu_tmc) + tmc.TMCStealthchopHelper(config, self.mcu_tmc, TMC_FREQUENCY) + set_config_field = self.fields.set_config_field + # GCONF + set_config_field(config, "multistep_filt", True) + # CHOPCONF + set_config_field(config, "toff", 3) + set_config_field(config, "hstrt", 5) + set_config_field(config, "hend", 2) + set_config_field(config, "fd3", 0) + set_config_field(config, "disfdcc", 0) + set_config_field(config, "chm", 0) + set_config_field(config, "tbl", 2) + set_config_field(config, "vhighfs", 0) + set_config_field(config, "vhighchm", 0) + set_config_field(config, "tpfd", 4) + set_config_field(config, "diss2g", 0) + set_config_field(config, "diss2vs", 0) + # COOLCONF + set_config_field(config, "semin", 0) # page 52 + set_config_field(config, "seup", 0) + set_config_field(config, "semax", 0) + set_config_field(config, "sedn", 0) + set_config_field(config, "seimin", 0) + set_config_field(config, "sgt", 0) + set_config_field(config, "sfilt", 0) + # DRV_CONF + set_config_field(config, "drvstrength", 0) + set_config_field(config, "bbmclks", 4) + set_config_field(config, "bbmtime", 0) + set_config_field(config, "filt_isense", 0) + # IHOLDIRUN + set_config_field(config, "iholddelay", 6) + # PWMCONF + set_config_field(config, "pwm_ofs", 30) + set_config_field(config, "pwm_grad", 0) + set_config_field(config, "pwm_freq", 0) + set_config_field(config, "pwm_autoscale", True) + set_config_field(config, "pwm_autograd", True) + set_config_field(config, "freewheel", 0) + set_config_field(config, "pwm_reg", 4) + set_config_field(config, "pwm_lim", 12) + # TPOWERDOWN + set_config_field(config, "tpowerdown", 10) + +def load_config_prefix(config): + return TMC5160(config) diff --git a/klippy/extras/tmc_uart.py b/klippy/extras/tmc_uart.py index fe51303..3c0aa40 100644 --- a/klippy/extras/tmc_uart.py +++ b/klippy/extras/tmc_uart.py @@ -1,252 +1,255 @@ -# Helper code for communicating with TMC stepper drivers via UART -# -# Copyright (C) 2018-2021 Kevin O'Connor -# -# This file may be distributed under the terms of the GNU GPLv3 license. -import logging - - -###################################################################### -# TMC uart analog mux support -###################################################################### - -class MCU_analog_mux: - def __init__(self, mcu, cmd_queue, select_pins_desc): - self.mcu = mcu - self.cmd_queue = cmd_queue - ppins = mcu.get_printer().lookup_object("pins") - select_pin_params = [ppins.lookup_pin(spd, can_invert=True) - for spd in select_pins_desc] - self.oids = [self.mcu.create_oid() for pp in select_pin_params] - self.pins = [pp['pin'] for pp in select_pin_params] - self.pin_values = tuple([-1 for pp in select_pin_params]) - for oid, pin in zip(self.oids, self.pins): - self.mcu.add_config_cmd("config_digital_out oid=%d pin=%s" - " value=0 default_value=0 max_duration=0" - % (oid, pin)) - self.update_pin_cmd = None - self.mcu.register_config_callback(self.build_config) - def build_config(self): - self.update_pin_cmd = self.mcu.lookup_command( - "update_digital_out oid=%c value=%c", cq=self.cmd_queue) - def get_instance_id(self, select_pins_desc): - ppins = self.mcu.get_printer().lookup_object("pins") - select_pin_params = [ppins.parse_pin(spd, can_invert=True) - for spd in select_pins_desc] - for pin_params in select_pin_params: - if pin_params['chip'] != self.mcu: - raise self.mcu.get_printer().config_error( - "TMC mux pins must be on the same mcu") - pins = [pp['pin'] for pp in select_pin_params] - if pins != self.pins: - raise self.mcu.get_printer().config_error( - "All TMC mux instances must use identical pins") - return tuple([not pp['invert'] for pp in select_pin_params]) - def activate(self, instance_id): - for oid, old, new in zip(self.oids, self.pin_values, instance_id): - if old != new: - self.update_pin_cmd.send([oid, new]) - self.pin_values = instance_id - - -###################################################################### -# TMC uart communication -###################################################################### - -# Share mutexes so only one active tmc_uart command on a single mcu at -# a time. This helps limit cpu usage on slower micro-controllers. -class PrinterTMCUartMutexes: - def __init__(self): - self.mcu_to_mutex = {} -def lookup_tmc_uart_mutex(mcu): - printer = mcu.get_printer() - pmutexes = printer.lookup_object('tmc_uart', None) - if pmutexes is None: - pmutexes = PrinterTMCUartMutexes() - printer.add_object('tmc_uart', pmutexes) - mutex = pmutexes.mcu_to_mutex.get(mcu) - if mutex is None: - mutex = printer.get_reactor().mutex() - pmutexes.mcu_to_mutex[mcu] = mutex - return mutex - -TMC_BAUD_RATE = 40000 -TMC_BAUD_RATE_AVR = 9000 - -# Code for sending messages on a TMC uart -class MCU_TMC_uart_bitbang: - def __init__(self, rx_pin_params, tx_pin_params, select_pins_desc): - self.mcu = rx_pin_params['chip'] - self.mutex = lookup_tmc_uart_mutex(self.mcu) - self.pullup = rx_pin_params['pullup'] - self.rx_pin = rx_pin_params['pin'] - self.tx_pin = tx_pin_params['pin'] - self.oid = self.mcu.create_oid() - self.cmd_queue = self.mcu.alloc_command_queue() - self.analog_mux = None - if select_pins_desc is not None: - self.analog_mux = MCU_analog_mux(self.mcu, self.cmd_queue, - select_pins_desc) - self.instances = {} - self.tmcuart_send_cmd = None - self.mcu.register_config_callback(self.build_config) - def build_config(self): - baud = TMC_BAUD_RATE - mcu_type = self.mcu.get_constants().get("MCU", "") - if mcu_type.startswith("atmega") or mcu_type.startswith("at90usb"): - baud = TMC_BAUD_RATE_AVR - bit_ticks = self.mcu.seconds_to_clock(1. / baud) - self.mcu.add_config_cmd( - "config_tmcuart oid=%d rx_pin=%s pull_up=%d tx_pin=%s bit_time=%d" - % (self.oid, self.rx_pin, self.pullup, self.tx_pin, bit_ticks)) - self.tmcuart_send_cmd = self.mcu.lookup_query_command( - "tmcuart_send oid=%c write=%*s read=%c", - "tmcuart_response oid=%c read=%*s", oid=self.oid, - cq=self.cmd_queue, is_async=True) - def register_instance(self, rx_pin_params, tx_pin_params, - select_pins_desc, addr): - if (rx_pin_params['pin'] != self.rx_pin - or tx_pin_params['pin'] != self.tx_pin - or (select_pins_desc is None) != (self.analog_mux is None)): - raise self.mcu.get_printer().config_error( - "Shared TMC uarts must use the same pins") - instance_id = None - if self.analog_mux is not None: - instance_id = self.analog_mux.get_instance_id(select_pins_desc) - if (instance_id, addr) in self.instances: - raise self.mcu.get_printer().config_error( - "Shared TMC uarts need unique address or select_pins polarity") - self.instances[(instance_id, addr)] = True - return instance_id - def _calc_crc8(self, data): - # Generate a CRC8-ATM value for a bytearray - crc = 0 - for b in data: - for i in range(8): - if (crc >> 7) ^ (b & 0x01): - crc = (crc << 1) ^ 0x07 - else: - crc = (crc << 1) - crc &= 0xff - b >>= 1 - return crc - def _add_serial_bits(self, data): - # Add serial start and stop bits to a message in a bytearray - out = 0 - pos = 0 - for d in data: - b = (d << 1) | 0x200 - out |= (b << pos) - pos += 10 - res = bytearray() - for i in range((pos+7)//8): - res.append((out >> (i*8)) & 0xff) - return res - def _encode_read(self, sync, addr, reg): - # Generate a uart read register message - msg = bytearray([sync, addr, reg]) - msg.append(self._calc_crc8(msg)) - return self._add_serial_bits(msg) - def _encode_write(self, sync, addr, reg, val): - # Generate a uart write register message - msg = bytearray([sync, addr, reg, (val >> 24) & 0xff, - (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff]) - msg.append(self._calc_crc8(msg)) - return self._add_serial_bits(msg) - def _decode_read(self, reg, data): - # Extract a uart read response message - if len(data) != 10: - return None - # Convert data into a long integer for easy manipulation - mval = pos = 0 - for d in bytearray(data): - mval |= d << pos - pos += 8 - # Extract register value - val = ((((mval >> 31) & 0xff) << 24) | (((mval >> 41) & 0xff) << 16) - | (((mval >> 51) & 0xff) << 8) | ((mval >> 61) & 0xff)) - # Verify start/stop bits and crc - encoded_data = self._encode_write(0x05, 0xff, reg, val) - if data != encoded_data: - return None - return val - def reg_read(self, instance_id, addr, reg): - if self.analog_mux is not None: - self.analog_mux.activate(instance_id) - msg = self._encode_read(0xf5, addr, reg) - params = self.tmcuart_send_cmd.send([self.oid, msg, 10]) - return self._decode_read(reg, params['read']) - def reg_write(self, instance_id, addr, reg, val, print_time=None): - minclock = 0 - if print_time is not None: - minclock = self.mcu.print_time_to_clock(print_time) - if self.analog_mux is not None: - self.analog_mux.activate(instance_id) - msg = self._encode_write(0xf5, addr, reg | 0x80, val) - self.tmcuart_send_cmd.send([self.oid, msg, 0], minclock=minclock) - -# Lookup a (possibly shared) tmc uart -def lookup_tmc_uart_bitbang(config, max_addr): - ppins = config.get_printer().lookup_object("pins") - rx_pin_params = ppins.lookup_pin(config.get('uart_pin'), can_pullup=True, - share_type="tmc_uart_rx") - tx_pin_desc = config.get('tx_pin', None) - if tx_pin_desc is None: - tx_pin_params = rx_pin_params - else: - tx_pin_params = ppins.lookup_pin(tx_pin_desc, share_type="tmc_uart_tx") - if rx_pin_params['chip'] is not tx_pin_params['chip']: - raise ppins.error("TMC uart rx and tx pins must be on the same mcu") - select_pins_desc = config.getlist('select_pins', None) - addr = config.getint('uart_address', 0, minval=0, maxval=max_addr) - mcu_uart = rx_pin_params.get('class') - if mcu_uart is None: - mcu_uart = MCU_TMC_uart_bitbang(rx_pin_params, tx_pin_params, - select_pins_desc) - rx_pin_params['class'] = mcu_uart - instance_id = mcu_uart.register_instance(rx_pin_params, tx_pin_params, - select_pins_desc, addr) - return instance_id, addr, mcu_uart - -# Helper code for communicating via TMC uart -class MCU_TMC_uart: - def __init__(self, config, name_to_reg, fields, max_addr=0): - self.printer = config.get_printer() - self.name = config.get_name().split()[-1] - self.name_to_reg = name_to_reg - self.fields = fields - self.ifcnt = None - self.instance_id, self.addr, self.mcu_uart = lookup_tmc_uart_bitbang( - config, max_addr) - self.mutex = self.mcu_uart.mutex - def get_fields(self): - return self.fields - def _do_get_register(self, reg_name): - reg = self.name_to_reg[reg_name] - if self.printer.get_start_args().get('debugoutput') is not None: - return 0 - for retry in range(5): - val = self.mcu_uart.reg_read(self.instance_id, self.addr, reg) - if val is not None: - return val - raise self.printer.command_error( - "Unable to read tmc uart '%s' register %s" % (self.name, reg_name)) - def get_register(self, reg_name): - with self.mutex: - return self._do_get_register(reg_name) - def set_register(self, reg_name, val, print_time=None): - reg = self.name_to_reg[reg_name] - if self.printer.get_start_args().get('debugoutput') is not None: - return - with self.mutex: - for retry in range(5): - ifcnt = self.ifcnt - if ifcnt is None: - self.ifcnt = ifcnt = self._do_get_register("IFCNT") - self.mcu_uart.reg_write(self.instance_id, self.addr, reg, val, - print_time) - self.ifcnt = self._do_get_register("IFCNT") - if self.ifcnt == (ifcnt + 1) & 0xff: - return - raise self.printer.command_error( - "Unable to write tmc uart '%s' register %s" % (self.name, reg_name)) +# Helper code for communicating with TMC stepper drivers via UART +# +# Copyright (C) 2018-2021 Kevin O'Connor +# +# This file may be distributed under the terms of the GNU GPLv3 license. +import logging + + +###################################################################### +# TMC uart analog mux support +###################################################################### + +class MCU_analog_mux: + def __init__(self, mcu, cmd_queue, select_pins_desc): + self.mcu = mcu + self.cmd_queue = cmd_queue + ppins = mcu.get_printer().lookup_object("pins") + select_pin_params = [ppins.lookup_pin(spd, can_invert=True) + for spd in select_pins_desc] + self.oids = [self.mcu.create_oid() for pp in select_pin_params] + self.pins = [pp['pin'] for pp in select_pin_params] + self.pin_values = tuple([-1 for pp in select_pin_params]) + for oid, pin in zip(self.oids, self.pins): + self.mcu.add_config_cmd("config_digital_out oid=%d pin=%s" + " value=0 default_value=0 max_duration=0" + % (oid, pin)) + self.update_pin_cmd = None + self.mcu.register_config_callback(self.build_config) + def build_config(self): + self.update_pin_cmd = self.mcu.lookup_command( + "update_digital_out oid=%c value=%c", cq=self.cmd_queue) + def get_instance_id(self, select_pins_desc): + ppins = self.mcu.get_printer().lookup_object("pins") + select_pin_params = [ppins.parse_pin(spd, can_invert=True) + for spd in select_pins_desc] + for pin_params in select_pin_params: + if pin_params['chip'] != self.mcu: + raise self.mcu.get_printer().config_error( + "TMC mux pins must be on the same mcu") + pins = [pp['pin'] for pp in select_pin_params] + if pins != self.pins: + raise self.mcu.get_printer().config_error( + "All TMC mux instances must use identical pins") + return tuple([not pp['invert'] for pp in select_pin_params]) + def activate(self, instance_id): + for oid, old, new in zip(self.oids, self.pin_values, instance_id): + if old != new: + self.update_pin_cmd.send([oid, new]) + self.pin_values = instance_id + + +###################################################################### +# TMC uart communication +###################################################################### + +# Share mutexes so only one active tmc_uart command on a single mcu at +# a time. This helps limit cpu usage on slower micro-controllers. +class PrinterTMCUartMutexes: + def __init__(self): + self.mcu_to_mutex = {} +def lookup_tmc_uart_mutex(mcu): + printer = mcu.get_printer() + pmutexes = printer.lookup_object('tmc_uart', None) + if pmutexes is None: + pmutexes = PrinterTMCUartMutexes() + printer.add_object('tmc_uart', pmutexes) + mutex = pmutexes.mcu_to_mutex.get(mcu) + if mutex is None: + mutex = printer.get_reactor().mutex() + pmutexes.mcu_to_mutex[mcu] = mutex + return mutex + +TMC_BAUD_RATE = 40000 +TMC_BAUD_RATE_AVR = 9000 + +# Code for sending messages on a TMC uart +class MCU_TMC_uart_bitbang: + def __init__(self, rx_pin_params, tx_pin_params, select_pins_desc): + self.mcu = rx_pin_params['chip'] + self.mutex = lookup_tmc_uart_mutex(self.mcu) + self.pullup = rx_pin_params['pullup'] + self.rx_pin = rx_pin_params['pin'] + self.tx_pin = tx_pin_params['pin'] + self.oid = self.mcu.create_oid() + self.cmd_queue = self.mcu.alloc_command_queue() + self.analog_mux = None + if select_pins_desc is not None: + self.analog_mux = MCU_analog_mux(self.mcu, self.cmd_queue, + select_pins_desc) + self.instances = {} + self.tmcuart_send_cmd = None + self.mcu.register_config_callback(self.build_config) + def build_config(self): + baud = TMC_BAUD_RATE + mcu_type = self.mcu.get_constants().get("MCU", "") + if mcu_type.startswith("atmega") or mcu_type.startswith("at90usb"): + baud = TMC_BAUD_RATE_AVR + bit_ticks = self.mcu.seconds_to_clock(1. / baud) + self.mcu.add_config_cmd( + "config_tmcuart oid=%d rx_pin=%s pull_up=%d tx_pin=%s bit_time=%d" + % (self.oid, self.rx_pin, self.pullup, self.tx_pin, bit_ticks)) + self.tmcuart_send_cmd = self.mcu.lookup_query_command( + "tmcuart_send oid=%c write=%*s read=%c", + "tmcuart_response oid=%c read=%*s", oid=self.oid, + cq=self.cmd_queue, is_async=True) + def register_instance(self, rx_pin_params, tx_pin_params, + select_pins_desc, addr): + if (rx_pin_params['pin'] != self.rx_pin + or tx_pin_params['pin'] != self.tx_pin + or (select_pins_desc is None) != (self.analog_mux is None)): + raise self.mcu.get_printer().config_error( + "Shared TMC uarts must use the same pins") + instance_id = None + if self.analog_mux is not None: + instance_id = self.analog_mux.get_instance_id(select_pins_desc) + if (instance_id, addr) in self.instances: + raise self.mcu.get_printer().config_error( + "Shared TMC uarts need unique address or select_pins polarity") + self.instances[(instance_id, addr)] = True + return instance_id + def _calc_crc8(self, data): + # Generate a CRC8-ATM value for a bytearray + crc = 0 + for b in data: + for i in range(8): + if (crc >> 7) ^ (b & 0x01): + crc = (crc << 1) ^ 0x07 + else: + crc = (crc << 1) + crc &= 0xff + b >>= 1 + return crc + def _add_serial_bits(self, data): + # Add serial start and stop bits to a message in a bytearray + out = 0 + pos = 0 + for d in data: + b = (d << 1) | 0x200 + out |= (b << pos) + pos += 10 + res = bytearray() + for i in range((pos+7)//8): + res.append((out >> (i*8)) & 0xff) + return res + def _encode_read(self, sync, addr, reg): + # Generate a uart read register message + msg = bytearray([sync, addr, reg]) + msg.append(self._calc_crc8(msg)) + return self._add_serial_bits(msg) + def _encode_write(self, sync, addr, reg, val): + # Generate a uart write register message + msg = bytearray([sync, addr, reg, (val >> 24) & 0xff, + (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff]) + msg.append(self._calc_crc8(msg)) + return self._add_serial_bits(msg) + def _decode_read(self, reg, data): + # Extract a uart read response message + if len(data) != 10: + return None + # Convert data into a long integer for easy manipulation + mval = pos = 0 + for d in bytearray(data): + mval |= d << pos + pos += 8 + # Extract register value + val = ((((mval >> 31) & 0xff) << 24) | (((mval >> 41) & 0xff) << 16) + | (((mval >> 51) & 0xff) << 8) | ((mval >> 61) & 0xff)) + # Verify start/stop bits and crc + encoded_data = self._encode_write(0x05, 0xff, reg, val) + if data != encoded_data: + return None + return val + def reg_read(self, instance_id, addr, reg): + if self.analog_mux is not None: + self.analog_mux.activate(instance_id) + msg = self._encode_read(0xf5, addr, reg) + params = self.tmcuart_send_cmd.send([self.oid, msg, 10]) + return self._decode_read(reg, params['read']) + def reg_write(self, instance_id, addr, reg, val, print_time=None): + minclock = 0 + if print_time is not None: + minclock = self.mcu.print_time_to_clock(print_time) + if self.analog_mux is not None: + self.analog_mux.activate(instance_id) + msg = self._encode_write(0xf5, addr, reg | 0x80, val) + self.tmcuart_send_cmd.send([self.oid, msg, 0], minclock=minclock) + +# Lookup a (possibly shared) tmc uart +def lookup_tmc_uart_bitbang(config, max_addr): + ppins = config.get_printer().lookup_object("pins") + rx_pin_params = ppins.lookup_pin(config.get('uart_pin'), can_pullup=True, + share_type="tmc_uart_rx") + tx_pin_desc = config.get('tx_pin', None) + if tx_pin_desc is None: + tx_pin_params = rx_pin_params + else: + tx_pin_params = ppins.lookup_pin(tx_pin_desc, share_type="tmc_uart_tx") + if rx_pin_params['chip'] is not tx_pin_params['chip']: + raise ppins.error("TMC uart rx and tx pins must be on the same mcu") + select_pins_desc = config.getlist('select_pins', None) + addr = config.getint('uart_address', 0, minval=0, maxval=max_addr) + mcu_uart = rx_pin_params.get('class') + if mcu_uart is None: + mcu_uart = MCU_TMC_uart_bitbang(rx_pin_params, tx_pin_params, + select_pins_desc) + rx_pin_params['class'] = mcu_uart + instance_id = mcu_uart.register_instance(rx_pin_params, tx_pin_params, + select_pins_desc, addr) + return instance_id, addr, mcu_uart + +# Helper code for communicating via TMC uart +class MCU_TMC_uart: + def __init__(self, config, name_to_reg, fields, max_addr, tmc_frequency): + self.printer = config.get_printer() + self.name = config.get_name().split()[-1] + self.name_to_reg = name_to_reg + self.fields = fields + self.ifcnt = None + self.instance_id, self.addr, self.mcu_uart = lookup_tmc_uart_bitbang( + config, max_addr) + self.mutex = self.mcu_uart.mutex + self.tmc_frequency = tmc_frequency + def get_fields(self): + return self.fields + def _do_get_register(self, reg_name): + reg = self.name_to_reg[reg_name] + if self.printer.get_start_args().get('debugoutput') is not None: + return 0 + for retry in range(5): + val = self.mcu_uart.reg_read(self.instance_id, self.addr, reg) + if val is not None: + return val + raise self.printer.command_error( + "Unable to read tmc uart '%s' register %s" % (self.name, reg_name)) + def get_register(self, reg_name): + with self.mutex: + return self._do_get_register(reg_name) + def set_register(self, reg_name, val, print_time=None): + reg = self.name_to_reg[reg_name] + if self.printer.get_start_args().get('debugoutput') is not None: + return + with self.mutex: + for retry in range(5): + ifcnt = self.ifcnt + if ifcnt is None: + self.ifcnt = ifcnt = self._do_get_register("IFCNT") + self.mcu_uart.reg_write(self.instance_id, self.addr, reg, val, + print_time) + self.ifcnt = self._do_get_register("IFCNT") + if self.ifcnt == (ifcnt + 1) & 0xff: + return + raise self.printer.command_error( + "Unable to write tmc uart '%s' register %s" % (self.name, reg_name)) + def get_tmc_frequency(self): + return self.tmc_frequency diff --git a/klippy/extras/tmc_uart.pyc b/klippy/extras/tmc_uart.pyc deleted file mode 100644 index 079bedec87c7fc2f9c36d2a0685996aec11cdfdd..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 10820 zcmb_i-)|h(dA+l{TyiN=zi3HjWGfpxv}xCloK~sRRzE4#YJh5!4kas5EsuvYBWlRy z?sD#|O*&#*go>LcEsVUhD4O;^$Wzb)eaJ&z@{|I7XkUXq76l3vDB9Qbob$~tDLFMD zF+Yd* zyUu;%PT2bTJOAo2tq)TU9dd#J> z<9kzlu*k11z=X$_cax-mSUKFSwni+BMPcgxi_qcx(7?axk`dTThrAH#(|D zkV@Un^Zqw=f6A4uag!M~NgL|^cbp3+JMFeExbl$3x2H_G-5Q?yl6$A-cBb4;OZV_> z$Q$#Wat~VWUd^4v0Kw+Z+--=B105bUJEF=_J|MuopjlPi#Aq5P)kw%-tY?xuW&aGx;G$`_3iAl`jyxZ@u4+l|y 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self.current_file.close() self.current_file = None + self.lines = 0 self.print_stats.note_cancel() self.file_position = self.file_size = 0. # G-Code commands @@ -232,16 +236,20 @@ class VirtualSD: partial_input = "" lines = [] error_message = None + plr_file = open("/home/mks/scripts/plr/plr_record", 'w', buffering=0) while not self.must_pause_work: if not lines: # Read more data try: data = self.current_file.read(8192) except: + plr_file.close() logging.exception("virtual_sdcard read") break if not data: # End of file + self.lines = 0 + plr_file.close() self.current_file.close() self.current_file = None logging.info("Finished SD card print") @@ -263,6 +271,13 @@ class VirtualSD: next_file_position = self.file_position + len(line) + 1 self.next_file_position = next_file_position try: + self.lines += 1 + if self.lines % self.save_every_n_lines == 0: + # temp = "SAVE_VARIABLE VARIABLE=gcode_lines VALUE=" + str(self.lines) + # self.gcode._process_commands([temp], need_ack=False) + plr_file.seek(0) + plr_file.write(str(self.lines)) + plr_file.truncate() self.gcode.run_script(line) except self.gcode.error as e: error_message = str(e) @@ -287,6 +302,7 @@ class VirtualSD: lines = [] partial_input = "" logging.info("Exiting SD card print (position %d)", self.file_position) + plr_file.close() self.work_timer = None self.cmd_from_sd = False if error_message is not None: @@ -296,6 +312,16 @@ class VirtualSD: else: self.print_stats.note_complete() return self.reactor.NEVER + # cmd_TOGGLE_PLR_help = "enable or disable power lose resume" + # def cmd_TOGGLE_PLR(self, gcmd): + # if self.plr_enable: + # self.plr_enable = False + # temp = "SAVE_VARIABLE VARIABLE=plr_enable VALUE=" + str(self.plr_enable) + # self.gcode._process_commands([temp], need_ack=False) + # gcmd.respond_raw("Power lose resume disabled") + # else: + # self.plr_enable = True + # gcmd.respond_raw("Power lose resume enabled") def load_config(config): return VirtualSD(config) diff --git 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zhCClpblHsTrh2z(JdVl`mam`|@jR=uyC@!|-5HjBcjL2v;NLIq$dOHMstyd1zm5C6 zvLLd!&#Z0Qi|BA^2hY6z|4Ei#L_I~O-(u_n1M#}km(gzS_q(gN{ygj4W^jjri$J^q z%S-Pqc?w}^wZs7}t}4CFEg_HFM5CRCJL=wl9a-wMM+~^Ri5m#6Jm1!EXifE2;XRgeM--%kXK?|rF{dxJ zg<5?j)*)W6Ww=>MDbF8xMi=&A@g+8==QDf1$f?O&H5{JPs9Fb5YPD0D7~UO#WOk+x z8*!6ts~e%W$Syb|R#56G42O2Bc#qJ_f8w)0L|_2TCjrc71e}+gW55h!fbRT<+vNgZ z_2_$^fdXMWU-7wNvQjyt~*2W?z6``$NDL0%tucNr5Y-C%5+!6pN0i{330 zm3x-KV+Pk4e8k`t2G<$9%HRfr?=$!TgTG)vUxxSB49F($#|-|K!KV!Vj=|qEAUC@( zL}I_+D?P7>o_K#{>72wJzgs$9>KmCW4VC&z{iOoF0mKWXA#l4NU#T=$Dwawk(+Gk5MhGr12^aY#iiHyOjH!S6Q%5qR;j>RZOIf{F~XsE6qc z`qw8PyH;#Vrg3Z|&p-jif^fasuBTxW59wi}ym!z>SmXUPr|!^n4xy*pDpGF@ATBpl Pmv}!_7%NQv#+?5@U9y -# This file may be distributed under the terms of the GNU GPLv3 license. - -""" -[x_twist_compensation] -horizontal_move_z: 10 -speed: 50 -start_x: 0 ; nozzle's x coordinate at the start of the calibration ! required -end_x: 200 ; nozzle's x coordinate at the end of the calibration ! required -y: 100 ; nozzle's y coordinate during the calibration ! required -""" - -import logging -import math -from . import manual_probe as ManualProbe, bed_mesh as BedMesh - -DEFAULT_N_POINTS = 3 -DEFAULT_PROFILE_NAME = 'default' -BED_MESH_CONFIG_NAME = 'bed_mesh' - - -class Config: - # values stored in printer.cfg when a profile is saved - DEFAULT_SPEED = 50. - DEFAULT_HORIZONTAL_MOVE_Z = 10. - REQUIRED = True - OPTIONAL = False - CONFIG_OPTIONS = { - 'horizontal_move_z': (float, OPTIONAL, DEFAULT_HORIZONTAL_MOVE_Z), - 'speed': (float, OPTIONAL, DEFAULT_SPEED), - 'start_x': (float, REQUIRED, None), - 'end_x': (float, REQUIRED, None), - 'y': (float, REQUIRED, None) - } - - -class XTwistCompensation: - def __init__(self, config): - # get printer - self.printer = config.get_printer() - - # get values from [x_twist_compensation] section in printer .cfg - for config_key, \ - (config_type, required, default) in Config.CONFIG_OPTIONS.items(): - value = None - if config_type == float: - value = config.getfloat(config_key, default) - else: - value = config.get(config_key, default) - if required and value is None: - raise config.error( - "Missing required config option for section [{}]: {}" - .format(config.get_name(), config_key)) - setattr(self, config_key, value) - - # setup persistent storage - self.pmgr = ProfileManager(config, self) - - # setup calibrater - calibrater_config = { - 'horizontal_move_z': self.horizontal_move_z - if hasattr(self, 'horizontal_move_z') else None, - 'speed': self.speed if hasattr(self, 'speed') else None, - 'start_x': self.start_x if hasattr(self, 'start_x') else None, - 'end_x': self.end_x if hasattr(self, 'end_x') else None, - 'y': self.y if hasattr(self, 'y') else None - } - self.calibrater = Calibrater( - config, self.pmgr, calibrater_config) - - self.enabled = False - - # register gcode handlers - self._register_gcode_handlers() - - def _register_gcode_handlers(self): - # register gcode handlers - self.gcode = self.printer.lookup_object('gcode') - self.gcode.register_command( - 'X_TWIST_COMPENSATE_MESH', - self.cmd_X_TWIST_COMPENSATE_MESH, - desc=self.cmd_X_TWIST_COMPENSATE_MESH_help) - self.gcode.register_command( - 'X_TWIST_COMPENSATE_STATUS', - self.cmd_X_TWIST_COMPENSATE_STATUS, - desc=self.cmd_X_TWIST_COMPENSATE_STATUS_help) - - def get_z_compensation_value(self, x_coord, optional_profile_name=None): - # returns the (lineraly interpolated) z compensation value - # for the given x coordinate - # uses the current profile if optional_profile_name is not specified - enabled = self.pmgr.get_is_enabled() - if enabled or optional_profile_name is not None: - current_profile = \ - self.pmgr.get_current_profile() \ - if optional_profile_name is None \ - else self.pmgr.get_profile(optional_profile_name) - z_compensations = current_profile.z_compensations - n_points = len(z_compensations) - spacing = (self.end_x - self.start_x) / (n_points - 1) - interpolate_t = (x_coord - self.start_x) / spacing - interpolate_i = int(math.floor(interpolate_t)) - interpolate_i = BedMesh.constrain(interpolate_i, 0, n_points - 2) - interpolate_t -= interpolate_i - interpolated_z_compensation = BedMesh.lerp( - interpolate_t, z_compensations[interpolate_i], - z_compensations[interpolate_i + 1]) - return interpolated_z_compensation - else: - return 0 - - cmd_X_TWIST_COMPENSATE_MESH_help = \ - "Compensate a mesh by applying the x" \ - "twist compensation to the given raw mesh" - - def cmd_X_TWIST_COMPENSATE_MESH(self, gcmd): - # get the mesh name from the gcode command - raw_mesh_name = gcmd.get('MESH_NAME', None) - Helpers.check_non_empty_param(raw_mesh_name, gcmd, 'MESH_NAME') - - # get the compensation profile name from the gcode command - compensation_name = gcmd.get('COMPENSATION_NAME', None) - Helpers.check_non_empty_param( - compensation_name, gcmd, 'COMPENSATION_NAME') - - # get the bed_mesh object, then the bed_mesh profile manager - bed_mesh = self.printer.lookup_object('bed_mesh', None) - if not bed_mesh: - raise gcmd.error( - "[bed_mesh] is not specified in your printer configuration") - bed_mesh_pmgr = bed_mesh.pmgr - # load specified bed mesh as active bed mesh - bed_mesh_pmgr.load_profile(raw_mesh_name) - # get the active bed mesh - active_bed_mesh = bed_mesh.get_mesh() - # modify the probed matrix by applying the x twist compensation - #modified_probed_matrix = self._modify_probed_matrix( - # active_bed_mesh, compensation_name) - - enabled = self.pmgr.get_is_enabled() - if enabled or compensation_name is not None: - current_profile = \ - self.pmgr.get_current_profile() \ - if compensation_name is None \ - else self.pmgr.get_profile(compensation_name) - z_compensations = current_profile.z_compensations - modified_probed_matrix = self._modify_probed_matrix_XY(active_bed_mesh, z_compensations[0], z_compensations[1]) - - # update active mesh with modified probed matrix, save under new name - #compensated_mesh_name = \ - # raw_mesh_name + '_compensated_' + compensation_name - active_bed_mesh.build_mesh(modified_probed_matrix) - #bed_mesh_pmgr.save_profile(compensated_mesh_name) - bed_mesh_pmgr.save_profile(raw_mesh_name) - - def _modify_probed_matrix_XY(self, bed_mesh, xz, yz): - - probed_matrix = bed_mesh.get_probed_matrix() - compensated_matrix = [] - row_count = len(probed_matrix) - 1 - yz_step = yz / row_count - col_count = len(probed_matrix[0]) - 1 - xz_step = xz / col_count - - for row_index in range(len(probed_matrix)): - compensated_row = [] - row = probed_matrix[row_index] - for col_index in range(len(row)): - z = row[col_index] - compensated_z = z + (xz_step * col_index) + (yz_step * row_index) - compensated_row.append(compensated_z) - compensated_matrix.append(compensated_row) - - compensated_matrix = tuple(tuple(row) for row in compensated_matrix) - return compensated_matrix - - def _modify_probed_matrix(self, bed_mesh, compensation_profile_name): - # do compensating, by modifying z values in probed matrix - # probed matrix is a list of rows of probed z values - # eg. probed_matrix[0][0] = bottom left corner of mesh, z value - probed_matrix = bed_mesh.get_probed_matrix() - compensated_matrix = [] - for row_index in range(len(probed_matrix)): - compensated_row = [] - row = probed_matrix[row_index] - for col_index in range(len(row)): - z = row[col_index] - x_coord = self._get_mesh_point_x_coord(col_index, bed_mesh) - compensated_z = z + \ - self.get_z_compensation_value( - x_coord, compensation_profile_name) - compensated_row.append(compensated_z) - compensated_matrix.append(compensated_row) - # compensated_matrix is a list of list - # bed_mesh expects tuple of tuple hence convert - compensated_matrix = tuple(tuple(row) for row in compensated_matrix) - return compensated_matrix - - def _get_mesh_point_x_coord(self, col_index, mesh): - # returns the x coordinate of the given column index - # in the probed matrix - x_min = mesh.mesh_x_min - x_range = mesh.mesh_x_max - mesh.mesh_x_min - x_step = x_range / (len(mesh.probed_matrix[0]) - 1) - return x_min + col_index * x_step - - cmd_X_TWIST_COMPENSATE_STATUS_help = \ - "Get the status of the x twist compensation" - - def cmd_X_TWIST_COMPENSATE_STATUS(self, gcmd): - if (self.pmgr.get_is_enabled()): - profile = self.pmgr.get_current_profile() - profile_name = profile.name - profile_z_compensations = profile.z_compensations - profile_recommended_z_offset = profile.recommended_z_offset - gcmd.respond_info( - """ - X twist compensation is enabled - Profile name: {} - Profile z compensations: {} - Profile recommended z offset: {} - """.format(profile_name, - profile_z_compensations, profile_recommended_z_offset)) - else: - gcmd.respond_info( - "X twist compensation is disabled, "\ - "load a profile using X_TWIST_PROFILE_LOAD" - ) - - -class Calibrater: - def __init__(self, config, pmgr, calibrater_config): - # setup self attributes - self.printer = config.get_printer() - self.gcode = self.printer.lookup_object('gcode') - self.pmgr = pmgr - self.probe = None - # probe settings are set to none, until they are available - self.lift_speed, self.probe_x_offset, self.probe_y_offset, \ - self.stored_probe_z_offset = None, None, None, None - self.printer.register_event_handler("klippy:connect", - self._handle_connect(config)) - self.speed = calibrater_config['speed'] - self.horizontal_move_z = calibrater_config['horizontal_move_z'] - self.start_point = ( - calibrater_config['start_x'], calibrater_config['y']) - self.end_point = (calibrater_config['end_x'], calibrater_config['y']) - self.results = [] - self.current_point_index = None - self.gcmd = None - - # register gcode handlers - self._register_gcode_handlers() - - def _handle_connect(self, config): - # gets probe settings when they are available - def callback(): - self.probe = self.printer.lookup_object('probe', None) - if (self.probe is None): - raise config.error( - "X_TWIST_COMPENSATION requires [probe] to be defined") - self.lift_speed = self.probe.get_lift_speed() - self.probe_x_offset, self.probe_y_offset, \ - self.stored_probe_z_offset = self.probe.get_offsets() - return callback - - def _register_gcode_handlers(self): - # register gcode handlers - self.gcode = self.printer.lookup_object('gcode') - self.gcode.register_command( - 'X_TWIST_CALIBRATE', self.cmd_X_TWIST_CALIBRATE, - desc=self.cmd_X_TWIST_CALIBRATE_help) - - cmd_X_TWIST_CALIBRATE_help = """ - Performs the x twist calibration wizard - Measure z probe offset at n points along the x axis, - and calculate x twist compensation - Specify PROFILE_NAME= - optional, default is 'default' - """ - - def cmd_X_TWIST_CALIBRATE(self, gcmd): - self.gcmd = gcmd - # performs the x twist calibration wizard - # get params from command - profile_name = gcmd.get('PROFILE_NAME', DEFAULT_PROFILE_NAME) - n_points = gcmd.get_int('N_POINTS', DEFAULT_N_POINTS) - - # check for valid profile_name - Helpers.check_non_empty_param(profile_name, self.gcmd, 'PROFILE_NAME') - # check for valid n_points - if n_points is None or n_points < 3: - raise self.gcmd.error( - "N_POINTS to probe must be at least 3") - - # clear the current profile - self.pmgr.clear_profile() - - # calculate some values - x_range = self.end_point[0] - self.start_point[0] - interval_dist = x_range / (n_points - 1) - nozzle_points = self._calculate_nozzle_points(n_points, interval_dist) - probe_points = self._calculate_probe_points( - nozzle_points, self.probe_x_offset, self.probe_y_offset) - - # verify no other manual probe is in progress - ManualProbe.verify_no_manual_probe(self.printer) - - # begin calibration - self.current_point_index = 0 - self._calibration( - profile_name, probe_points, nozzle_points, interval_dist) - - def _calculate_nozzle_points(self, n_points, interval_dist): - # calculate the points to put the probe at, returned as a list of tuples - nozzle_points = [] - for i in range(n_points): - x = self.start_point[0] + i * interval_dist - y = self.start_point[1] - nozzle_points.append((x, y)) - return nozzle_points - - def _calculate_probe_points(self, nozzle_points, - probe_x_offset, probe_y_offset): - # calculate the points to put the nozzle at - # returned as a list of tuples - probe_points = [] - for point in nozzle_points: - x = point[0] - probe_x_offset - y = point[1] - probe_y_offset - probe_points.append((x, y)) - return probe_points - - def _move_helper(self, target_coordinates, override_speed=None): - # pad target coordinates - target_coordinates = \ - (target_coordinates[0], target_coordinates[1], None) \ - if len(target_coordinates) == 2 else target_coordinates - toolhead = self.printer.lookup_object('toolhead') - speed = self.speed if target_coordinates[2] == None else self.lift_speed - speed = override_speed if override_speed is not None else speed - toolhead.manual_move(target_coordinates, speed) - - def _calibration(self, profile_name, probe_points, nozzle_points, interval): - # begin the calibration process - self.gcmd.respond_info("X_TWIST_CALIBRATE: Probing point %d of %d" % ( - self.current_point_index + 1, len(probe_points))) - - # horizontal_move_z (to prevent probe trigger or hitting bed) - self._move_helper((None, None, self.horizontal_move_z)) - - # move to point to probe - self._move_helper((probe_points[self.current_point_index] - [0], probe_points[self.current_point_index][1], None)) - - # probe the point - self.probe.run_probe(self.gcmd) - - # horizontal_move_z (to prevent probe trigger or hitting bed) - self._move_helper((None, None, self.horizontal_move_z)) - - # move the nozzle over the probe point - self._move_helper((nozzle_points[self.current_point_index])) - - # start the manual (nozzle) probe - ManualProbe.ManualProbeHelper( - self.printer, self.gcmd, - self._manual_probe_callback_factory(profile_name, - probe_points, nozzle_points, interval)) - - def _manual_probe_callback_factory(self, profile_name, probe_points, - nozzle_points, interval): - # returns a callback function for the manual probe - is_end = self.current_point_index == len(probe_points) - 1 - - def callback(kin_pos): - if kin_pos is None: - # probe was cancelled - self.gcmd.respond_info( - "X_TWIST_CALIBRATE: Probe cancelled, calibration aborted") - return - z_offset = self.stored_probe_z_offset - kin_pos[2] - self.results.append(z_offset) - if is_end: - # end of calibration - self._finalize_calibration(profile_name) - else: - # move to next point - self.current_point_index += 1 - self._calibration( - profile_name, probe_points, nozzle_points, interval) - return callback - - def _finalize_calibration(self, profile_name): - # finalize the calibration process - # calculate average of results - avg = sum(self.results) / len(self.results) - # subtract average from each result - # so that they are independent of z_offset - self.results = [avg - x for x in self.results] - # create a new profile using profile manager - self.pmgr.create_profile(profile_name, self.results, avg) - # recommend z offset to user - self.gcmd.respond_info( - "X_TWIST_CALIBRATE: Calibration complete, reccomended z_offset: %f" - % (avg)) - - -class Profile: - PROFILE_OPTIONS = { - 'z_compensations': str, 'recommended_z_offset': float - } - - def __init__(self, name, z_compensations, recommended_z_offset): - self.name = name - self.z_compensations = z_compensations - self.recommended_z_offset = recommended_z_offset - - -class ProfileManager: - def __init__(self, config, x_twist_compensation): - # setup self attributes - self.name = config.get_name() - self.printer = config.get_printer() - self.x_twist_compensation = x_twist_compensation - self.profiles = {} - self.gcode = self.printer.lookup_object('gcode') - self.current_profile = None - - # fetch the stored profiles - self._fetch_stored_profiles(config) - logging.info('stored profiles: %s', self.profiles) - - # register gcode handlers - self._register_gcode_handlers() - - def get_is_enabled(self): - # returns - return self.current_profile is not None - - def get_current_profile(self): - # return the current profile - if self.current_profile is None: - raise self.gcode.error( - "No X_TWIST_PROFILE loaded") - return self.current_profile - - def get_profiles(self): - # dictionary of profiles loaded from printer.cfg, key is profile name - return self.profiles - - def get_profile(self, profile_name): - # attempt to get profile from self.profiles - # throws error if profile does not exist or is corrupt - logging.info('attempting to get profile name %s', profile_name) - logging.info('available profiles: %s', self.profiles) - profile = self.profiles.get(profile_name, None) - if profile is None: - raise self.gcode.error( - "X_TWIST_PROFILE %s does not exist" % (profile_name)) - z_compensations = profile.get('z_compensations', None) - if z_compensations is None: - raise self.gcode.error( - "X_TWIST_PROFILE %s does not have z_compensations" - % (profile_name)) - recommended_z_offset = profile.get('recommended_z_offset', None) - if recommended_z_offset is None: - raise self.gcode.error( - "X_TWIST_PROFILE %s does not have recommended_z_offset" - % (profile_name)) - return Profile(profile_name, z_compensations, recommended_z_offset) - - def _fetch_stored_profiles(self, config): - # fetch stored profiles in printer.cfg - # (using prefix of "x_twist_compensation"") - stored_profiles = config.get_prefix_sections(self.name) - stored_profiles = [ - stored_profile for stored_profile in stored_profiles - if stored_profile.get_name() != self.name - ] - # add stored profiles to self.profiles - for stored_profile in stored_profiles: - prefixed_name = stored_profile.get_name() - # remove prefix from name - name = prefixed_name.split(' ', 1)[1] - self.profiles[name] = {} - for option, option_type in Profile.PROFILE_OPTIONS.items(): - if option_type == float: - self.profiles[name][option] = stored_profile.getfloat( - option) - elif option_type == str: - value = stored_profile.get(option) - if option == 'z_compensations': - self.profiles[name][option] = \ - Helpers.parse_comma_separated_floats(value) - else: - self.profiles[name][option] = stored_profile.get( - option) - - def _register_gcode_handlers(self): - # register gcode handlers - self.gcode.register_command( - 'X_TWIST_PROFILE', self.cmd_X_TWIST_PROFILE, - desc=self.cmd_X_TWIST_PROFILE_help) - self.gcode.register_command( - 'X_TWIST_PROFILE_LOAD', self.cmd_X_TWIST_PROFILE_LOAD, - desc=self.cmd_X_TWIST_PROFILE_LOAD_help) - self.gcode.register_command( - 'X_TWIST_PROFILE_SAVE', self.cmd_X_TWIST_PROFILE_SAVE, - desc=self.cmd_X_TWIST_PROFILE_SAVE_help) - self.gcode.register_command( - 'X_TWIST_PROFILE_DELETE', self.cmd_X_TWIST_PROFILE_DELETE, - desc=self.cmd_X_TWIST_PROFILE_DELETE_help) - self.gcode.register_command( - 'X_TWIST_PROFILE_CLEAR', self.cmd_X_TWIST_PROFILE_CLEAR, - desc=self.cmd_X_TWIST_PROFILE_CLEAR_help) - - def create_profile(self, profile_name, z_compensations, - recommended_z_offset): - # create a new profile - new_profile = Profile( - profile_name, z_compensations, recommended_z_offset) - # save the profile - self._save_profile(new_profile) - - def load_profile(self, profile_name): - # set the current profile - self.current_profile = self.get_profile(profile_name) - - def clear_profile(self): - # clear the current profile - self.current_profile = None - - def delete_profile(self, profile_name): - # try getting the profile to ensure it exists - self.get_profile(profile_name) - # remove the profile from config file - configfile = self.printer.lookup_object('configfile') - configfile.remove_section('%s %s' % (self.name, profile_name)) - # remove the profile from self.profiles - profiles = dict(self.profiles) - del profiles[profile_name] - self.profiles = profiles - # inform user to save deletion - self.gcode.respond_info( - "Profile [%s] removed from storage for this session.\n" - "The SAVE_CONFIG command will update the printer\n" - "configuration and restart the printer" % (profile_name)) - - def _save_profile(self, profile): - profile_name = profile.name - config_name = '%s %s' % (self.name, profile_name) - configfile = self.printer.lookup_object('configfile') - # save the profile to config file - # also save to self.profiles, make sure immutable by making a copy - profiles = dict(self.profiles) - profiles[profile_name] = new_profile = {} - for option, option_type in Profile.PROFILE_OPTIONS.items(): - value = getattr(profile, option) - if option_type == float: - value = float(value) - new_profile[option] = value # save to self.profiles - configfile.set(config_name, option, - Helpers.format_float_to_n_decimals(value)) - elif option_type == str: - if option == 'z_compensations': - # convert to list of floats - value = [float(x) for x in value] - new_profile[option] = value # save to self.profiles - value_as_str = [Helpers.format_float_to_n_decimals( - x) for x in value] # convert to list of strs - configfile.set(config_name, option, ', '.join( - value_as_str)) # store as comma separated - else: - new_profile[option] = value # save to self.profiles - configfile.set(config_name, option, value) - # inform user to save changes - self.gcode.respond_info( - "X_TWIST_COMPENSATION state has been saved to profile [%s]\n" - "for the current session. The SAVE_CONFIG command will\n" - "update the printer config file and restart the printer." - % (profile_name)) - - def save_current_profile(self, profile_name): - # get the current profile - profile = self.get_current_profile() - # set the name - profile.name = profile_name - # save the profile - self._save_profile(profile) - - cmd_X_TWIST_PROFILE_LOAD_help = \ - "Loads a saved mesh as the active mesh" - - def cmd_X_TWIST_PROFILE_LOAD(self, gcmd): - # loads a saved mesh as the active mesh - profile_name = gcmd.get('NAME', None) - Helpers.check_non_empty_param(profile_name, gcmd, 'NAME') - self.load_profile(profile_name) - - cmd_X_TWIST_PROFILE_CLEAR_help = \ - "Clears the active mesh" - - def cmd_X_TWIST_PROFILE_CLEAR(self, gcmd): - # clears the active mesh - self.clear_profile() - - cmd_X_TWIST_PROFILE_SAVE_help = \ - "Saves the active mesh to the config file" - - def cmd_X_TWIST_PROFILE_SAVE(self, gcmd): - # saves the active mesh to the config file - profile_name = gcmd.get('NAME', None) - Helpers.check_non_empty_param(profile_name, gcmd, 'NAME') - self.save_current_profile(profile_name) - - cmd_X_TWIST_PROFILE_DELETE_help = \ - "Deletes a saved profile from the config file" - - def cmd_X_TWIST_PROFILE_DELETE(self, gcmd): - # deletes a saved mesh from the config file - profile_name = gcmd.get('NAME', None) - Helpers.check_non_empty_param(profile_name, gcmd, 'NAME') - self.delete_profile(profile_name) - - cmd_X_TWIST_PROFILE_help = \ - "Prints information on how to use the X_TWIST_PROFILE command" - - def cmd_X_TWIST_PROFILE(self, gcmd): - raise self.gcode.error( - """ - Please follow the following syntax: - X_TWIST_PROFILE_LOAD NAME= - X_TWIST_PROFILE_SAVE NAME= - X_TWIST_PROFILE_DELETE NAME= - X_TWIST_PROFILE_CLEAR - """ - ) - - -class Helpers: - @staticmethod - def format_float_to_n_decimals(raw_float, n=6): - # format float to n decimals, defaults to 6 - return "{:.{}f}".format(raw_float, n) - - @staticmethod - def parse_comma_separated_floats(comma_separated_floats): - # parse comma separated floats into list of floats - return [float(value) for value in comma_separated_floats.split(', ')] - - @staticmethod - def check_non_empty_param(param_str, gcmd, param_name=None): - # throws gcmd error if parameter is None or just spaces - if param_str is None or not param_str.strip(): - error = "Parameter [%s] is required" % ( - param_name) if param_name else "Parameter is required" - raise gcmd.error(error) - -# klipper's entry point using [x_twist_compensation] section in printer.cfg - - -def load_config(config): - return XTwistCompensation(config) \ No newline at end of file diff --git a/klippy/extras/x_twist_compensation.pyc b/klippy/extras/x_twist_compensation.pyc deleted file mode 100644 index c5813f5f550e89f6c45cb662d8a9ddbcd139dd67..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 22006 zcmc&+Yj9j=dH&As>awzA$&zJDxsVfMCxSW`LKBE_XdFpNOl{d5i8xUrPS?9f*4nFG zdC!q8Id&m9C4ot&os!bhPTL=p!c2#uP$*OS1Im<^mfl-BZ7I{~Oqs&Z4*gyFJkNX1 z?n;&ejFhSD^X+%O`{ljA-*@ugAL#qetJO-`rGI(+K8h#)8iI;*^9Vgx$+?>6<`J=Y z&dujsCGRQ)SIfKQf}8Jh%iV6i$9a`5H{a_jcqzI{kDKpv6}*nRO3}UO+;!)kncw9q zNZscuyIM*8u7dyjU1gw^G~g<`U1iKw23tvZA99s(SJ~4_8g!LmSGmPiMp{WIvX?LO zdpPddiCa0H5zo24XV=2yay3rEa$|WVs>h|I+Ndw|Ej60eD~)C`)hu=(P&nx^->b~rNmE`B3~u_#-d)z zrCRlDQ+@b%`pxL#YPA_v`l5P;Z9Q=R4{Z%4e@I*F9O;I3);mX4S#4J9=U!_t)gRz* zri#UJ6FCG)KZ4~_eHCl5(rlcKl3pa7jVj@C6fac?9Z3&@O0-y7tt9~~Cfx`o8}-HN zxfU1|kn|Xy_!5E$djYsX2%rHNsK-Tlw+N8RxrfsCoZj>H-bH9) zeqqyl*QWPw_Yi9R-jVX;so?nhshPQBC&H7b zo|+El6E4(TbJf;4n11(rjt8j2(L7$N#g=^P^xW}NGsjLSd9l_gC8{>ls7J|el$<;@ z^Z4;6LMt{qffUyc;uY_`VCZ>dH#gwBPmnqP3)1itpPBFYaAg54hj^ z@x*%(bmzJ~`+fx~rZ$FXD3*o8`H+ zPq-xK&gb3v0x8ne!mIANoV%8D&*j}U{4cm`7>RS&y4}@0;rl|)HJ?>0J??7GUF~w$ zQNG*Nhn3j7A@OR#H9zjIViwL_=v5ruW8?_?RDKtGMLTHZy5~ONxwRq08JPTr!#t`TTBowTCm|!1uXizanEA z?>Oi0VZgH!BqlTQTM?eD#xbc?MkqnZNK*X93aPZe*l7B3R95`i=dUds@t?mI6i_eV zP6wnx0UHar`4hJwNC*$-q6CDjT2G>;FguM4vV#$pV)begEyn?2IUsouhNGt8S{^BQ zF=EhcHku-M7|${gk-f1GQUfC$QG(>A5c71iu~@A|CrkCxIrPubt}LIkfh?84ev;-* zry#;InX(X6CY{MRO4JMn@v8o!dg*K}sw87b2%FJ4U}Dq^&y^dMC|oMlE48Q@ixjH+ zII1mb__ny#s@6HY5Up#)EGJCXSB&~(`wRsobrdp*tyst=6ka z7~YM3;(HOe++aTM9RLmL_eOKW-ms|An721SoX_X(@a*4#Tpqc_e3=xRPm2(o!3)s= z|0T!(^$43nt@9!WKq?j}kP0zEH1GuFmR(RP5Zkf=-pCdhvy&Muj#eJf4zd`|ojE=` z7fzl!d3t(g_SoEXcyfC7N$o==ip$~*TNIj|J2v+oV_(5Ov?HEUYcwvbu7r)V=Ya#k zJxm@#(AscFG+^76gu+gFxe{*Ct~&Q$J3m~CYAea@H!oy^OAh?75^89I>mM9KurqKG z97Izm@x(+`mmBqpULH?h`dcQd66+(E)V_MUU?!p~c2sD7xnNvN%Zf z(X24Yr*m~tTEYu9UZfhF0n{CE0sa6qA|LR?B~S*O0b#EjBjxwp*eIx>QEw&oxY299 zE-5s@Hd6ZCc~E+A2vL7P*BIy~GEfMqZ)ZIe0YSxk7n8>A2i@!+XHl?~ zJ~xZ%vx3F~W^F=U6){&O=1!1e1a}}1X(G+4#$if5MEVkvL#CHko6V?Bx+(J2K}YSK zEnV3lL&phMz82Mu1atY70=g@32c=vRc7URSev(c<7FA9{q{M;%U>o%qatKOuGL($r2F#Om@;0lA@aQ;@1z9NX=n779p z^~M4I-FWtRgNu`=ynY+Ipr8tVs(3gKcX;e$tShaIShOs{75- zWz{Sba)?kZB6@F2ngZ|v*dPc%ZZc_#!i!N>$S)>x0VLBxkfTIIfqpCmbYdal7Vrr$ zpOzDb#g|#=yaYkuh)GDqydGj6fFCGj80j&!NNlCBCNzYQ#aCcokBh%Vd`Hv7^zUbJ zVEQ++!ji>OOz&~$`&ou)i4J;+mOw*DXKWexhc1AnUBEy5bh`}qy4`t@3UupXN*LTw zHaK*gia3IEQs8jr*vV-z&lX>RaIaKpQ}M%C?q@TNYr(I^P&pGHx=FdZSdA)vweGJs zR-1k*$)sY^swtX=?4?}L^+>;>g5C?=t<)x^6A*?s*VYIxGtcNS5W@%ac zCU^@gQGzmZL6s0nN2Ns%h)o1l!d5`_B6vFk4&2a9vItb7>LS{u776vSlr*br;nUAZ zrSan2j&;p515&75+JD#P12I^(E+|j1UPRM&XzBfxJ9y1g5-!! zvJBCSV5&7@@>vZSE4*>YJA>Wp5773^m>D)?4+4NMF8GJqn$4g3ek8gP5}1Mg68@BV8* zid|H*t_}({E`HFRA$lMISO;9WxBwkT($r#C$01 z05cc%xNDwEv@&SnDet0Cepcegj6yM=WObz$nVEyl+wzqZ#dj?~~ z6+!xj)})QMsCooWKx3lD^;{_7NfgmelAz;Ad*#eMBnafb@R=<~UGk?U}3~D&02mCJDhnbY@p>II9fSZYc?x2fXnT$t z2Y?EtQM3!>cXon=a;8HhVC&+)
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e4f6df5..5b87832 100644 --- a/klippy/gcode.py +++ b/klippy/gcode.py @@ -9,6 +9,11 @@ class CommandError(Exception): pass Coord = collections.namedtuple('Coord', ('x', 'y', 'z', 'e')) +priority_queue = [] +set_gcode_offset_r = re.compile( + r'^\s*SET_GCODE_OFFSET(?:\s+[a-zA-Z_]+=[+-]?\d*\.?\d+)*\s+MOVE=1(?:\s+[a-zA-Z_]+=[+-]?\d*\.?\d+)*(?:\s|$)', + re.IGNORECASE + ) class GCodeCommand: error = CommandError @@ -111,6 +116,8 @@ class GCodeDispatch: func = getattr(self, 'cmd_' + cmd) desc = getattr(self, 'cmd_' + cmd + '_help', None) self.register_command(cmd, func, True, desc) + # Gcode macro interupt + self.break_flag=False def is_traditional_gcode(self, cmd): # A "traditional" g-code command is a letter and followed by a number try: @@ -138,6 +145,13 @@ class GCodeDispatch: self.base_gcode_handlers[cmd] = func if desc is not None: self.gcode_help[cmd] = desc + def remove_command(self, cmd): + if cmd in self.ready_gcode_handlers: + del self.ready_gcode_handlers[cmd] + if cmd in self.base_gcode_handlers: + del self.base_gcode_handlers[cmd] + else: + raise self.printer.config_error("Gcode command '%s' not registered" % cmd) def register_mux_command(self, cmd, key, value, func, desc=None): prev = self.mux_commands.get(cmd) if prev is None: @@ -176,6 +190,45 @@ class GCodeDispatch: for line in commands: # Ignore comments and leading/trailing spaces line = origline = line.strip() + # Gcode macro interupt + if self.break_flag: + if str(line) != "CANCEL_PRINT": + continue + else: + self.break_flag = False + self.printer.lookup_object("heaters").break_flag = False + while priority_queue: + priority_command = priority_queue.pop(0) + # self.respond_info("priority: {}".format(priority_command)) + cpos = priority_command.find(';') + if cpos >= 0: + priority_command = priority_command[:cpos] + parts = self.args_r.split(priority_command.upper()) + numparts = len(parts) + cmd = "" + if numparts >= 3 and parts[1] != 'N': + cmd = parts[1] + parts[2].strip() + elif numparts >= 5 and parts[1] == 'N': + cmd = parts[3] + parts[4].strip() + params = { parts[i]: parts[i+1].strip() + for i in range(1, numparts, 2) } + gcmd = GCodeCommand(self, cmd, priority_command, params, need_ack) + handler = self.gcode_handlers.get(cmd, self.cmd_default) + try: + handler(gcmd) + except self.error as e: + self._respond_error(str(e)) + self.printer.send_event("gcode:command_error") + if not need_ack: + raise + except: + msg = 'Internal error on command:"%s"' % (cmd,) + logging.exception(msg) + self.printer.invoke_shutdown(msg) + self._respond_error(msg) + if not need_ack: + raise + gcmd.ack() cpos = line.find(';') if cpos >= 0: line = line[:cpos] @@ -212,8 +265,16 @@ class GCodeDispatch: def run_script_from_command(self, script): self._process_commands(script.split('\n'), need_ack=False) def run_script(self, script): + lines = script.split('\n') + temp_lines = [] + for line in lines: + if set_gcode_offset_r.match(line) is not None: + priority_queue.append(line) + else: + temp_lines.append(line) + lines = temp_lines with self.mutex: - self._process_commands(script.split('\n'), need_ack=False) + self._process_commands(lines, need_ack=False) def get_mutex(self): return self.mutex def create_gcode_command(self, command, commandline, params): diff --git a/klippy/gcode.pyc b/klippy/gcode.pyc deleted file mode 100644 index 1db50b4e8470ab72e3fbc09a5e29654deb3535af..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 20076 zcmb_kdyHJySwDAXU$b7@+uiuFu@jG-Y`jk5SDHuTI&qSw7qz#piThfqNgEvQfdRa>AuiXv!%KR}}V ze!uVDJL7dy?KJi7J$vqXpYMF{^Ihk^w{h^BpS}=OUGlFFe;>mW{T7k{zn-f*Hjzte^(FASDQh2V0qPNdkz|L_&zW0#h=M$vlYZ#$`z%n zN*?rM)RDDPDU<(^xxLZrxBIrimn&IDX(g5%n8Rqdb!xN`DR zuQkG$04pz7T9u_JE->E+!=PNLE~;rOjFy{?pj>OrHRBDaP77L<%Qkus3Zt+-r$f_; zYRGgx_UW9CD@tbLiKmmb@n(G}li*;jQH#sv&0GSp*?9%~$qji`LLhwvSMC%*U1)=c z)jl^ZaQPgk>xFQG^I@FAbQ@lU#%}#9APK#L6>!-dE8wY){Sd3*M&7|Hw%)i3L#Z$h zThWd+iy?LA@#s+g7#Ta1Yrt_}F_@y~u6r)po4)4w+Pa^wpwuGTHLOq0T?0Af+(Mo# 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b/klippy/klippy.py @@ -90,6 +90,19 @@ class Printer: raise self.config_error( "Printer object '%s' already created" % (name,)) self.objects[name] = obj + def remove_object(self, name): + if name not in self.objects: + raise self.config_error("Printer object '%s' not found" % (name,)) + del self.objects[name] + def swap_object(self, name1, name2): + if name1 not in self.objects or name2 not in self.objects: + raise self.config_error("Printer object '%s' or '%s' not found" % (name1, name2)) + self.objects[name1], self.objects[name2] = self.objects[name2], self.objects[name1] + def copy_object(self, name, new_name): + if name not in self.objects: + raise self.config_error("Object '%s' not found" % name) + new_obj = self.objects[name] + self.objects[new_name] = new_obj def lookup_object(self, name, default=configfile.sentinel): if name in self.objects: return self.objects[name] @@ -129,6 +142,11 @@ class Printer: raise self.config_error("Unable to load module '%s'" % (section,)) self.objects[section] = init_func(config.getsection(section)) return self.objects[section] + def unload_object(self, section): + if section in self.objects: + del self.objects[section] + else: + raise self.config_error("Object '%s' not found" % section) def _read_config(self): self.objects['configfile'] = pconfig = configfile.PrinterConfig(self) config = pconfig.read_main_config() diff --git a/klippy/mathutil.pyc b/klippy/mathutil.pyc deleted file mode 100644 index 27f9ed8dfa27d82cd9f57a2e70887614549566ed..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 4598 zcmcInL2nz!6@Eiflt@vQBFUE2pon1D4S@i%<+N#?3bp|^?M+SA1yl$Q7OUM6wG_Ea z?JgC`AWMArOm{y@F!Hf#C5;Rn3Nzhbbj!2%gXMrmG7e3p56=D-* z3gt0M`hgM2L`FuQ8yN$o;mnc9_t>t=s8WvABs0>T|-b_$OuDs1z4 zRSed9(x!{IeYjQ_8a0$BDCruiP`&%%ygFMQ|I3OT)iH_c9Ta>%d)Vfq&Dj~Njk_6b z4!p$cyOGzo`8c{Hy@l$|LEN`@`iJSA!(KQT*d%|R-syYU!7vMZ8-vr77Pf-W&-}PQ zc(BO1wB5)}JdWce2qQ1E>w!&u8)fTZ6lS5Wo{r_*BO%0x&YUi%b@IT48eh+{g=&7pN=pqAL3!7$ZLu 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zg`0LCHw1GAWHaE=9o_?@?&3X$y+eDO){gt<8v2fuc7ZZApF1jc@_&&ze4PJF%z<1z z#_GejFS3RVrC(<5OHAHi@@*zvK+`6NI4Y4PbrtXIF!5Jei*oJ%Bg^o)SC_(WO^v{ z6Y5FWiCb;{9wW-Ga1#JOFoBNs$Pbdw(Nr~~f0DVMWAX(in!PmVKj2Y^#l1@oC~-b_ zO6tI;-22~Q@?9i7zESS(@k2oLto``-Lu5l;gL=>#Ej?J8Do?!aj!zt`?5iC4U#xKm AT>t<8 diff --git a/klippy/stepper.py b/klippy/stepper.py index ad7d128..3ffa3a4 100644 --- a/klippy/stepper.py +++ b/klippy/stepper.py @@ -5,6 +5,7 @@ # This file may be distributed under the terms of the GNU GPLv3 license. import math, logging, collections import chelper +from extras.homing import Homing class error(Exception): pass @@ -299,6 +300,9 @@ class PrinterRail: self.steppers = [] self.endstops = [] self.endstop_map = {} + # Reverse homing + self.endstops_reverse = [] + self.endstop_map_reverse = {} self.add_extra_stepper(config) mcu_stepper = self.steppers[0] self.get_name = mcu_stepper.get_name @@ -354,6 +358,21 @@ class PrinterRail: raise config.error( "Invalid homing_positive_dir / position_endstop in '%s'" % (config.get_name(),)) + # Reverse homing + if self.get_name() == "stepper_z": + if config.get('endstop_pin_reverse', None): + self.reversed = False + self.position_endstop_reverse = config.getfloat("position_endstop_reverse") + self.homing_positive_dir_reverse = config.getboolean('homing_positive_dir_reverse') + self.homing_speed_reverse = config.getfloat('homing_speed_reverse', self.homing_speed, above=0.) + self.homing_retract_dist_reverse = 0 + self.printer = config.get_printer() + self.gcode = self.printer.lookup_object('gcode') + self.printer.register_event_handler("klippy:ready", self.handle_ready) + self.printer.register_event_handler("homing:home_rails_end", self.handle_reverse_home_rails_end) + def handle_ready(self): + gcode = self.printer.lookup_object('gcode') + gcode.register_command("REVERSE_HOMING", self.cmd_REVERSE_HOMING) def get_range(self): return self.position_min, self.position_max def get_homing_info(self): @@ -371,6 +390,23 @@ class PrinterRail: def add_extra_stepper(self, config): stepper = PrinterStepper(config, self.stepper_units_in_radians) self.steppers.append(stepper) + # logging.info("%s begin to add stepper" % (stepper._name)) + if stepper._name == "stepper_z" or stepper._name == "stepper_z1": + endstop_pin_reverse = config.get('endstop_pin_reverse', None) + # logging.info("%s begin to add mcu endstop" % (stepper._name)) + # logging.info(endstop_pin_reverse) + if endstop_pin_reverse: + printer = config.get_printer() + ppins = printer.lookup_object('pins') + pin_params = ppins.parse_pin(endstop_pin_reverse, True, True) + pin_name = "%s:%s" % (pin_params['chip_name'], pin_params['pin']) + mcu_endstop_reverse = ppins.setup_pin('endstop', endstop_pin_reverse) + self.endstop_map_reverse[pin_name] = {'endstop': mcu_endstop_reverse, + 'invert': pin_params['invert'], + 'pullup': pin_params['pullup']} + name = stepper.get_name(short=True) + self.endstops_reverse.append((mcu_endstop_reverse, name)) + mcu_endstop_reverse.add_stepper(stepper) if self.endstops and config.get('endstop_pin', None) is None: # No endstop defined - use primary endstop self.endstops[0][0].add_stepper(stepper) @@ -402,6 +438,36 @@ class PrinterRail: "must specify the same pullup/invert settings" % ( self.get_name(), pin_name)) mcu_endstop.add_stepper(stepper) + def homing_params_switch(self): + self.reversed = not self.reversed + self.endstop_map, self.endstop_map_reverse = self.endstop_map_reverse, self.endstop_map + self.endstops, self.endstops_reverse = self.endstops_reverse, self.endstops + self.position_endstop, self.position_endstop_reverse = self.position_endstop_reverse, self.position_endstop + self.homing_positive_dir, self.homing_positive_dir_reverse = self.homing_positive_dir_reverse, self.homing_positive_dir + self.homing_retract_dist, self.homing_retract_dist_reverse = self.homing_retract_dist_reverse, self.homing_retract_dist + self.homing_speed, self.homing_speed_reverse = self.homing_speed_reverse, self.homing_speed + # logging.info("homing_params_switch") + # logging.info(str(list(self.endstop_map))) + # logging.info(str(self.endstops)) + # logging.info(self.position_endstop) + # logging.info(self.homing_positive_dir) + # logging.info(self.homing_retract_dist) + def cmd_REVERSE_HOMING(self, gcmd): + self.homing_params_switch() + try: + homing_state = Homing(self.printer) + homing_state.set_axes([2]) + kin = self.printer.lookup_object('toolhead').get_kinematics() + kin.home(homing_state) + except self.printer.command_error: + if self.printer.is_shutdown(): + raise self.printer.command_error( + "Homing failed due to printer shutdown") + self.printer.lookup_object('stepper_enable').motor_off() + raise + def handle_reverse_home_rails_end(self, homing_state, rails): + if self.reversed: + self.homing_params_switch() def setup_itersolve(self, alloc_func, *params): for stepper in self.steppers: stepper.setup_itersolve(alloc_func, *params) diff --git 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self.buffer_time_low = config.getfloat( 'buffer_time_low', 1.000, above=0.) self.buffer_time_high = config.getfloat( - 'buffer_time_high', 2.000, above=self.buffer_time_low) + 'buffer_time_high', 10.000, above=self.buffer_time_low) self.buffer_time_start = config.getfloat( 'buffer_time_start', 0.250, above=0.) self.move_flush_time = config.getfloat( @@ -268,12 +269,44 @@ class ToolHead: gcode.register_command('SET_VELOCITY_LIMIT', self.cmd_SET_VELOCITY_LIMIT, desc=self.cmd_SET_VELOCITY_LIMIT_help) + # Change z velocity + gcode.register_command('SET_Z_VELOCITY_LIMIT', + self.cmd_SET_Z_VELOCITY_LIMIT, + desc=self.cmd_SET_Z_VELOCITY_LIMIT_help) + gcode.register_command('SET_Z_ACCEL_LIMIT', + self.cmd_SET_Z_ACCEL_LIMIT, + desc=self.cmd_SET_Z_ACCEL_LIMIT_help) + gcode.register_command('M204', self.cmd_M204) # Load some default modules modules = ["gcode_move", "homing", "idle_timeout", "statistics", "manual_probe", "tuning_tower"] for module_name in modules: self.printer.load_object(config, module_name) + + # Change z velocity + cmd_SET_Z_VELOCITY_LIMIT_help = "Change z velocity limit, parameter VALUE" + def cmd_SET_Z_VELOCITY_LIMIT(self, gcmd): + kin = self.get_kinematics() + value = gcmd.get_float('VALUE', None, above=0.) + # gcmd.respond_info('Z velocity before change: ' + str(kin.max_z_velocity)) + if value: + kin.max_z_velocity = value + else: + gcmd.respond_info("Value given is illegal") + # gcmd.respond_info('Z velocity after change: ' + str(kin.max_z_velocity)) + + cmd_SET_Z_ACCEL_LIMIT_help = "Change z accel, parameter VALUE" + def cmd_SET_Z_ACCEL_LIMIT(self, gcmd): + kin = self.get_kinematics() + value = gcmd.get_float('VALUE', None, above=0.) + # gcmd.respond_info('Z accel before change: ' + str(kin.max_z_accel)) + if value: + kin.max_z_accel = value + else: + gcmd.respond_info("Value given is illegal") + # gcmd.respond_info('Z accel after change: ' + str(kin.max_z_accel)) + # Print time tracking def _update_move_time(self, next_print_time): batch_time = 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disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * * Neither the name of the copyright holders nor the names of - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - ****************************************************************************/ - - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 0 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION -// is at least 8 digits long. -// -#define COMPONENT_VERSION 00010000 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 50 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.0" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2016-09-15 13:24:20" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - +/***************************************************************************** + * + * Copyright (C) 2016 Atmel Corporation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * + * * Neither the name of the copyright holders nor the names of + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 0 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version, with leading zeros. The COMPONENT_VERSION +// is at least 8 digits long. +// +#define COMPONENT_VERSION 00010000 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 50 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.0" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2016-09-15 13:24:20" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/lib/samd21/samd21a/gcc/system_samd21.c b/lib/samd21/samd21a/gcc/system_samd21.c index d8287b9..05a18f9 100644 --- a/lib/samd21/samd21a/gcc/system_samd21.c +++ b/lib/samd21/samd21a/gcc/system_samd21.c @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd21.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (1000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd21.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (1000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/lib/samd21/samd21a/include/component-version.h b/lib/samd21/samd21a/include/component-version.h index d58a259..ed7de37 100644 --- a/lib/samd21/samd21a/include/component-version.h +++ b/lib/samd21/samd21a/include/component-version.h @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 3 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version. -// -#define COMPONENT_VERSION 10003 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 304 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.3" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2018-05-23 09:26:19" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 3 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10003 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 304 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.3" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2018-05-23 09:26:19" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/lib/samd21/samd21a/include/component/ac.h b/lib/samd21/samd21a/include/component/ac.h index ac5923f..53dd4a5 100644 --- a/lib/samd21/samd21a/include/component/ac.h +++ b/lib/samd21/samd21a/include/component/ac.h @@ -1,545 +1,545 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_AC_COMPONENT_ -#define _SAMD21_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_AC Analog Comparators */ -/*@{*/ - -#define AC_U2205 -#define REV_AC 0x111 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :4; /*!< bit: 3.. 6 Reserved */ - uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ -#define AC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << AC_CTRLA_RUNSTDBY_Pos) -#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) -#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ -#define AC_CTRLA_LPMUX (_U_(0x1) << AC_CTRLA_LPMUX_Pos) -#define AC_CTRLA_MASK _U_(0x87) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ - uint16_t :6; /*!< bit: 10..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ -#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ -#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_MASK _U_(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :5; /*!< bit: 2.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ -#define AC_STATUSB_SYNCBUSY (_U_(0x1) << AC_STATUSB_SYNCBUSY_Pos) -#define AC_STATUSB_MASK _U_(0x83) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSC_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ -#define AC_STATUSC_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ - -#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ -#define AC_STATUSC_STATE0 (_U_(1) << AC_STATUSC_STATE0_Pos) -#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ -#define AC_STATUSC_STATE1 (_U_(1) << AC_STATUSC_STATE1_Pos) -#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ -#define AC_STATUSC_STATE_Msk (_U_(0x3) << AC_STATUSC_STATE_Pos) -#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) -#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ -#define AC_STATUSC_WSTATE0_Msk (_U_(0x3) << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) -#define AC_STATUSC_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSC) Signal is above window */ -#define AC_STATUSC_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ -#define AC_STATUSC_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSC) Signal is below window */ -#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) -#define AC_STATUSC_MASK _U_(0x33) /**< \brief (AC_STATUSC) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t ENABLE:1; /*!< bit: 0 Enable */ - uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ - uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ - uint32_t :1; /*!< bit: 4 Reserved */ - uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ - uint32_t :1; /*!< bit: 14 Reserved */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t OUT:2; /*!< bit: 16..17 Output */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t :4; /*!< bit: 20..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :5; /*!< bit: 27..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x1) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x3) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYST (_U_(0x1) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_MASK _U_(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - RoReg8 Reserved1[0x1]; - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ - __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ - RoReg8 Reserved2[0x1]; - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ - RoReg8 Reserved3[0x3]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved4[0x8]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_AC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_AC_COMPONENT_ +#define _SAMD21_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_AC Analog Comparators */ +/*@{*/ + +#define AC_U2205 +#define REV_AC 0x111 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :4; /*!< bit: 3.. 6 Reserved */ + uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ +#define AC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << AC_CTRLA_RUNSTDBY_Pos) +#define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) +#define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ +#define AC_CTRLA_LPMUX (_U_(0x1) << AC_CTRLA_LPMUX_Pos) +#define AC_CTRLA_MASK _U_(0x87) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ + uint16_t :6; /*!< bit: 10..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :5; /*!< bit: 2.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ +#define AC_STATUSB_SYNCBUSY (_U_(0x1) << AC_STATUSB_SYNCBUSY_Pos) +#define AC_STATUSB_MASK _U_(0x83) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ +#define AC_STATUSC_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ + +#define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ +#define AC_STATUSC_STATE0 (_U_(1) << AC_STATUSC_STATE0_Pos) +#define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ +#define AC_STATUSC_STATE1 (_U_(1) << AC_STATUSC_STATE1_Pos) +#define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ +#define AC_STATUSC_STATE_Msk (_U_(0x3) << AC_STATUSC_STATE_Pos) +#define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) +#define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ +#define AC_STATUSC_WSTATE0_Msk (_U_(0x3) << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) +#define AC_STATUSC_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSC) Signal is above window */ +#define AC_STATUSC_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ +#define AC_STATUSC_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSC) Signal is below window */ +#define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) +#define AC_STATUSC_MASK _U_(0x33) /**< \brief (AC_STATUSC) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ENABLE:1; /*!< bit: 0 Enable */ + uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ + uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ + uint32_t :1; /*!< bit: 4 Reserved */ + uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ + uint32_t :1; /*!< bit: 14 Reserved */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t OUT:2; /*!< bit: 16..17 Output */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t :4; /*!< bit: 20..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :5; /*!< bit: 27..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x1) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x3) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYST (_U_(0x1) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_MASK _U_(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + RoReg8 Reserved1[0x1]; + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ + __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ + RoReg8 Reserved2[0x1]; + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ + RoReg8 Reserved3[0x3]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved4[0x8]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_AC_COMPONENT_ */ diff --git a/lib/samd21/samd21a/include/component/adc.h b/lib/samd21/samd21a/include/component/adc.h index 4ed49e8..6f5a6b3 100644 --- a/lib/samd21/samd21a/include/component/adc.h +++ b/lib/samd21/samd21a/include/component/adc.h @@ -1,685 +1,685 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_ADC_COMPONENT_ -#define _SAMD21_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2204 -#define REV_ADC 0x120 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_MASK _U_(0x07) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INT1V_Val _U_(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External reference */ -#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_MASK _U_(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ - uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ - uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ - uint16_t :2; /*!< bit: 6.. 7 Reserved */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ -#define ADC_CTRLB_DIFFMODE (_U_(0x1) << ADC_CTRLB_DIFFMODE_Pos) -#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ -#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ -#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) -#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ -#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ -#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ -#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ -#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ -#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ -#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ -#define ADC_CTRLB_PRESCALER_DIV512_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ -#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) -#define ADC_CTRLB_MASK _U_(0x073F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ -#define ADC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ - -#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ -#define ADC_WINCTRL_WINMODE_Msk (_U_(0x7) << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) -#define ADC_WINCTRL_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */ -#define ADC_WINCTRL_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ -#define ADC_WINCTRL_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ -#define ADC_WINCTRL_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ -#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) -#define ADC_WINCTRL_MASK _U_(0x07) /**< \brief (ADC_WINCTRL) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ -#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint32_t :3; /*!< bit: 5.. 7 Reserved */ - uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint32_t :3; /*!< bit: 13..15 Reserved */ - uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ - uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ - uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ - uint32_t :4; /*!< bit: 28..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */ -#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ -#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U_(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos) -#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) -#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ -#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U_(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos) -#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) -#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ -#define ADC_INPUTCTRL_GAIN_Msk (_U_(0xF) << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) -#define ADC_INPUTCTRL_GAIN_1X_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) 1x */ -#define ADC_INPUTCTRL_GAIN_2X_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) 2x */ -#define ADC_INPUTCTRL_GAIN_4X_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) 4x */ -#define ADC_INPUTCTRL_GAIN_8X_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) 8x */ -#define ADC_INPUTCTRL_GAIN_16X_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) 16x */ -#define ADC_INPUTCTRL_GAIN_DIV2_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */ -#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) -#define ADC_INPUTCTRL_MASK _U_(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ - uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ -#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ -#define ADC_EVCTRL_SYNCEI (_U_(0x1) << ADC_EVCTRL_SYNCEI_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U_(0x33) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ -#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ -#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ -#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define ADC_INTENCLR_SYNCRDY (_U_(0x1) << ADC_INTENCLR_SYNCRDY_Pos) -#define ADC_INTENCLR_MASK _U_(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ -#define ADC_INTENSET_SYNCRDY (_U_(0x1) << ADC_INTENSET_SYNCRDY_Pos) -#define ADC_INTENSET_MASK _U_(0x0F) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ - __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ - __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ -#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ -#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ -#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ -#define ADC_INTFLAG_SYNCRDY (_U_(0x1) << ADC_INTFLAG_SYNCRDY_Pos) -#define ADC_INTFLAG_MASK _U_(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ -#define ADC_STATUS_SYNCBUSY (_U_(0x1) << ADC_STATUS_SYNCBUSY_Pos) -#define ADC_STATUS_MASK _U_(0x80) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ -#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ - uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ -#define ADC_CALIB_LINEARITY_CAL_Msk (_U_(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos) -#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) -#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ -#define ADC_CALIB_BIAS_CAL_Msk (_U_(0x7) << ADC_CALIB_BIAS_CAL_Pos) -#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) -#define ADC_CALIB_MASK _U_(0x07FF) /**< \brief (ADC_CALIB) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ - RoReg8 Reserved1[0x2]; - __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ - RoReg8 Reserved2[0x3]; - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ - RoReg8 Reserved3[0x3]; - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ - RoReg8 Reserved4[0x1]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ - RoReg8 Reserved5[0x2]; - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ - RoReg8 Reserved6[0x2]; - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_ADC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_ADC_COMPONENT_ +#define _SAMD21_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2204 +#define REV_ADC 0x120 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_MASK _U_(0x07) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x01 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INT1V_Val _U_(0x0) /**< \brief (ADC_REFCTRL) 1.0V voltage reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x1) /**< \brief (ADC_REFCTRL) 1/1.48 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA (only for VDDANA > 2.0V) */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x3) /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External reference */ +#define ADC_REFCTRL_REFSEL_INT1V (ADC_REFCTRL_REFSEL_INT1V_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x02 /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x03 /**< \brief (ADC_SAMPCTRL offset) Sampling Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sampling Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_MASK _U_(0x3F) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */ + uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */ + uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */ + uint16_t :2; /*!< bit: 6.. 7 Reserved */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x04 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_DIFFMODE_Pos 0 /**< \brief (ADC_CTRLB) Differential Mode */ +#define ADC_CTRLB_DIFFMODE (_U_(0x1) << ADC_CTRLB_DIFFMODE_Pos) +#define ADC_CTRLB_LEFTADJ_Pos 1 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 2 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 3 /**< \brief (ADC_CTRLB) Digital Correction Logic Enabled */ +#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 4 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_PRESCALER_Pos 8 /**< \brief (ADC_CTRLB) Prescaler Configuration */ +#define ADC_CTRLB_PRESCALER_Msk (_U_(0x7) << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER(value) (ADC_CTRLB_PRESCALER_Msk & ((value) << ADC_CTRLB_PRESCALER_Pos)) +#define ADC_CTRLB_PRESCALER_DIV4_Val _U_(0x0) /**< \brief (ADC_CTRLB) Peripheral clock divided by 4 */ +#define ADC_CTRLB_PRESCALER_DIV8_Val _U_(0x1) /**< \brief (ADC_CTRLB) Peripheral clock divided by 8 */ +#define ADC_CTRLB_PRESCALER_DIV16_Val _U_(0x2) /**< \brief (ADC_CTRLB) Peripheral clock divided by 16 */ +#define ADC_CTRLB_PRESCALER_DIV32_Val _U_(0x3) /**< \brief (ADC_CTRLB) Peripheral clock divided by 32 */ +#define ADC_CTRLB_PRESCALER_DIV64_Val _U_(0x4) /**< \brief (ADC_CTRLB) Peripheral clock divided by 64 */ +#define ADC_CTRLB_PRESCALER_DIV128_Val _U_(0x5) /**< \brief (ADC_CTRLB) Peripheral clock divided by 128 */ +#define ADC_CTRLB_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (ADC_CTRLB) Peripheral clock divided by 256 */ +#define ADC_CTRLB_PRESCALER_DIV512_Val _U_(0x7) /**< \brief (ADC_CTRLB) Peripheral clock divided by 512 */ +#define ADC_CTRLB_PRESCALER_DIV4 (ADC_CTRLB_PRESCALER_DIV4_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV8 (ADC_CTRLB_PRESCALER_DIV8_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV16 (ADC_CTRLB_PRESCALER_DIV16_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV32 (ADC_CTRLB_PRESCALER_DIV32_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV64 (ADC_CTRLB_PRESCALER_DIV64_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV128 (ADC_CTRLB_PRESCALER_DIV128_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV256 (ADC_CTRLB_PRESCALER_DIV256_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_PRESCALER_DIV512 (ADC_CTRLB_PRESCALER_DIV512_Val << ADC_CTRLB_PRESCALER_Pos) +#define ADC_CTRLB_MASK _U_(0x073F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINCTRL_OFFSET 0x08 /**< \brief (ADC_WINCTRL offset) Window Monitor Control */ +#define ADC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_WINCTRL reset_value) Window Monitor Control */ + +#define ADC_WINCTRL_WINMODE_Pos 0 /**< \brief (ADC_WINCTRL) Window Monitor Mode */ +#define ADC_WINCTRL_WINMODE_Msk (_U_(0x7) << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE(value) (ADC_WINCTRL_WINMODE_Msk & ((value) << ADC_WINCTRL_WINMODE_Pos)) +#define ADC_WINCTRL_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_WINCTRL) No window mode (default) */ +#define ADC_WINCTRL_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_WINCTRL) Mode 1: RESULT > WINLT */ +#define ADC_WINCTRL_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_WINCTRL) Mode 2: RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_WINCTRL) Mode 3: WINLT < RESULT < WINUT */ +#define ADC_WINCTRL_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_WINCTRL) Mode 4: !(WINLT < RESULT < WINUT) */ +#define ADC_WINCTRL_WINMODE_DISABLE (ADC_WINCTRL_WINMODE_DISABLE_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE1 (ADC_WINCTRL_WINMODE_MODE1_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE2 (ADC_WINCTRL_WINMODE_MODE2_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE3 (ADC_WINCTRL_WINMODE_MODE3_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_WINMODE_MODE4 (ADC_WINCTRL_WINMODE_MODE4_Val << ADC_WINCTRL_WINMODE_Pos) +#define ADC_WINCTRL_MASK _U_(0x07) /**< \brief (ADC_WINCTRL) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 ADC Start Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x0C /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) ADC Start Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint32_t :3; /*!< bit: 5.. 7 Reserved */ + uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */ + uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */ + uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */ + uint32_t :4; /*!< bit: 28..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x10 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_PIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_TEMP_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Temperature Reference */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PIN0 (ADC_INPUTCTRL_MUXPOS_PIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN1 (ADC_INPUTCTRL_MUXPOS_PIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN2 (ADC_INPUTCTRL_MUXPOS_PIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN3 (ADC_INPUTCTRL_MUXPOS_PIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN4 (ADC_INPUTCTRL_MUXPOS_PIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN5 (ADC_INPUTCTRL_MUXPOS_PIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN6 (ADC_INPUTCTRL_MUXPOS_PIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN7 (ADC_INPUTCTRL_MUXPOS_PIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN8 (ADC_INPUTCTRL_MUXPOS_PIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN9 (ADC_INPUTCTRL_MUXPOS_PIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN10 (ADC_INPUTCTRL_MUXPOS_PIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN11 (ADC_INPUTCTRL_MUXPOS_PIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN12 (ADC_INPUTCTRL_MUXPOS_PIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN13 (ADC_INPUTCTRL_MUXPOS_PIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN14 (ADC_INPUTCTRL_MUXPOS_PIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN15 (ADC_INPUTCTRL_MUXPOS_PIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN16 (ADC_INPUTCTRL_MUXPOS_PIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN17 (ADC_INPUTCTRL_MUXPOS_PIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN18 (ADC_INPUTCTRL_MUXPOS_PIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PIN19 (ADC_INPUTCTRL_MUXPOS_PIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_TEMP (ADC_INPUTCTRL_MUXPOS_TEMP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_PIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_IOGND_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) I/O Ground */ +#define ADC_INPUTCTRL_MUXNEG_PIN0 (ADC_INPUTCTRL_MUXNEG_PIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN1 (ADC_INPUTCTRL_MUXNEG_PIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN2 (ADC_INPUTCTRL_MUXNEG_PIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN3 (ADC_INPUTCTRL_MUXNEG_PIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN4 (ADC_INPUTCTRL_MUXNEG_PIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN5 (ADC_INPUTCTRL_MUXNEG_PIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN6 (ADC_INPUTCTRL_MUXNEG_PIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_PIN7 (ADC_INPUTCTRL_MUXNEG_PIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_IOGND (ADC_INPUTCTRL_MUXNEG_IOGND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_INPUTSCAN_Pos 16 /**< \brief (ADC_INPUTCTRL) Number of Input Channels Included in Scan */ +#define ADC_INPUTCTRL_INPUTSCAN_Msk (_U_(0xF) << ADC_INPUTCTRL_INPUTSCAN_Pos) +#define ADC_INPUTCTRL_INPUTSCAN(value) (ADC_INPUTCTRL_INPUTSCAN_Msk & ((value) << ADC_INPUTCTRL_INPUTSCAN_Pos)) +#define ADC_INPUTCTRL_INPUTOFFSET_Pos 20 /**< \brief (ADC_INPUTCTRL) Positive Mux Setting Offset */ +#define ADC_INPUTCTRL_INPUTOFFSET_Msk (_U_(0xF) << ADC_INPUTCTRL_INPUTOFFSET_Pos) +#define ADC_INPUTCTRL_INPUTOFFSET(value) (ADC_INPUTCTRL_INPUTOFFSET_Msk & ((value) << ADC_INPUTCTRL_INPUTOFFSET_Pos)) +#define ADC_INPUTCTRL_GAIN_Pos 24 /**< \brief (ADC_INPUTCTRL) Gain Factor Selection */ +#define ADC_INPUTCTRL_GAIN_Msk (_U_(0xF) << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN(value) (ADC_INPUTCTRL_GAIN_Msk & ((value) << ADC_INPUTCTRL_GAIN_Pos)) +#define ADC_INPUTCTRL_GAIN_1X_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) 1x */ +#define ADC_INPUTCTRL_GAIN_2X_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) 2x */ +#define ADC_INPUTCTRL_GAIN_4X_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) 4x */ +#define ADC_INPUTCTRL_GAIN_8X_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) 8x */ +#define ADC_INPUTCTRL_GAIN_16X_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) 16x */ +#define ADC_INPUTCTRL_GAIN_DIV2_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) 1/2x */ +#define ADC_INPUTCTRL_GAIN_1X (ADC_INPUTCTRL_GAIN_1X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_2X (ADC_INPUTCTRL_GAIN_2X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_4X (ADC_INPUTCTRL_GAIN_4X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_8X (ADC_INPUTCTRL_GAIN_8X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_16X (ADC_INPUTCTRL_GAIN_16X_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_GAIN_DIV2 (ADC_INPUTCTRL_GAIN_DIV2_Val << ADC_INPUTCTRL_GAIN_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x0FFF1F1F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */ + uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x14 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_STARTEI_Pos 0 /**< \brief (ADC_EVCTRL) Start Conversion Event In */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_SYNCEI_Pos 1 /**< \brief (ADC_EVCTRL) Synchronization Event In */ +#define ADC_EVCTRL_SYNCEI (_U_(0x1) << ADC_EVCTRL_SYNCEI_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x33) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x16 /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Enable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Enable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Enable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_SYNCRDY_Pos 3 /**< \brief (ADC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define ADC_INTENCLR_SYNCRDY (_U_(0x1) << ADC_INTENCLR_SYNCRDY_Pos) +#define ADC_INTENCLR_MASK _U_(0x0F) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x17 /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_SYNCRDY_Pos 3 /**< \brief (ADC_INTENSET) Synchronization Ready Interrupt Enable */ +#define ADC_INTENSET_SYNCRDY (_U_(0x1) << ADC_INTENSET_SYNCRDY_Pos) +#define ADC_INTENSET_MASK _U_(0x0F) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */ + __I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */ + __I uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x18 /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_SYNCRDY_Pos 3 /**< \brief (ADC_INTFLAG) Synchronization Ready */ +#define ADC_INTFLAG_SYNCRDY (_U_(0x1) << ADC_INTFLAG_SYNCRDY_Pos) +#define ADC_INTFLAG_MASK _U_(0x0F) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x19 /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_SYNCBUSY_Pos 7 /**< \brief (ADC_STATUS) Synchronization Busy */ +#define ADC_STATUS_SYNCBUSY (_U_(0x1) << ADC_STATUS_SYNCBUSY_Pos) +#define ADC_STATUS_MASK _U_(0x80) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x1A /**< \brief (ADC_RESULT offset) Result */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x1C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x20 /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x24 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x26 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */ + uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x28 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_LINEARITY_CAL_Pos 0 /**< \brief (ADC_CALIB) Linearity Calibration Value */ +#define ADC_CALIB_LINEARITY_CAL_Msk (_U_(0xFF) << ADC_CALIB_LINEARITY_CAL_Pos) +#define ADC_CALIB_LINEARITY_CAL(value) (ADC_CALIB_LINEARITY_CAL_Msk & ((value) << ADC_CALIB_LINEARITY_CAL_Pos)) +#define ADC_CALIB_BIAS_CAL_Pos 8 /**< \brief (ADC_CALIB) Bias Calibration Value */ +#define ADC_CALIB_BIAS_CAL_Msk (_U_(0x7) << ADC_CALIB_BIAS_CAL_Pos) +#define ADC_CALIB_BIAS_CAL(value) (ADC_CALIB_BIAS_CAL_Msk & ((value) << ADC_CALIB_BIAS_CAL_Pos)) +#define ADC_CALIB_MASK _U_(0x07FF) /**< \brief (ADC_CALIB) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x2A /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */ + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */ + RoReg8 Reserved1[0x2]; + __IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */ + RoReg8 Reserved2[0x3]; + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */ + RoReg8 Reserved3[0x3]; + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */ + RoReg8 Reserved4[0x1]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */ + RoReg8 Reserved5[0x2]; + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */ + RoReg8 Reserved6[0x2]; + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */ + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_ADC_COMPONENT_ */ diff --git a/lib/samd21/samd21a/include/component/dac.h b/lib/samd21/samd21a/include/component/dac.h index 824dde6..45e10f0 100644 --- a/lib/samd21/samd21a/include/component/dac.h +++ b/lib/samd21/samd21a/include/component/dac.h @@ -1,272 +1,272 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DAC_COMPONENT_ -#define _SAMD21_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DAC Digital Analog Converter */ -/*@{*/ - -#define DAC_U2214 -#define REV_DAC 0x110 - -/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ -#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ -#define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) -#define DAC_CTRLA_MASK _U_(0x07) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ - uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ - uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ - uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ - uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ - uint8_t :1; /*!< bit: 5 Reserved */ - uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ -#define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos) -#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ -#define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos) -#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ -#define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos) -#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ -#define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos) -#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ -#define DAC_CTRLB_BDWP (_U_(0x1) << DAC_CTRLB_BDWP_Pos) -#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ -#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ -#define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */ -#define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */ -#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U_(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ - uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ -#define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ -#define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_MASK _U_(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ -#define DAC_INTENCLR_SYNCRDY (_U_(0x1) << DAC_INTENCLR_SYNCRDY_Pos) -#define DAC_INTENCLR_MASK _U_(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ - uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ - uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ -#define DAC_INTENSET_SYNCRDY (_U_(0x1) << DAC_INTENSET_SYNCRDY_Pos) -#define DAC_INTENSET_MASK _U_(0x07) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ - __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ - __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ -#define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ -#define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ -#define DAC_INTFLAG_SYNCRDY (_U_(0x1) << DAC_INTFLAG_SYNCRDY_Pos) -#define DAC_INTFLAG_MASK _U_(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t :7; /*!< bit: 0.. 6 Reserved */ - uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ -#define DAC_STATUS_SYNCBUSY (_U_(0x1) << DAC_STATUS_SYNCBUSY_Pos) -#define DAC_STATUS_MASK _U_(0x80) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ -#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ -#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ - __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ - RoReg8 Reserved2[0x2]; - __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD21_DAC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21_DAC_COMPONENT_ +#define _SAMD21_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAMD21_DAC Digital Analog Converter */ +/*@{*/ + +#define DAC_U2214 +#define REV_DAC 0x110 + +/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ +#define DAC_CTRLA_RUNSTDBY (_U_(0x1) << DAC_CTRLA_RUNSTDBY_Pos) +#define DAC_CTRLA_MASK _U_(0x07) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ + uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ + uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ + uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ + uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ + uint8_t :1; /*!< bit: 5 Reserved */ + uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ +#define DAC_CTRLB_EOEN (_U_(0x1) << DAC_CTRLB_EOEN_Pos) +#define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ +#define DAC_CTRLB_IOEN (_U_(0x1) << DAC_CTRLB_IOEN_Pos) +#define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ +#define DAC_CTRLB_LEFTADJ (_U_(0x1) << DAC_CTRLB_LEFTADJ_Pos) +#define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ +#define DAC_CTRLB_VPD (_U_(0x1) << DAC_CTRLB_VPD_Pos) +#define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ +#define DAC_CTRLB_BDWP (_U_(0x1) << DAC_CTRLB_BDWP_Pos) +#define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_INT1V_Val _U_(0x0) /**< \brief (DAC_CTRLB) Internal 1.0V reference */ +#define DAC_CTRLB_REFSEL_AVCC_Val _U_(0x1) /**< \brief (DAC_CTRLB) AVCC */ +#define DAC_CTRLB_REFSEL_VREFP_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference */ +#define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0xDF) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ + uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ +#define DAC_EVCTRL_STARTEI (_U_(0x1) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ +#define DAC_EVCTRL_EMPTYEO (_U_(0x1) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_MASK _U_(0x03) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN (_U_(0x1) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY (_U_(0x1) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ +#define DAC_INTENCLR_SYNCRDY (_U_(0x1) << DAC_INTENCLR_SYNCRDY_Pos) +#define DAC_INTENCLR_MASK _U_(0x07) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ + uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ + uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN (_U_(0x1) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY (_U_(0x1) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ +#define DAC_INTENSET_SYNCRDY (_U_(0x1) << DAC_INTENSET_SYNCRDY_Pos) +#define DAC_INTENSET_MASK _U_(0x07) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ + __I uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ + __I uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ +#define DAC_INTFLAG_UNDERRUN (_U_(0x1) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ +#define DAC_INTFLAG_EMPTY (_U_(0x1) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ +#define DAC_INTFLAG_SYNCRDY (_U_(0x1) << DAC_INTFLAG_SYNCRDY_Pos) +#define DAC_INTFLAG_MASK _U_(0x07) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t :7; /*!< bit: 0.. 6 Reserved */ + uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ +#define DAC_STATUS_SYNCBUSY (_U_(0x1) << DAC_STATUS_SYNCBUSY_Pos) +#define DAC_STATUS_MASK _U_(0x80) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ + __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ + RoReg8 Reserved2[0x2]; + __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD21_DAC_COMPONENT_ */ diff --git a/lib/samd21/samd21a/include/component/dmac.h b/lib/samd21/samd21a/include/component/dmac.h index c09402a..7d80b41 100644 --- a/lib/samd21/samd21a/include/component/dmac.h +++ b/lib/samd21/samd21a/include/component/dmac.h @@ -1,1073 +1,1073 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21_DMAC_COMPONENT_ -#define _SAMD21_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD21_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2223 -#define REV_DMAC 0x100 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */ - uint16_t :5; /*!< bit: 3.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_CRCENABLE_Pos 2 /**< \brief (DMAC_CTRL) CRC Enable */ -#define DMAC_CTRL_CRCENABLE (_U_(0x1) << DMAC_CTRL_CRCENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U_(0x0F07) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_NOACT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) No action */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_NOACT (DMAC_CRCCTRL_CRCSRC_NOACT_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_MASK _U_(0x3F0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_MASK _U_(0x03) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */ - uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */ - uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_QOSCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_QOSCTRL_OFFSET 0x0E /**< \brief (DMAC_QOSCTRL offset) QOS Control */ -#define DMAC_QOSCTRL_RESETVALUE _U_(0x15) /**< \brief (DMAC_QOSCTRL reset_value) QOS Control */ - -#define DMAC_QOSCTRL_WRBQOS_Pos 0 /**< \brief (DMAC_QOSCTRL) Write-Back Quality of Service */ -#define DMAC_QOSCTRL_WRBQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS(value) (DMAC_QOSCTRL_WRBQOS_Msk & ((value) << DMAC_QOSCTRL_WRBQOS_Pos)) -#define DMAC_QOSCTRL_WRBQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_WRBQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_WRBQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_WRBQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_WRBQOS_DISABLE (DMAC_QOSCTRL_WRBQOS_DISABLE_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_LOW (DMAC_QOSCTRL_WRBQOS_LOW_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_MEDIUM (DMAC_QOSCTRL_WRBQOS_MEDIUM_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_WRBQOS_HIGH (DMAC_QOSCTRL_WRBQOS_HIGH_Val << DMAC_QOSCTRL_WRBQOS_Pos) -#define DMAC_QOSCTRL_FQOS_Pos 2 /**< \brief (DMAC_QOSCTRL) Fetch Quality of Service */ -#define DMAC_QOSCTRL_FQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS(value) (DMAC_QOSCTRL_FQOS_Msk & ((value) << DMAC_QOSCTRL_FQOS_Pos)) -#define DMAC_QOSCTRL_FQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_FQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_FQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_FQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_FQOS_DISABLE (DMAC_QOSCTRL_FQOS_DISABLE_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_LOW (DMAC_QOSCTRL_FQOS_LOW_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_MEDIUM (DMAC_QOSCTRL_FQOS_MEDIUM_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_FQOS_HIGH (DMAC_QOSCTRL_FQOS_HIGH_Val << DMAC_QOSCTRL_FQOS_Pos) -#define DMAC_QOSCTRL_DQOS_Pos 4 /**< \brief (DMAC_QOSCTRL) Data Transfer Quality of Service */ -#define DMAC_QOSCTRL_DQOS_Msk (_U_(0x3) << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS(value) (DMAC_QOSCTRL_DQOS_Msk & ((value) << DMAC_QOSCTRL_DQOS_Pos)) -#define DMAC_QOSCTRL_DQOS_DISABLE_Val _U_(0x0) /**< \brief (DMAC_QOSCTRL) Background (no sensitive operation) */ -#define DMAC_QOSCTRL_DQOS_LOW_Val _U_(0x1) /**< \brief (DMAC_QOSCTRL) Sensitive Bandwidth */ -#define DMAC_QOSCTRL_DQOS_MEDIUM_Val _U_(0x2) /**< \brief (DMAC_QOSCTRL) Sensitive Latency */ -#define DMAC_QOSCTRL_DQOS_HIGH_Val _U_(0x3) /**< \brief (DMAC_QOSCTRL) Critical Latency */ -#define DMAC_QOSCTRL_DQOS_DISABLE (DMAC_QOSCTRL_DQOS_DISABLE_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_LOW (DMAC_QOSCTRL_DQOS_LOW_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_MEDIUM (DMAC_QOSCTRL_DQOS_MEDIUM_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_DQOS_HIGH (DMAC_QOSCTRL_DQOS_HIGH_Val << DMAC_QOSCTRL_DQOS_Pos) -#define DMAC_QOSCTRL_MASK _U_(0x3F) /**< \brief (DMAC_QOSCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U_(0x00000FFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */ - uint32_t :3; /*!< bit: 4.. 6 Reserved */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */ - uint32_t :3; /*!< bit: 12..14 Reserved */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */ - uint32_t :3; /*!< bit: 20..22 Reserved */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */ - uint32_t :3; /*!< bit: 28..30 Reserved */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0xF) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U_(0x8F8F8F8F) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :2; /*!< bit: 11..12 Reserved */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U_(0xF) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U_(0xE70F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U_(0x00000FFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U_(0x00000FFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U_(0x00000FFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHID_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHID_OFFSET 0x3F /**< \brief (DMAC_CHID offset) Channel ID */ -#define DMAC_CHID_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHID reset_value) Channel ID */ - -#define DMAC_CHID_ID_Pos 0 /**< \brief (DMAC_CHID) Channel ID */ -#define DMAC_CHID_ID_Msk (_U_(0xF) << DMAC_CHID_ID_Pos) -#define DMAC_CHID_ID(value) (DMAC_CHID_ID_Msk & ((value) << DMAC_CHID_ID_Pos)) -#define DMAC_CHID_MASK _U_(0x0F) /**< \brief (DMAC_CHID) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLA reset_value) Channel Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */ - uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */ - uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */ - uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */ - uint32_t :8; /*!< bit: 14..21 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */ - uint32_t CMD:2; /*!< bit: 24..25 Software Command */ - uint32_t :6; /*!< bit: 26..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLB reset_value) Channel Control B */ - -#define DMAC_CHCTRLB_EVACT_Pos 0 /**< \brief (DMAC_CHCTRLB) Event Input Action */ -#define DMAC_CHCTRLB_EVACT_Msk (_U_(0x7) << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT(value) (DMAC_CHCTRLB_EVACT_Msk & ((value) << DMAC_CHCTRLB_EVACT_Pos)) -#define DMAC_CHCTRLB_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Transfer and periodic transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Conditional transfer trigger */ -#define DMAC_CHCTRLB_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) Conditional block transfer */ -#define DMAC_CHCTRLB_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHCTRLB) Skip next block suspend action */ -#define DMAC_CHCTRLB_EVACT_NOACT (DMAC_CHCTRLB_EVACT_NOACT_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_TRIG (DMAC_CHCTRLB_EVACT_TRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CTRIG (DMAC_CHCTRLB_EVACT_CTRIG_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_CBLOCK (DMAC_CHCTRLB_EVACT_CBLOCK_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SUSPEND (DMAC_CHCTRLB_EVACT_SUSPEND_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_RESUME (DMAC_CHCTRLB_EVACT_RESUME_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVACT_SSKIP (DMAC_CHCTRLB_EVACT_SSKIP_Val << DMAC_CHCTRLB_EVACT_Pos) -#define DMAC_CHCTRLB_EVIE_Pos 3 /**< \brief (DMAC_CHCTRLB) Channel Event Input Enable */ -#define DMAC_CHCTRLB_EVIE (_U_(0x1) << DMAC_CHCTRLB_EVIE_Pos) -#define DMAC_CHCTRLB_EVOE_Pos 4 /**< \brief (DMAC_CHCTRLB) Channel Event Output Enable */ -#define DMAC_CHCTRLB_EVOE (_U_(0x1) << DMAC_CHCTRLB_EVOE_Pos) -#define DMAC_CHCTRLB_LVL_Pos 5 /**< \brief (DMAC_CHCTRLB) Channel Arbitration Level */ -#define DMAC_CHCTRLB_LVL_Msk (_U_(0x3) << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL(value) (DMAC_CHCTRLB_LVL_Msk & ((value) << DMAC_CHCTRLB_LVL_Pos)) -#define DMAC_CHCTRLB_LVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 0 */ -#define DMAC_CHCTRLB_LVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 1 */ -#define DMAC_CHCTRLB_LVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 2 */ -#define DMAC_CHCTRLB_LVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) Channel Priority Level 3 */ -#define DMAC_CHCTRLB_LVL_LVL0 (DMAC_CHCTRLB_LVL_LVL0_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL1 (DMAC_CHCTRLB_LVL_LVL1_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL2 (DMAC_CHCTRLB_LVL_LVL2_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_LVL_LVL3 (DMAC_CHCTRLB_LVL_LVL3_Val << DMAC_CHCTRLB_LVL_Pos) -#define DMAC_CHCTRLB_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLB) Trigger Source */ -#define DMAC_CHCTRLB_TRIGSRC_Msk (_U_(0x3F) << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGSRC(value) (DMAC_CHCTRLB_TRIGSRC_Msk & ((value) << DMAC_CHCTRLB_TRIGSRC_Pos)) -#define DMAC_CHCTRLB_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) Only software/event triggers */ -#define DMAC_CHCTRLB_TRIGSRC_DISABLE (DMAC_CHCTRLB_TRIGSRC_DISABLE_Val << DMAC_CHCTRLB_TRIGSRC_Pos) -#define DMAC_CHCTRLB_TRIGACT_Pos 22 /**< \brief (DMAC_CHCTRLB) Trigger Action */ -#define DMAC_CHCTRLB_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT(value) (DMAC_CHCTRLB_TRIGACT_Msk & ((value) << DMAC_CHCTRLB_TRIGACT_Pos)) -#define DMAC_CHCTRLB_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) One trigger required for each block transfer */ -#define DMAC_CHCTRLB_TRIGACT_BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) One trigger required for each beat transfer */ -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLB) One trigger required for each transaction */ -#define DMAC_CHCTRLB_TRIGACT_BLOCK (DMAC_CHCTRLB_TRIGACT_BLOCK_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_BEAT (DMAC_CHCTRLB_TRIGACT_BEAT_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_TRIGACT_TRANSACTION (DMAC_CHCTRLB_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLB_TRIGACT_Pos) -#define DMAC_CHCTRLB_CMD_Pos 24 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U_(0x03C03F7F) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel Status */ -#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Event strobe when block transfer complete */ -#define DMAC_BTCTRL_EVOSEL_BEAT_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Event strobe when beat transfer complete */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BEAT (DMAC_BTCTRL_EVOSEL_BEAT_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21E15A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1001030D) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E15A_H */ +/** + * \file + * + * \brief Header file for SAMD21E15A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E15A_ +#define _SAMD21E15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E15A_definitions SAMD21E15A definitions + * This file defines all structures and symbols for SAMD21E15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21E15A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1001030D) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E15A_H */ diff --git a/lib/samd21/samd21a/include/samd21e16a.h b/lib/samd21/samd21a/include/samd21e16a.h index fb5e6df..2788ab0 100644 --- a/lib/samd21/samd21a/include/samd21e16a.h +++ b/lib/samd21/samd21a/include/samd21e16a.h @@ -1,559 +1,559 @@ -/** - * \file - * - * \brief Header file for SAMD21E16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E16A_ -#define _SAMD21E16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions - * This file defines all structures and symbols for SAMD21E16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21E16A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1001030C) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E16A_H */ +/** + * \file + * + * \brief Header file for SAMD21E16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E16A_ +#define _SAMD21E16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E16A_definitions SAMD21E16A definitions + * This file defines all structures and symbols for SAMD21E16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21E16A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1001030C) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E16A_H */ diff --git a/lib/samd21/samd21a/include/samd21e17a.h b/lib/samd21/samd21a/include/samd21e17a.h index 26b25bb..8dde727 100644 --- a/lib/samd21/samd21a/include/samd21e17a.h +++ b/lib/samd21/samd21a/include/samd21e17a.h @@ -1,559 +1,559 @@ -/** - * \file - * - * \brief Header file for SAMD21E17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E17A_ -#define _SAMD21E17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions - * This file defines all structures and symbols for SAMD21E17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21E17A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1001030B) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E17A_H */ +/** + * \file + * + * \brief Header file for SAMD21E17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E17A_ +#define _SAMD21E17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E17A_definitions SAMD21E17A definitions + * This file defines all structures and symbols for SAMD21E17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21E17A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1001030B) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E17A_H */ diff --git a/lib/samd21/samd21a/include/samd21e18a.h b/lib/samd21/samd21a/include/samd21e18a.h index afc982e..61b40de 100644 --- a/lib/samd21/samd21a/include/samd21e18a.h +++ b/lib/samd21/samd21a/include/samd21e18a.h @@ -1,559 +1,559 @@ -/** - * \file - * - * \brief Header file for SAMD21E18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21E18A_ -#define _SAMD21E18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions - * This file defines all structures and symbols for SAMD21E18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21E18A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ - TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pvReserved13; - void* pvReserved14; - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21E18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21e18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1001030A) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 1 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21E18A_H */ +/** + * \file + * + * \brief Header file for SAMD21E18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21E18A_ +#define _SAMD21E18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21E18A_definitions SAMD21E18A definitions + * This file defines all structures and symbols for SAMD21E18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21E18A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */ + TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pvReserved13; + void* pvReserved14; + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM_INST_NUM 4 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21E18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21e18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1001030A) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 1 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21E18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21E18A_H */ diff --git a/lib/samd21/samd21a/include/samd21g15a.h b/lib/samd21/samd21a/include/samd21g15a.h index 4b6090e..47317ae 100644 --- a/lib/samd21/samd21a/include/samd21g15a.h +++ b/lib/samd21/samd21a/include/samd21g15a.h @@ -1,571 +1,571 @@ -/** - * \file - * - * \brief Header file for SAMD21G15A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G15A_ -#define _SAMD21G15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions - * This file defines all structures and symbols for SAMD21G15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21G15A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010308) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G15A_H */ +/** + * \file + * + * \brief Header file for SAMD21G15A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G15A_ +#define _SAMD21G15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G15A_definitions SAMD21G15A definitions + * This file defines all structures and symbols for SAMD21G15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21G15A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010308) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G15A_H */ diff --git a/lib/samd21/samd21a/include/samd21g16a.h b/lib/samd21/samd21a/include/samd21g16a.h index 856389a..0b80a3c 100644 --- a/lib/samd21/samd21a/include/samd21g16a.h +++ b/lib/samd21/samd21a/include/samd21g16a.h @@ -1,571 +1,571 @@ -/** - * \file - * - * \brief Header file for SAMD21G16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G16A_ -#define _SAMD21G16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions - * This file defines all structures and symbols for SAMD21G16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21G16A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010307) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G16A_H */ +/** + * \file + * + * \brief Header file for SAMD21G16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G16A_ +#define _SAMD21G16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G16A_definitions SAMD21G16A definitions + * This file defines all structures and symbols for SAMD21G16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21G16A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010307) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G16A_H */ diff --git a/lib/samd21/samd21a/include/samd21g17a.h b/lib/samd21/samd21a/include/samd21g17a.h index c8042f6..1221a79 100644 --- a/lib/samd21/samd21a/include/samd21g17a.h +++ b/lib/samd21/samd21a/include/samd21g17a.h @@ -1,571 +1,571 @@ -/** - * \file - * - * \brief Header file for SAMD21G17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17A_ -#define _SAMD21G17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions - * This file defines all structures and symbols for SAMD21G17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21G17A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010306) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17A_H */ +/** + * \file + * + * \brief Header file for SAMD21G17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G17A_ +#define _SAMD21G17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G17A_definitions SAMD21G17A definitions + * This file defines all structures and symbols for SAMD21G17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21G17A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010306) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G17A_H */ diff --git a/lib/samd21/samd21a/include/samd21g17au.h b/lib/samd21/samd21a/include/samd21g17au.h index a4752c5..630a7d6 100644 --- a/lib/samd21/samd21a/include/samd21g17au.h +++ b/lib/samd21/samd21a/include/samd21g17au.h @@ -1,583 +1,583 @@ -/** - * \file - * - * \brief Header file for SAMD21G17AU - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G17AU_ -#define _SAMD21G17AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions - * This file defines all structures and symbols for SAMD21G17AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21G17AU-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G17AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g17au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010310) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G17AU_H */ +/** + * \file + * + * \brief Header file for SAMD21G17AU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G17AU_ +#define _SAMD21G17AU_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G17AU_definitions SAMD21G17AU definitions + * This file defines all structures and symbols for SAMD21G17AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21G17AU-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G17AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g17au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010310) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G17AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G17AU_H */ diff --git a/lib/samd21/samd21a/include/samd21g18a.h b/lib/samd21/samd21a/include/samd21g18a.h index 381a73b..5774e9b 100644 --- a/lib/samd21/samd21a/include/samd21g18a.h +++ b/lib/samd21/samd21a/include/samd21g18a.h @@ -1,571 +1,571 @@ -/** - * \file - * - * \brief Header file for SAMD21G18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18A_ -#define _SAMD21G18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions - * This file defines all structures and symbols for SAMD21G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21G18A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ - ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pvReserved21; - void* pvReserved22; - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010305) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18A_H */ +/** + * \file + * + * \brief Header file for SAMD21G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G18A_ +#define _SAMD21G18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G18A_definitions SAMD21G18A definitions + * This file defines all structures and symbols for SAMD21G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21G18A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */ + ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pvReserved21; + void* pvReserved22; + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010305) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G18A_H */ diff --git a/lib/samd21/samd21a/include/samd21g18au.h b/lib/samd21/samd21a/include/samd21g18au.h index 06b66d0..c790793 100644 --- a/lib/samd21/samd21a/include/samd21g18au.h +++ b/lib/samd21/samd21a/include/samd21g18au.h @@ -1,583 +1,583 @@ -/** - * \file - * - * \brief Header file for SAMD21G18AU - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21G18AU_ -#define _SAMD21G18AU_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions - * This file defines all structures and symbols for SAMD21G18AU: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21G18AU-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ -/** \defgroup SAMD21G18AU_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21g18au.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x1001030F) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21G18AU_H */ +/** + * \file + * + * \brief Header file for SAMD21G18AU + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21G18AU_ +#define _SAMD21G18AU_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21G18AU_definitions SAMD21G18AU definitions + * This file defines all structures and symbols for SAMD21G18AU: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21G18AU-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ +/** \defgroup SAMD21G18AU_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21g18au.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x1001030F) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21G18AU */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21G18AU_H */ diff --git a/lib/samd21/samd21a/include/samd21j15a.h b/lib/samd21/samd21a/include/samd21j15a.h index 98679a9..eb18097 100644 --- a/lib/samd21/samd21a/include/samd21j15a.h +++ b/lib/samd21/samd21a/include/samd21j15a.h @@ -1,583 +1,583 @@ -/** - * \file - * - * \brief Header file for SAMD21J15A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J15A_ -#define _SAMD21J15A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions - * This file defines all structures and symbols for SAMD21J15A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21J15A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J15A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j15a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00001000) /* 4 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010303) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J15A_H */ +/** + * \file + * + * \brief Header file for SAMD21J15A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J15A_ +#define _SAMD21J15A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J15A_definitions SAMD21J15A definitions + * This file defines all structures and symbols for SAMD21J15A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21J15A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J15A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j15a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00008000) /* 32 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00001000) /* 4 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010303) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J15A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J15A_H */ diff --git a/lib/samd21/samd21a/include/samd21j16a.h b/lib/samd21/samd21a/include/samd21j16a.h index b1e9c1d..3504e60 100644 --- a/lib/samd21/samd21a/include/samd21j16a.h +++ b/lib/samd21/samd21a/include/samd21j16a.h @@ -1,583 +1,583 @@ -/** - * \file - * - * \brief Header file for SAMD21J16A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J16A_ -#define _SAMD21J16A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions - * This file defines all structures and symbols for SAMD21J16A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21J16A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J16A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j16a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00002000) /* 8 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010302) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J16A_H */ +/** + * \file + * + * \brief Header file for SAMD21J16A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J16A_ +#define _SAMD21J16A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J16A_definitions SAMD21J16A definitions + * This file defines all structures and symbols for SAMD21J16A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21J16A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J16A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j16a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00010000) /* 64 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00002000) /* 8 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010302) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J16A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J16A_H */ diff --git a/lib/samd21/samd21a/include/samd21j17a.h b/lib/samd21/samd21a/include/samd21j17a.h index 55d62a6..066f1a7 100644 --- a/lib/samd21/samd21a/include/samd21j17a.h +++ b/lib/samd21/samd21a/include/samd21j17a.h @@ -1,583 +1,583 @@ -/** - * \file - * - * \brief Header file for SAMD21J17A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J17A_ -#define _SAMD21J17A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions - * This file defines all structures and symbols for SAMD21J17A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21J17A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J17A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j17a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010301) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J17A_H */ +/** + * \file + * + * \brief Header file for SAMD21J17A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J17A_ +#define _SAMD21J17A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions + * This file defines all structures and symbols for SAMD21J17A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21J17A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J17A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j17a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00004000) /* 16 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010301) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J17A_H */ diff --git a/lib/samd21/samd21a/include/samd21j18a.h b/lib/samd21/samd21a/include/samd21j18a.h index 40587c8..37d55c4 100644 --- a/lib/samd21/samd21a/include/samd21j18a.h +++ b/lib/samd21/samd21a/include/samd21j18a.h @@ -1,583 +1,583 @@ -/** - * \file - * - * \brief Header file for SAMD21J18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD21J18A_ -#define _SAMD21J18A_ - -/** - * \ingroup SAMD21_definitions - * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions - * This file defines all structures and symbols for SAMD21J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M0+ Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD21J18A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ - SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ - WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ - RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ - EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ - NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ - DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ - USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ - EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ - SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ - SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ - SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ - SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ - SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ - SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ - TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ - TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ - TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ - TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ - ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ - AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ - DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ - PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ - I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ - - PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pvReservedM12; - void* pvReservedM11; - void* pvReservedM10; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pvReservedM4; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnSYSCTRL_Handler; /* 1 System Control */ - void* pfnWDT_Handler; /* 2 Watchdog Timer */ - void* pfnRTC_Handler; /* 3 Real-Time Counter */ - void* pfnEIC_Handler; /* 4 External Interrupt Controller */ - void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ - void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ - void* pfnUSB_Handler; /* 7 Universal Serial Bus */ - void* pfnEVSYS_Handler; /* 8 Event System Interface */ - void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ - void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ - void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ - void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ - void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ - void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ - void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ - void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ - void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ - void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ - void* pfnADC_Handler; /* 23 Analog Digital Converter */ - void* pfnAC_Handler; /* 24 Analog Comparators */ - void* pfnDAC_Handler; /* 25 Digital Analog Converter */ - void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ - void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ - void* pvReserved28; -} DeviceVectors; - -/* Cortex-M0+ processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void SVCall_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void SYSCTRL_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_Handler ( void ); -void NVMCTRL_Handler ( void ); -void DMAC_Handler ( void ); -void USB_Handler ( void ); -void EVSYS_Handler ( void ); -void SERCOM0_Handler ( void ); -void SERCOM1_Handler ( void ); -void SERCOM2_Handler ( void ); -void SERCOM3_Handler ( void ); -void SERCOM4_Handler ( void ); -void SERCOM5_Handler ( void ); -void TCC0_Handler ( void ); -void TCC1_Handler ( void ); -void TCC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void ADC_Handler ( void ); -void AC_Handler ( void ); -void DAC_Handler ( void ); -void PTC_Handler ( void ); -void I2S_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals - */ - -#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd21.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/i2s.h" -#include "component/mtb.h" -#include "component/nvmctrl.h" -#include "component/pac.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/rtc.h" -#include "component/sercom.h" -#include "component/sysctrl.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/gclk.h" -#include "instance/sbmatrix.h" -#include "instance/i2s.h" -#include "instance/mtb.h" -#include "instance/nvmctrl.h" -#include "instance/pac0.h" -#include "instance/pac1.h" -#include "instance/pac2.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/ptc.h" -#include "instance/rtc.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sysctrl.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ -#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ - -// Peripheral instances on HPB1 bridge -#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_PORT 35 /**< \brief Port Module (PORT) */ -#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ -#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ -#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ - -// Peripheral instances on HPB2 bridge -#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ -#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ -#define ID_AC 81 /**< \brief Analog Comparators (AC) */ -#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ -#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ -#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ - -#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42004400) /**< \brief (AC) APB Base Address */ -#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ -#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ -#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ -#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ -#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ -#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ -#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ -#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ -#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ -#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ -#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ -#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ -#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ -#define USB (0x41005000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ -#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ - -#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ -#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ -#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ -#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ -#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ -#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ -#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ -#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ -#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ -#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ -#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ -#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ - -#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ -#define PTC_GCLK_ID 34 -#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ -#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ - -#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ -#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ -#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ - -#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD21J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd21j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 64 -#define FLASH_NB_OF_PAGES 4096 -#define FLASH_USER_PAGE_SIZE 64 -#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ -#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x10010300) -#define EIC_EXTINT_NUM 16 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD21J18A_H */ +/** + * \file + * + * \brief Header file for SAMD21J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD21J18A_ +#define _SAMD21J18A_ + +/** + * \ingroup SAMD21_definitions + * \addtogroup SAMD21J18A_definitions SAMD21J18A definitions + * This file defines all structures and symbols for SAMD21J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M0+ Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD21J18A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */ + SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */ + WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */ + RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */ + EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */ + NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */ + DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */ + USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */ + EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */ + SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */ + SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */ + SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */ + SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */ + SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */ + SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */ + TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */ + TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */ + TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */ + TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */ + ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */ + AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */ + DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */ + PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */ + I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */ + + PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pvReservedM12; + void* pvReservedM11; + void* pvReservedM10; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pvReservedM4; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnSYSCTRL_Handler; /* 1 System Control */ + void* pfnWDT_Handler; /* 2 Watchdog Timer */ + void* pfnRTC_Handler; /* 3 Real-Time Counter */ + void* pfnEIC_Handler; /* 4 External Interrupt Controller */ + void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ + void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ + void* pfnUSB_Handler; /* 7 Universal Serial Bus */ + void* pfnEVSYS_Handler; /* 8 Event System Interface */ + void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ + void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ + void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ + void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ + void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ + void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ + void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ + void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ + void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ + void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ + void* pfnADC_Handler; /* 23 Analog Digital Converter */ + void* pfnAC_Handler; /* 24 Analog Comparators */ + void* pfnDAC_Handler; /* 25 Digital Analog Converter */ + void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ + void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ + void* pvReserved28; +} DeviceVectors; + +/* Cortex-M0+ processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void SVCall_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void SYSCTRL_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_Handler ( void ); +void NVMCTRL_Handler ( void ); +void DMAC_Handler ( void ); +void USB_Handler ( void ); +void EVSYS_Handler ( void ); +void SERCOM0_Handler ( void ); +void SERCOM1_Handler ( void ); +void SERCOM2_Handler ( void ); +void SERCOM3_Handler ( void ); +void SERCOM4_Handler ( void ); +void SERCOM5_Handler ( void ); +void TCC0_Handler ( void ); +void TCC1_Handler ( void ); +void TCC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void ADC_Handler ( void ); +void AC_Handler ( void ); +void DAC_Handler ( void ); +void PTC_Handler ( void ); +void I2S_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ + +#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd21.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/i2s.h" +#include "component/mtb.h" +#include "component/nvmctrl.h" +#include "component/pac.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/rtc.h" +#include "component/sercom.h" +#include "component/sysctrl.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/gclk.h" +#include "instance/sbmatrix.h" +#include "instance/i2s.h" +#include "instance/mtb.h" +#include "instance/nvmctrl.h" +#include "instance/pac0.h" +#include "instance/pac1.h" +#include "instance/pac2.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/ptc.h" +#include "instance/rtc.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sysctrl.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ +#define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ + +// Peripheral instances on HPB1 bridge +#define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_PORT 35 /**< \brief Port Module (PORT) */ +#define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ +#define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ +#define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ + +// Peripheral instances on HPB2 bridge +#define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ +#define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ +#define ID_AC 81 /**< \brief Analog Comparators (AC) */ +#define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ +#define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ +#define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ + +#define ID_PERIPH_COUNT 85 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42004400) /**< \brief (AC) APB Base Address */ +#define ADC (0x42004000) /**< \brief (ADC) APB Base Address */ +#define DAC (0x42004800) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x41004800) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40001800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x42000400) /**< \brief (EVSYS) APB Base Address */ +#define GCLK (0x40000C00) /**< \brief (GCLK) APB Base Address */ +#define SBMATRIX (0x41007000) /**< \brief (SBMATRIX) APB Base Address */ +#define I2S (0x42005000) /**< \brief (I2S) APB Base Address */ +#define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define PAC0 (0x40000000) /**< \brief (PAC0) APB Base Address */ +#define PAC1 (0x41000000) /**< \brief (PAC1) APB Base Address */ +#define PAC2 (0x42000000) /**< \brief (PAC2) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41004400) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ +#define PTC (0x42004C00) /**< \brief (PTC) APB Base Address */ +#define RTC (0x40001400) /**< \brief (RTC) APB Base Address */ +#define SERCOM0 (0x42000800) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x42000C00) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x42001000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x42001400) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x42001800) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x42001C00) /**< \brief (SERCOM5) APB Base Address */ +#define SYSCTRL (0x40000800) /**< \brief (SYSCTRL) APB Base Address */ +#define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42003000) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42003400) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x42003800) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x42003C00) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x42002000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x42002400) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42002800) /**< \brief (TCC2) APB Base Address */ +#define USB (0x41005000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40001000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ +#define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ + +#define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ +#define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ +#define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ +#define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ +#define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ +#define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ +#define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ +#define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ +#define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ +#define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ +#define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ +#define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ + +#define PTC ((void *)0x42004C00UL) /**< \brief (PTC) APB Base Address */ +#define PTC_GCLK_ID 34 +#define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ +#define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ + +#define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ +#define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ +#define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ + +#define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD21J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd21j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ + +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 64 +#define FLASH_NB_OF_PAGES 4096 +#define FLASH_USER_PAGE_SIZE 64 +#define HMCRAMC0_SIZE _UL_(0x00008000) /* 32 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ +#define HMCRAMC0_ADDR _UL_(0x20000000) /**< HMCRAMC0 base address */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x10010300) +#define EIC_EXTINT_NUM 16 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD21J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD21J18A_H */ diff --git a/lib/samd21/samd21a/include/system_samd21.h b/lib/samd21/samd21a/include/system_samd21.h index de6f4f1..ed948b6 100644 --- a/lib/samd21/samd21a/include/system_samd21.h +++ b/lib/samd21/samd21a/include/system_samd21.h @@ -1,48 +1,48 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAMD21_H_INCLUDED_ -#define _SYSTEM_SAMD21_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD21_H_INCLUDED */ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAMD21_H_INCLUDED_ +#define _SYSTEM_SAMD21_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAMD21_H_INCLUDED */ diff --git a/lib/samd51/samd51a/gcc/system_samd51.c b/lib/samd51/samd51a/gcc/system_samd51.c index 310dda3..bebd18f 100644 --- a/lib/samd51/samd51a/gcc/system_samd51.c +++ b/lib/samd51/samd51a/gcc/system_samd51.c @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup. - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#include "samd51.h" - -/** - * Initial system clock frequency. The System RC Oscillator (RCSYS) provides - * the source for the main clock at chip startup. - */ -#define __SYSTEM_CLOCK (48000000) - -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -/** - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void) -{ - // Keep the default device state after reset - SystemCoreClock = __SYSTEM_CLOCK; - return; -} - -/** - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void) -{ - // Not implemented - SystemCoreClock = __SYSTEM_CLOCK; - return; -} +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "samd51.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/lib/samd51/samd51a/include/component-version.h b/lib/samd51/samd51a/include/component-version.h index ec33360..2e2976f 100644 --- a/lib/samd51/samd51a/include/component-version.h +++ b/lib/samd51/samd51a/include/component-version.h @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Component version header file - * - * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _COMPONENT_VERSION_H_INCLUDED -#define _COMPONENT_VERSION_H_INCLUDED - -#define COMPONENT_VERSION_MAJOR 1 -#define COMPONENT_VERSION_MINOR 1 - -// -// The COMPONENT_VERSION define is composed of the major and the minor version number. -// -// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. -// The rest of the COMPONENT_VERSION is the major version. -// -#define COMPONENT_VERSION 10001 - -// -// The build number does not refer to the component, but to the build number -// of the device pack that provides the component. -// -#define BUILD_NUMBER 96 - -// -// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. -// -#define COMPONENT_VERSION_STRING "1.1" - -// -// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. -// -// The COMPONENT_DATE_STRING is written out using the following strftime pattern. -// -// "%Y-%m-%d %H:%M:%S" -// -// -#define COMPONENT_DATE_STRING "2018-09-21 03:51:18" - -#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ - +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2018 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 1 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10001 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 96 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.1" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2018-09-21 03:51:18" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/lib/samd51/samd51a/include/component/ac.h b/lib/samd51/samd51a/include/component/ac.h index 30206f8..f0f0371 100644 --- a/lib/samd51/samd51a/include/component/ac.h +++ b/lib/samd51/samd51a/include/component/ac.h @@ -1,598 +1,598 @@ -/** - * \file - * - * \brief Component description for AC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_AC_COMPONENT_ -#define _SAMD51_AC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_AC Analog Comparators */ -/*@{*/ - -#define AC_U2501 -#define REV_AC 0x100 - -/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ -#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ - -#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ -#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) -#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ -#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) -#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ - -/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ - uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ -#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ - -#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ -#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) -#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ -#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) -#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ -#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) -#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) -#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ - -/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ - uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ - uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ - uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ - uint16_t :2; /*!< bit: 2.. 3 Reserved */ - uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ - uint16_t :2; /*!< bit: 10..11 Reserved */ - uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ - uint16_t :2; /*!< bit: 14..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} AC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ -#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ - -#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ -#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) -#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ -#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) -#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ -#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) -#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) -#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ -#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) -#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ -#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) -#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) -#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ -#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) -#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ -#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) -#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ -#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) -#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) -#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) -#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ -#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) -#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ -#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) -#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) -#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ - -/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ -#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ -#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) -#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ -#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) -#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ -#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) -#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) -#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ -#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) -#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ -#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) -#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) -#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ - -/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ - uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ - uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ -#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ - -#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ -#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) -#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ -#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) -#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ -#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) -#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) -#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ -#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) -#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ -#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) -#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) -#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ - -/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ - __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ - __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ - __I uint8_t WIN:1; /*!< bit: 4 Window x */ - __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ -#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) -#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ -#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) -#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ -#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) -#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) -#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ -#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) -#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ -#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) -#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) -#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ - -/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ - uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ - uint8_t :2; /*!< bit: 2.. 3 Reserved */ - uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ -#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ - -#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ -#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) -#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ -#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) -#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ -#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) -#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) -#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ -#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) -#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ -#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ -#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ -#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) -#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ - -/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ - uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} AC_STATUSB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ -#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ - -#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ -#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) -#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ -#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) -#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ -#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) -#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) -#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ - -/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ -#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ - -#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ -#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) -#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ - -/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ - uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_WINCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ -#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ - -#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ -#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) -#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ -#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) -#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ -#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ -#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ -#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ -#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) -#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ - -/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AC_SCALER_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ -#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ - -#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ -#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) -#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) -#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ - -/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ - uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ - uint32_t :1; /*!< bit: 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ - uint32_t :1; /*!< bit: 11 Reserved */ - uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ - uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ - uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ - uint32_t :1; /*!< bit: 18 Reserved */ - uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ - uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ - uint32_t :1; /*!< bit: 27 Reserved */ - uint32_t OUT:2; /*!< bit: 28..29 Output */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AC_COMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ -#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ - -#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ -#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) -#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ -#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) -#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ -#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) -#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ -#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ -#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ -#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ -#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) -#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ -#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) -#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ -#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) -#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ -#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ -#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ -#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ -#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) -#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ -#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) -#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ -#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ -#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ -#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ -#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ -#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) -#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ -#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) -#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ -#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) -#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ -#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) -#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ -#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) -#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ -#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) -#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ -#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ -#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ -#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) -#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ -#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) -#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ -#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ -#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ -#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) -#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ -#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) -#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ -#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) -#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ - -/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ - uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ - uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ - uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :3; /*!< bit: 0.. 2 Reserved */ - uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ - uint32_t :27; /*!< bit: 5..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} AC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ -#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ - -#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ -#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) -#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ -#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) -#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ -#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) -#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) -#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ -#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) -#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) -#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ - -/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ - uint16_t :14; /*!< bit: 2..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} AC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ -#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ - -#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ -#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) -#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) -#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ - -/** \brief AC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ - __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ - __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ - __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ - __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ - __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ - RoReg8 Reserved1[0x1]; - __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ - RoReg8 Reserved2[0x2]; - __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ - RoReg8 Reserved3[0x8]; - __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ - __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ -} Ac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_AC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_AC_COMPONENT_ +#define _SAMD51_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_AC Analog Comparators */ +/*@{*/ + +#define AC_U2501 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ + uint16_t :14; /*!< bit: 2..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} AC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ +#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ + +#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_AC_COMPONENT_ */ diff --git a/lib/samd51/samd51a/include/component/adc.h b/lib/samd51/samd51a/include/component/adc.h index 0dbe8e3..a379a22 100644 --- a/lib/samd51/samd51a/include/component/adc.h +++ b/lib/samd51/samd51a/include/component/adc.h @@ -1,871 +1,871 @@ -/** - * \file - * - * \brief Component description for ADC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_ADC_COMPONENT_ -#define _SAMD51_ADC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR ADC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_ADC Analog Digital Converter */ -/*@{*/ - -#define ADC_U2500 -#define REV_ADC 0x100 - -/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t ENABLE:1; /*!< bit: 1 Enable */ - uint16_t :1; /*!< bit: 2 Reserved */ - uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ - uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ - uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ - uint16_t :4; /*!< bit: 11..14 Reserved */ - uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ -#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ - -#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ -#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) -#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ -#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) -#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ -#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) -#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ -#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ -#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) -#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ -#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) -#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ -#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) -#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ -#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) -#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ -#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) -#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ -#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ -#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ -#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ -#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ -#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ -#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ -#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ -#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) -#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ -#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) -#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ - -/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ - uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ - uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ - uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ - uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ - uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ - uint8_t :2; /*!< bit: 6.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ -#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ - -#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ -#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) -#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ -#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) -#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ -#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) -#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ -#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) -#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ -#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) -#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ -#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) -#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ - -/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ -#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ - -#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ -#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) -#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ - -/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ - uint16_t :2; /*!< bit: 5.. 6 Reserved */ - uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ - uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ - uint16_t :2; /*!< bit: 13..14 Reserved */ - uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_INPUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ -#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ - -#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ -#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) -#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ -#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ -#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ -#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ -#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ -#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ -#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) -#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ -#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) -#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ -#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) -#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ -#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ -#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ -#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) -#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ -#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) -#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ - -/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ - uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ - uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ - uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ - uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ -#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ - -#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ -#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) -#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ -#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) -#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ -#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) -#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ -#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) -#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ -#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ -#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ -#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ -#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) -#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ -#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) -#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ -#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ -#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ -#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ -#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) -#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ -#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) -#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ - -/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ - uint8_t :3; /*!< bit: 4.. 6 Reserved */ - uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_REFCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ -#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ - -#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ -#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) -#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ -#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ -#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ -#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ -#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ -#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) -#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ -#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) -#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ - -/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ - uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_AVGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ -#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ - -#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ -#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) -#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ -#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ -#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ -#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ -#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ -#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ -#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ -#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ -#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ -#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ -#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) -#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ -#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) -#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) -#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ - -/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ - uint8_t :1; /*!< bit: 6 Reserved */ - uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SAMPCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ -#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ - -#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ -#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) -#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) -#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ -#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) -#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ - -/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINLT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ -#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ - -#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ -#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) -#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) -#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ - -/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_WINUT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ -#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ - -#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ -#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) -#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) -#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ - -/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_GAINCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ -#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ - -#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ -#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) -#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) -#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ - -/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_OFFSETCORR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ -#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ - -#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ -#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) -#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) -#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ - -/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ - uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_SWTRIG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ -#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ - -#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ -#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) -#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ -#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) -#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ - -/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ -#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ -#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) -#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ -#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) -#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ -#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) -#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ - -/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ - uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ - uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ -#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ - -#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ -#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) -#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ -#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) -#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ -#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) -#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ - -/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ - __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ - __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ -#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) -#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ -#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) -#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ -#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) -#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ - -/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ - uint8_t :1; /*!< bit: 1 Reserved */ - uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} ADC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ -#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ - -#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ -#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) -#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ -#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) -#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) -#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ - -/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ - uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ - uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ - uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ - uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ - uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ - uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ - uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ - uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ - uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ - uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ - uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ - uint32_t :20; /*!< bit: 12..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ -#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ - -#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ -#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) -#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ -#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) -#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ -#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) -#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ -#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) -#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ -#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) -#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ -#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) -#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ -#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) -#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) -#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ -#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) -#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ -#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) -#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ -#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) -#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ -#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) -#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ - -/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ -#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ - -#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ -#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) -#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) -#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ - -/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ -#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ - -#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ -#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) -#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ -#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) -#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ -#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) -#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ -#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) -#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ -#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) -#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ -#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) -#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ -#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) -#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ -#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) -#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ -#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) -#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ -#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) -#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ - -/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ - uint32_t CTRLB:1; /*!< bit: 1 Control B */ - uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ - uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ - uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ - uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ - uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ - uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ - uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ - uint32_t :22; /*!< bit: 9..30 Reserved */ - uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} ADC_DSEQSTAT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ -#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ - -#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ -#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) -#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ -#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) -#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ -#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) -#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ -#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) -#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ -#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) -#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ -#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) -#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ -#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) -#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ -#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) -#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ -#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) -#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ -#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) -#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ - -/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ -#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ - -#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ -#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) -#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) -#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ - -/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_RESS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ -#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ - -#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ -#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) -#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) -#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ - -/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ - uint16_t :1; /*!< bit: 3 Reserved */ - uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ - uint16_t :1; /*!< bit: 7 Reserved */ - uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ - uint16_t :5; /*!< bit: 11..15 Reserved */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} ADC_CALIB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ -#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ - -#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ -#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) -#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) -#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ -#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) -#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) -#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ -#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) -#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) -#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ - -/** \brief ADC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ - __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ - __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ - __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ - __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ - RoReg8 Reserved1[0x1]; - __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ - __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ - __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ - __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ - __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ - __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ - __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ - RoReg8 Reserved2[0x17]; - __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ - __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ - __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ - __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ - __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ - __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ - __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ - __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ - __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ - RoReg8 Reserved3[0x2]; - __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ - RoReg8 Reserved4[0x2]; - __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ -} Adc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_ADC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_ADC_COMPONENT_ +#define _SAMD51_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2500 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t :1; /*!< bit: 2 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ + uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :4; /*!< bit: 11..14 Reserved */ + uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ +#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) +#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :2; /*!< bit: 5.. 6 Reserved */ + uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :2; /*!< bit: 13..14 Reserved */ + uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ +#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ +#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ +#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ +#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) +#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ +#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) +#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ + uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ + uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ + uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ + uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ + uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ + uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ + uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ + uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) +#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ +#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ + +#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ +#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) +#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ +#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) +#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ +#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) +#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ +#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) +#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ +#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) +#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ +#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) +#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ +#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) +#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ +#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) +#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ +#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) +#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ +#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) +#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQSTAT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ +#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) +#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ +#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) +#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ +#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) +#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ +#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) +#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ +#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) +#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ +#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) +#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ +#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) +#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ +#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) +#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ +#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) +#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ +#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) +#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ +#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ + +#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ + RoReg8 Reserved1[0x1]; + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x17]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ + __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ + RoReg8 Reserved3[0x2]; + __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ + RoReg8 Reserved4[0x2]; + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_ADC_COMPONENT_ */ diff --git a/lib/samd51/samd51a/include/component/aes.h b/lib/samd51/samd51a/include/component/aes.h index 1d1c0f9..eca6f87 100644 --- a/lib/samd51/samd51a/include/component/aes.h +++ b/lib/samd51/samd51a/include/component/aes.h @@ -1,375 +1,375 @@ -/** - * \file - * - * \brief Component description for AES - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_AES_COMPONENT_ -#define _SAMD51_AES_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR AES */ -/* ========================================================================== */ -/** \addtogroup SAMD51_AES Advanced Encryption Standard */ -/*@{*/ - -#define AES_U2238 -#define REV_AES 0x220 - -/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Enable */ - uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ - uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ - uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ - uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ - uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ - uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ - uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ - uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ - uint32_t :1; /*!< bit: 15 Reserved */ - uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ - uint32_t :12; /*!< bit: 20..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} AES_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ -#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ - -#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ -#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) -#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ -#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) -#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ -#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) -#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ -#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ -#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ -#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ -#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ -#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ -#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ -#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) -#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ -#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) -#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ -#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) -#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ -#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) -#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ -#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) -#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ -#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ -#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ -#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) -#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ -#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ -#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ -#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) -#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ -#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ -#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) -#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ -#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ -#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) -#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ -#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ -#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ -#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) -#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ -#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) -#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) -#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ - -/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ - uint8_t NEWMSG:1; /*!< bit: 1 New message */ - uint8_t EOM:1; /*!< bit: 2 End of message */ - uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ -#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ - -#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ -#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) -#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ -#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) -#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ -#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) -#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ -#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) -#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ - -/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ -#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ - -#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ -#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) -#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) -#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ - -/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ - uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ -#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ - -#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ -#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) -#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ -#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) -#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ - -/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ - __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ - __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ -#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ - -#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ -#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) -#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ -#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) -#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ - -/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DATABUFPTR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ -#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ - -#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ -#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) -#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) -#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ - -/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} AES_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ -#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ - -#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ -#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) -#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ - -/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_KEYWORD_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ -#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ -#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ - -/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INDATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ -#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ -#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ - -/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_INTVECTV_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ -#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ -#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ - -/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_HASHKEY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ -#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ -#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ - -/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_GHASH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ -#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ -#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ - -/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_CIPLEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ -#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ -#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ - -/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - uint32_t reg; /*!< Type used for register access */ -} AES_RANDSEED_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ -#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ -#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ - -/** \brief AES hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ - __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ - __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ - __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ - __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ - __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ - __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ - RoReg8 Reserved1[0x2]; - __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ - RoReg8 Reserved2[0xC]; - __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ - __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ - RoReg8 Reserved3[0x10]; - __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ - __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ - RoReg8 Reserved4[0x4]; - __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ - __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ -} Aes; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_AES_COMPONENT_ */ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_AES_COMPONENT_ +#define _SAMD51_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAMD51_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x220 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ + uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ + uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ + uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_AES_COMPONENT_ */ diff --git a/lib/samd51/samd51a/include/component/ccl.h b/lib/samd51/samd51a/include/component/ccl.h index b51acc8..6c71395 100644 --- a/lib/samd51/samd51a/include/component/ccl.h +++ b/lib/samd51/samd51a/include/component/ccl.h @@ -1,228 +1,228 @@ -/** - * \file - * - * \brief Component description for CCL - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CCL_COMPONENT_ -#define _SAMD51_CCL_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CCL */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CCL Configurable Custom Logic */ -/*@{*/ - -#define CCL_U2225 -#define REV_CCL 0x110 - -/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable */ - uint8_t :4; /*!< bit: 2.. 5 Reserved */ - uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint8_t :1; /*!< bit: 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ -#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ - -#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ -#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) -#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ -#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) -#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ -#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) -#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ - -/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} CCL_SEQCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ -#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ - -#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ -#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) -#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ -#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ -#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ -#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ -#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ -#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) -#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ - -/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ - uint32_t :1; /*!< bit: 6 Reserved */ - uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ - uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ - uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ - uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ - uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ - uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ - uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ - uint32_t :1; /*!< bit: 23 Reserved */ - uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CCL_LUTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ -#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ - -#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ -#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) -#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ -#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) -#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ -#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ -#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ -#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) -#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ -#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) -#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ -#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) -#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) -#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ -#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) -#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) -#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ -#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) -#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ -#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ -#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ -#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ -#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ -#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ -#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ -#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ -#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ -#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ -#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) -#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ -#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) -#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ -#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) -#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ -#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) -#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ -#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) -#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) -#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ - -/** \brief CCL hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ - RoReg8 Reserved1[0x3]; - __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ - RoReg8 Reserved2[0x2]; - __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ -} Ccl; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_CCL_COMPONENT_ */ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_CCL_COMPONENT_ +#define _SAMD51_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAMD51_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x110 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ + uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_CCL_COMPONENT_ */ diff --git a/lib/samd51/samd51a/include/component/cmcc.h b/lib/samd51/samd51a/include/component/cmcc.h index 1b17736..060dba7 100644 --- a/lib/samd51/samd51a/include/component/cmcc.h +++ b/lib/samd51/samd51a/include/component/cmcc.h @@ -1,357 +1,357 @@ -/** - * \file - * - * \brief Component description for CMCC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_CMCC_COMPONENT_ -#define _SAMD51_CMCC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR CMCC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */ -/*@{*/ - -#define CMCC_U2015 -#define REV_CMCC 0x600 - -/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ - uint32_t :2; /*!< bit: 2.. 3 Reserved */ - uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ - uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ - uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ - uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ - uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ - uint32_t :18; /*!< bit: 14..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_TYPE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ -#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ - -#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ -#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) -#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ -#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) -#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ -#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) -#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ -#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ -#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ -#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) -#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ -#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) -#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ -#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) -#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ -#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) -#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ -#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) -#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ -#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) -#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ - -/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :1; /*!< bit: 0 Reserved */ - uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ - uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ - uint32_t :1; /*!< bit: 3 Reserved */ - uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ - uint32_t :25; /*!< bit: 7..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ -#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ - -#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ -#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) -#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ -#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) -#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ -#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ -#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) -#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ - -/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ -#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ - -#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ -#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) -#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ - -/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_SR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ -#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ - -#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ -#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) -#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ - -/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_LCKWAY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ -#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ - -#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ -#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) -#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) -#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ - -/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ -#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ - -#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ -#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) -#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ - -/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t :4; /*!< bit: 0.. 3 Reserved */ - uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ - uint32_t :16; /*!< bit: 12..27 Reserved */ - uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MAINT1_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ -#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ - -#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ -#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) -#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) -#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ -#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) -#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ -#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) -#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ - -/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ - uint32_t :30; /*!< bit: 2..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCFG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ -#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ - -#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ -#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) -#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ -#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ -#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ -#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) -#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ - -/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MEN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ -#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ - -#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ -#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) -#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ - -/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ - uint32_t :31; /*!< bit: 1..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ -#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ - -#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ -#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) -#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ - -/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} CMCC_MSR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ -#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ - -#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ -#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) -#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) -#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ - -/** \brief CMCC APB hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ - __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ - __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ - __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ - __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ - RoReg8 Reserved1[0xC]; - __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ - __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ - __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ - __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ - __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ - __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ -} Cmcc; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_CMCC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for CMCC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_CMCC_COMPONENT_ +#define _SAMD51_CMCC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CMCC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_CMCC Cortex M Cache Controller */ +/*@{*/ + +#define CMCC_U2015 +#define REV_CMCC 0x600 + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ + uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ + uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ + uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ + uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ + uint32_t :18; /*!< bit: 14..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_TYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ +#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ + +#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ +#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) +#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ +#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) +#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ +#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) +#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ + uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ +#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ + +#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ +#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) +#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ +#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) +#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ +#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ + +#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ +#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) +#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_SR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ +#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ + +#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ +#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) +#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_LCKWAY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ + +#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ + +#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ +#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) +#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ + uint32_t :16; /*!< bit: 12..27 Reserved */ + uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ + +#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ +#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ + +#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ +#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ + +#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ +#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) +#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ + +#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ +#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) +#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ +#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ + +#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ + +/** \brief CMCC APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ + __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ + __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ + __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + RoReg8 Reserved1[0xC]; + __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} Cmcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_CMCC_COMPONENT_ */ diff --git a/lib/samd51/samd51a/include/component/dac.h b/lib/samd51/samd51a/include/component/dac.h index 63ac31b..663c891 100644 --- a/lib/samd51/samd51a/include/component/dac.h +++ b/lib/samd51/samd51a/include/component/dac.h @@ -1,544 +1,544 @@ -/** - * \file - * - * \brief Component description for DAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_DAC_COMPONENT_ -#define _SAMD51_DAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DAC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */ -/*@{*/ - -#define DAC_U2502 -#define REV_DAC 0x100 - -/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t SWRST:1; /*!< bit: 0 Software Reset */ - uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ -#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ - -#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ -#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) -#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ -#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) -#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ - -/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ - uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_CTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ -#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ - -#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ -#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) -#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ -#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) -#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ -#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ -#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ -#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ -#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) -#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ - -/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ - uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ - uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ - uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ - uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ - uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ - uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ - uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ - uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ - uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ - uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_EVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ -#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ - -#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ -#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) -#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ -#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) -#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ -#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) -#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) -#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ -#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) -#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ -#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) -#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ -#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) -#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) -#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ -#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) -#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ -#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) -#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ -#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) -#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) -#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ -#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) -#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ -#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) -#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ -#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) -#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) -#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ - -/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ -#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ - -#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) -#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) -#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ -#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) -#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) -#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) -#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) -#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) -#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) -#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) -#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) -#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ -#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) -#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) -#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) -#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) -#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ -#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) -#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) -#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ - -/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ - uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ - uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ - uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ - uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ - uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ - uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ - uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ - uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ - uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ - uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ -#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ - -#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) -#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) -#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ -#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) -#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) -#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) -#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) -#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ -#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) -#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) -#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) -#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) -#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ -#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) -#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) -#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) -#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ -#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) -#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ -#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) -#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) -#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ - -/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ - __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ - __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ - __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ - __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ - __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ - __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ - __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ - } bit; /*!< Structure used for bit access */ - struct { - __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ - __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ - __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ - __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_INTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ -#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ - -#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ -#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) -#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ -#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) -#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ -#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) -#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) -#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ -#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) -#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ -#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) -#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ -#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) -#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) -#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ -#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) -#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ -#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) -#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ -#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) -#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) -#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ -#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) -#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ -#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) -#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ -#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) -#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) -#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ - -/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ - uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ - uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ - uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ - uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } vec; /*!< Structure used for vec access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_STATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ -#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ - -#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ -#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) -#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ -#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) -#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ -#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) -#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) -#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ -#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) -#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ -#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) -#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ -#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) -#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) -#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ - -/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ - uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ - uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ - uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ - uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t :2; /*!< bit: 0.. 1 Reserved */ - uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ - uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ - uint32_t :26; /*!< bit: 6..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DAC_SYNCBUSY_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ -#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ - -#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ -#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) -#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ -#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) -#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ -#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) -#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ -#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) -#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ -#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) -#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) -#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ -#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) -#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ -#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) -#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ -#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) -#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) -#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ - -/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ - uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ - uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ - uint16_t :1; /*!< bit: 4 Reserved */ - uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ - uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ - uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ - uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ - uint16_t :1; /*!< bit: 12 Reserved */ - uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DACCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ -#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ - -#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ -#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) -#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ -#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) -#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ -#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) -#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ -#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ -#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ -#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) -#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ -#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) -#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ -#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) -#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ -#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) -#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ -#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) -#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) -#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ -#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) -#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) -#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ - -/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ -#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ - -#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ -#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) -#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) -#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ - -/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_DATABUF_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ -#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ - -#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ -#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) -#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) -#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ - -/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ -#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ - -#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ -#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) -#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ - -/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DAC_RESULT_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ -#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ - -#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ -#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) -#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) -#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ - -/** \brief DAC hardware registers */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef struct { - __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ - __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ - __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ - RoReg8 Reserved1[0x1]; - __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ - __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ - __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ - __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ - __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ - __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ - __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ - __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ - __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ - RoReg8 Reserved2[0x3]; - __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ -} Dac; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -/*@}*/ - -#endif /* _SAMD51_DAC_COMPONENT_ */ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_DAC_COMPONENT_ +#define _SAMD51_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAMD51_DAC Digital-to-Analog Converter */ +/*@{*/ + +#define DAC_U2502 +#define REV_DAC 0x100 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ + uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ +#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ + uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ + uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ + uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ + uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ + uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ + uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ + uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ + uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ + uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ + uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ +#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) +#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ +#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ +#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) +#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ +#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ +#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) +#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ +#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) +#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ +#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) +#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ +#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) +#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) +#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) +#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) +#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) +#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) +#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) +#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) +#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) +#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) +#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) +#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) +#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) +#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) +#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) +#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) +#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) +#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) +#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ + __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ + __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ + __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ + __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ + __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ + __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ + __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ + __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ + __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ + __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ +#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) +#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ +#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ +#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) +#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ +#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) +#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ +#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) +#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ +#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) +#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ +#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) +#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ +#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) +#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) +#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ + uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ + uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ + uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ + uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ +#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) +#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ +#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ +#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) +#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ +#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) +#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) +#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ + uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ + uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ + uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ + uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ + uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ +#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ +#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) +#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ +#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ +#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) +#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ +#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) +#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ + uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ + uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ + uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ + uint16_t :1; /*!< bit: 12 Reserved */ + uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DACCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ + +#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ +#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ +#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ +#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) +#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ +#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) +#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ +#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) +#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ + +#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ +#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ +#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ + +#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ + __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ + __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ + __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x3]; + __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAMD51_DAC_COMPONENT_ */ diff --git a/lib/samd51/samd51a/include/component/dmac.h b/lib/samd51/samd51a/include/component/dmac.h index a173f99..011cec2 100644 --- a/lib/samd51/samd51a/include/component/dmac.h +++ b/lib/samd51/samd51a/include/component/dmac.h @@ -1,1416 +1,1416 @@ -/** - * \file - * - * \brief Component description for DMAC - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_DMAC_COMPONENT_ -#define _SAMD51_DMAC_COMPONENT_ - -/* ========================================================================== */ -/** SOFTWARE API DEFINITION FOR DMAC */ -/* ========================================================================== */ -/** \addtogroup SAMD51_DMAC Direct Memory Access Controller */ -/*@{*/ - -#define DMAC_U2503 -#define REV_DMAC 0x101 - -/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t SWRST:1; /*!< bit: 0 Software Reset */ - uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ - uint16_t :6; /*!< bit: 2.. 7 Reserved */ - uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ - uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ - uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ - uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } bit; /*!< Structure used for bit access */ - struct { - uint16_t :8; /*!< bit: 0.. 7 Reserved */ - uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ - uint16_t :4; /*!< bit: 12..15 Reserved */ - } vec; /*!< Structure used for vec access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ -#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ - -#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ -#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) -#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ -#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) -#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ -#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) -#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ -#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) -#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ -#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) -#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ -#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) -#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ -#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) -#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) -#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ - -/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ - uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ - uint16_t :4; /*!< bit: 4.. 7 Reserved */ - uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ - uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_CRCCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ -#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ - -#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ -#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ -#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) -#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ -#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) -#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ -#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) -#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ -#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) -#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ -#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ -#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) -#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ -#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) -#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ -#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ -#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) -#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ - -/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCDATAIN_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ -#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ - -#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ -#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) -#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) -#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ - -/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CRCCHKSUM_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ -#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ - -#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ -#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) -#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) -#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ - -/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ - uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ - uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CRCSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ -#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ - -#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ -#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) -#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ -#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) -#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ -#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) -#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ - -/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ - uint8_t :7; /*!< bit: 1.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_DBGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ -#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ - -#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ -#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) -#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ - -/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ - uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ - uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ - uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ - uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ - uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ - uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ - uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ - uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ - uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ - uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ - uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ - uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ - uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ - uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ - uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ - uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ - uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ - uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ - uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ - uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ - uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ - uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ - uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ - uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ - uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ - uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ - uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ - uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ - uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ - uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ - uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_SWTRIGCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ -#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ - -#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ -#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) -#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) -#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ - -/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ - uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ - uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ - uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ - uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ - uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ - uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ - uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ - uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ - uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ - uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ - uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PRICTRL0_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ -#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ - -#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) -#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) -#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ -#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) -#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) -#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) -#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) -#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) -#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ -#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) -#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) -#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) -#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) -#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) -#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ -#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) -#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) -#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) -#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ -#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) -#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) -#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ -#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) -#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ -#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ -#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ -#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ -#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) -#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ -#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) -#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ - -/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t TERR:1; /*!< bit: 8 Transfer Error */ - uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ - uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ - uint16_t :1; /*!< bit: 11 Reserved */ - uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ - uint16_t FERR:1; /*!< bit: 13 Fetch Error */ - uint16_t BUSY:1; /*!< bit: 14 Busy */ - uint16_t PEND:1; /*!< bit: 15 Pending */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_INTPEND_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ -#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ - -#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ -#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) -#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) -#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ -#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) -#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ -#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) -#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ -#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) -#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ -#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) -#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ -#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) -#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ -#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) -#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ -#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) -#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ - -/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ - uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ - uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ - uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ - uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ - uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ - uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ - uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ - uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ - uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ - uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ - uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ - uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ - uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ - uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ - uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ - uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ - uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ - uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ - uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ - uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ - uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ - uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ - uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ - uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ - uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ - uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ - uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ - uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ - uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ - uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ - uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_INTSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ -#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ - -#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) -#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) -#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) -#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) -#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) -#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) -#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) -#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) -#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) -#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) -#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) -#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) -#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) -#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) -#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) -#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) -#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) -#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) -#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) -#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) -#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) -#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) -#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) -#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) -#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) -#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) -#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) -#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) -#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) -#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) -#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) -#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) -#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ -#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) -#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) -#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ - -/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ - uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ - uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ - uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ - uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ - uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ - uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ - uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ - uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ - uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ - uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ - uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ - uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ - uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ - uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ - uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ - uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ - uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ - uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ - uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ - uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ - uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ - uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ - uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ - uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ - uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ - uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ - uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ - uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ - uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ - uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ - uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BUSYCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ -#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ - -#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ -#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) -#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ -#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) -#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ -#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) -#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ -#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) -#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ -#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) -#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ -#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) -#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ -#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) -#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ -#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) -#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ -#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) -#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ -#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) -#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ -#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) -#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ -#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) -#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ -#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) -#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ -#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) -#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ -#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) -#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ -#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) -#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ -#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) -#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ -#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) -#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ -#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) -#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ -#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) -#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ -#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) -#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ -#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) -#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ -#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) -#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ -#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) -#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ -#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) -#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ -#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) -#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ -#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) -#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ -#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) -#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ -#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) -#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ -#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) -#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ -#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) -#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ -#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) -#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ -#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) -#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) -#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ - -/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ - uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ - uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ - uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ - uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ - uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ - uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ - uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ - uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ - uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ - uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ - uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ - uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ - uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ - uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ - uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ - uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ - uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ - uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ - uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ - uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ - uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ - uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ - uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ - uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ - uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ - uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ - uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ - uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ - uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ - uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ - uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_PENDCH_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ -#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ - -#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ -#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) -#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ -#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) -#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ -#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) -#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ -#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) -#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ -#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) -#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ -#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) -#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ -#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) -#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ -#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) -#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ -#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) -#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ -#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) -#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ -#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) -#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ -#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) -#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ -#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) -#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ -#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) -#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ -#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) -#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ -#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) -#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ -#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) -#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ -#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) -#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ -#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) -#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ -#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) -#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ -#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) -#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ -#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) -#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ -#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) -#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ -#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) -#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ -#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) -#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ -#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) -#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ -#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) -#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ -#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) -#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ -#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) -#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ -#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) -#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ -#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) -#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ -#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) -#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ -#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) -#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) -#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ - -/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ - uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ - uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ - uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ - uint32_t :4; /*!< bit: 4.. 7 Reserved */ - uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ - uint32_t :2; /*!< bit: 13..14 Reserved */ - uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ - uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ - } bit; /*!< Structure used for bit access */ - struct { - uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ - uint32_t :28; /*!< bit: 4..31 Reserved */ - } vec; /*!< Structure used for vec access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_ACTIVE_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ -#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ - -#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) -#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) -#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) -#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) -#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ -#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) -#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) -#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ -#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) -#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) -#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ -#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) -#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ -#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) -#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) -#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ - -/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_BASEADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ -#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ - -#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ -#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) -#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) -#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ - -/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_WRBADDR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ -#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ - -#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ -#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) -#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) -#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ - -/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ - uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ - uint32_t :4; /*!< bit: 2.. 5 Reserved */ - uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ - uint32_t :1; /*!< bit: 7 Reserved */ - uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ - uint32_t :5; /*!< bit: 15..19 Reserved */ - uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ - uint32_t :2; /*!< bit: 22..23 Reserved */ - uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ - uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ - uint32_t :2; /*!< bit: 30..31 Reserved */ - } bit; /*!< Structure used for bit access */ - uint32_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLA_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ -#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ - -#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ -#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) -#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ -#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) -#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ -#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) -#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ -#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) -#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ -#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) -#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ -#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) -#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ -#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ -#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) -#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ -#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) -#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ -#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ -#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) -#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ -#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) -#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ -#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ -#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) -#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ - -/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHCTRLB_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ -#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ - -#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ -#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) -#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ -#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ -#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ -#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) -#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ - -/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ - uint8_t :6; /*!< bit: 2.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHPRILVL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ -#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ - -#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ -#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) -#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ -#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ -#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ -#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ -#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ -#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ -#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ -#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) -#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ - -/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ - uint8_t :1; /*!< bit: 3 Reserved */ - uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ - uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ - uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHEVCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ -#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ - -#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ -#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) -#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ -#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ -#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ -#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ -#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ -#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ -#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ -#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) -#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ -#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ -#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) -#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ -#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) -#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ -#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) -#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ - -/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENCLR_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ -#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ - -#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) -#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) -#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) -#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ - -/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ - uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ - uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ - uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTENSET_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ -#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ - -#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ -#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) -#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ -#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) -#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ -#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) -#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ - -/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { // __I to avoid read-modify-write on write-to-clear register - struct { - __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ - __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ - __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ - __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHINTFLAG_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ -#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ - -#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ -#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) -#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ -#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) -#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ -#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) -#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ - -/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint8_t PEND:1; /*!< bit: 0 Channel Pending */ - uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ - uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ - uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ - uint8_t :4; /*!< bit: 4.. 7 Reserved */ - } bit; /*!< Structure used for bit access */ - uint8_t reg; /*!< Type used for register access */ -} DMAC_CHSTATUS_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ -#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ - -#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ -#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) -#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ -#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) -#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ -#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) -#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ -#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) -#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ - -/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -typedef union { - struct { - uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ - uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ - uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ - uint16_t :3; /*!< bit: 5.. 7 Reserved */ - uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ - uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ - uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ - uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ - uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ - } bit; /*!< Structure used for bit access */ - uint16_t reg; /*!< Type used for register access */ -} DMAC_BTCTRL_Type; -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - -#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ -#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ - -#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ -#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) -#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ -#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) -#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ -#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ -#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ -#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) -#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ -#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) -#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ -#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ -#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ -#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) -#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ -#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) -#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ -#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) -#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ -#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) -#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ -#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) -#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ -#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ -#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ -#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) -#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ -#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) -#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) -#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits -#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM -#define USB_EPT_NUM 8 // Number of USB end points -#define USB_GCLK_ID 10 // Index of Generic Clock -#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value -#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value -#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented -#define USB_PIPE_NUM 8 // Number of USB pipes -#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system -#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) -#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode -#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested -#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode - -#endif /* _SAMD51_USB_INSTANCE_ */ +/** + * \file + * + * \brief Instance description for USB + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_USB_INSTANCE_ +#define _SAMD51_USB_INSTANCE_ + +/* ========== Register definition for USB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_USB_CTRLA (0x41000000) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (0x41000002) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (0x41000003) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (0x4100000D) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (0x41000024) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (0x41000028) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (0x41000008) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (0x4100000A) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (0x4100000C) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (0x41000010) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (0x41000014) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (0x41000018) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (0x4100001C) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (0x41000020) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (0x41000100) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (0x41000104) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (0x41000105) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (0x41000106) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (0x41000107) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (0x41000108) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (0x41000109) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (0x41000120) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (0x41000124) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (0x41000125) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (0x41000126) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (0x41000127) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (0x41000128) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (0x41000129) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (0x41000140) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (0x41000144) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (0x41000145) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (0x41000146) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (0x41000147) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (0x41000148) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (0x41000149) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (0x41000160) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (0x41000164) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (0x41000165) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (0x41000166) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (0x41000167) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (0x41000168) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (0x41000169) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (0x41000180) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (0x41000184) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (0x41000185) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (0x41000186) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (0x41000187) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (0x41000188) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (0x41000189) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (0x410001A0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (0x410001A4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (0x410001A5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (0x410001A6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (0x410001A7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (0x410001A8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (0x410001A9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (0x410001C0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (0x410001C4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (0x410001C5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (0x410001C6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (0x410001C7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (0x410001C8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (0x410001C9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (0x410001E0) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (0x410001E4) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (0x410001E5) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (0x410001E6) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (0x410001E7) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (0x410001E8) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (0x410001E9) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (0x41000008) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (0x4100000A) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (0x4100000C) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (0x41000010) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (0x41000012) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (0x41000014) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (0x41000018) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (0x4100001C) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (0x41000020) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (0x41000100) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (0x41000103) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (0x41000104) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (0x41000105) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (0x41000106) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (0x41000107) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (0x41000108) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (0x41000109) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (0x41000120) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (0x41000123) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (0x41000124) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (0x41000125) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (0x41000126) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (0x41000127) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (0x41000128) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (0x41000129) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (0x41000140) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (0x41000143) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (0x41000144) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (0x41000145) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (0x41000146) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (0x41000147) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (0x41000148) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (0x41000149) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (0x41000160) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (0x41000163) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (0x41000164) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (0x41000165) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (0x41000166) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (0x41000167) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (0x41000168) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (0x41000169) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (0x41000180) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (0x41000183) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (0x41000184) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (0x41000185) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (0x41000186) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (0x41000187) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (0x41000188) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (0x41000189) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (0x410001A0) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (0x410001A3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (0x410001A4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (0x410001A5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (0x410001A6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (0x410001A7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (0x410001A8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (0x410001A9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (0x410001C0) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (0x410001C3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (0x410001C4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (0x410001C5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (0x410001C6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (0x410001C7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (0x410001C8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (0x410001C9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (0x410001E0) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (0x410001E3) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (0x410001E4) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (0x410001E5) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (0x410001E6) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (0x410001E7) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (0x410001E8) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (0x410001E9) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#else +#define REG_USB_CTRLA (*(RwReg8 *)0x41000000UL) /**< \brief (USB) Control A */ +#define REG_USB_SYNCBUSY (*(RoReg8 *)0x41000002UL) /**< \brief (USB) Synchronization Busy */ +#define REG_USB_QOSCTRL (*(RwReg8 *)0x41000003UL) /**< \brief (USB) USB Quality Of Service */ +#define REG_USB_FSMSTATUS (*(RoReg8 *)0x4100000DUL) /**< \brief (USB) Finite State Machine Status */ +#define REG_USB_DESCADD (*(RwReg *)0x41000024UL) /**< \brief (USB) Descriptor Address */ +#define REG_USB_PADCAL (*(RwReg16*)0x41000028UL) /**< \brief (USB) USB PAD Calibration */ +#define REG_USB_DEVICE_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) DEVICE Control B */ +#define REG_USB_DEVICE_DADD (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) DEVICE Device Address */ +#define REG_USB_DEVICE_STATUS (*(RoReg8 *)0x4100000CUL) /**< \brief (USB) DEVICE Status */ +#define REG_USB_DEVICE_FNUM (*(RoReg16*)0x41000010UL) /**< \brief (USB) DEVICE Device Frame Number */ +#define REG_USB_DEVICE_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) DEVICE Device Interrupt Enable Clear */ +#define REG_USB_DEVICE_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) DEVICE Device Interrupt Enable Set */ +#define REG_USB_DEVICE_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) DEVICE Device Interrupt Flag */ +#define REG_USB_DEVICE_EPINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) DEVICE End Point Interrupt Summary */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 0 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 1 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 2 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 3 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 4 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 5 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 6 */ +#define REG_USB_DEVICE_ENDPOINT_EPCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Configuration 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Clear 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status Set 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Pipe Status 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Clear Flag 7 */ +#define REG_USB_DEVICE_ENDPOINT_EPINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) DEVICE_ENDPOINT End Point Interrupt Set Flag 7 */ +#define REG_USB_HOST_CTRLB (*(RwReg16*)0x41000008UL) /**< \brief (USB) HOST Control B */ +#define REG_USB_HOST_HSOFC (*(RwReg8 *)0x4100000AUL) /**< \brief (USB) HOST Host Start Of Frame Control */ +#define REG_USB_HOST_STATUS (*(RwReg8 *)0x4100000CUL) /**< \brief (USB) HOST Status */ +#define REG_USB_HOST_FNUM (*(RwReg16*)0x41000010UL) /**< \brief (USB) HOST Host Frame Number */ +#define REG_USB_HOST_FLENHIGH (*(RoReg8 *)0x41000012UL) /**< \brief (USB) HOST Host Frame Length */ +#define REG_USB_HOST_INTENCLR (*(RwReg16*)0x41000014UL) /**< \brief (USB) HOST Host Interrupt Enable Clear */ +#define REG_USB_HOST_INTENSET (*(RwReg16*)0x41000018UL) /**< \brief (USB) HOST Host Interrupt Enable Set */ +#define REG_USB_HOST_INTFLAG (*(RwReg16*)0x4100001CUL) /**< \brief (USB) HOST Host Interrupt Flag */ +#define REG_USB_HOST_PINTSMRY (*(RoReg16*)0x41000020UL) /**< \brief (USB) HOST Pipe Interrupt Summary */ +#define REG_USB_HOST_PIPE_PCFG0 (*(RwReg8 *)0x41000100UL) /**< \brief (USB) HOST_PIPE End Point Configuration 0 */ +#define REG_USB_HOST_PIPE_BINTERVAL0 (*(RwReg8 *)0x41000103UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 0 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR0 (*(WoReg8 *)0x41000104UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 0 */ +#define REG_USB_HOST_PIPE_PSTATUSSET0 (*(WoReg8 *)0x41000105UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 0 */ +#define REG_USB_HOST_PIPE_PSTATUS0 (*(RoReg8 *)0x41000106UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 0 */ +#define REG_USB_HOST_PIPE_PINTFLAG0 (*(RwReg8 *)0x41000107UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 0 */ +#define REG_USB_HOST_PIPE_PINTENCLR0 (*(RwReg8 *)0x41000108UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 0 */ +#define REG_USB_HOST_PIPE_PINTENSET0 (*(RwReg8 *)0x41000109UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 0 */ +#define REG_USB_HOST_PIPE_PCFG1 (*(RwReg8 *)0x41000120UL) /**< \brief (USB) HOST_PIPE End Point Configuration 1 */ +#define REG_USB_HOST_PIPE_BINTERVAL1 (*(RwReg8 *)0x41000123UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 1 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR1 (*(WoReg8 *)0x41000124UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 1 */ +#define REG_USB_HOST_PIPE_PSTATUSSET1 (*(WoReg8 *)0x41000125UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 1 */ +#define REG_USB_HOST_PIPE_PSTATUS1 (*(RoReg8 *)0x41000126UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 1 */ +#define REG_USB_HOST_PIPE_PINTFLAG1 (*(RwReg8 *)0x41000127UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 1 */ +#define REG_USB_HOST_PIPE_PINTENCLR1 (*(RwReg8 *)0x41000128UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 1 */ +#define REG_USB_HOST_PIPE_PINTENSET1 (*(RwReg8 *)0x41000129UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 1 */ +#define REG_USB_HOST_PIPE_PCFG2 (*(RwReg8 *)0x41000140UL) /**< \brief (USB) HOST_PIPE End Point Configuration 2 */ +#define REG_USB_HOST_PIPE_BINTERVAL2 (*(RwReg8 *)0x41000143UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 2 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR2 (*(WoReg8 *)0x41000144UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 2 */ +#define REG_USB_HOST_PIPE_PSTATUSSET2 (*(WoReg8 *)0x41000145UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 2 */ +#define REG_USB_HOST_PIPE_PSTATUS2 (*(RoReg8 *)0x41000146UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 2 */ +#define REG_USB_HOST_PIPE_PINTFLAG2 (*(RwReg8 *)0x41000147UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 2 */ +#define REG_USB_HOST_PIPE_PINTENCLR2 (*(RwReg8 *)0x41000148UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 2 */ +#define REG_USB_HOST_PIPE_PINTENSET2 (*(RwReg8 *)0x41000149UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 2 */ +#define REG_USB_HOST_PIPE_PCFG3 (*(RwReg8 *)0x41000160UL) /**< \brief (USB) HOST_PIPE End Point Configuration 3 */ +#define REG_USB_HOST_PIPE_BINTERVAL3 (*(RwReg8 *)0x41000163UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 3 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR3 (*(WoReg8 *)0x41000164UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 3 */ +#define REG_USB_HOST_PIPE_PSTATUSSET3 (*(WoReg8 *)0x41000165UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 3 */ +#define REG_USB_HOST_PIPE_PSTATUS3 (*(RoReg8 *)0x41000166UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 3 */ +#define REG_USB_HOST_PIPE_PINTFLAG3 (*(RwReg8 *)0x41000167UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 3 */ +#define REG_USB_HOST_PIPE_PINTENCLR3 (*(RwReg8 *)0x41000168UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 3 */ +#define REG_USB_HOST_PIPE_PINTENSET3 (*(RwReg8 *)0x41000169UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 3 */ +#define REG_USB_HOST_PIPE_PCFG4 (*(RwReg8 *)0x41000180UL) /**< \brief (USB) HOST_PIPE End Point Configuration 4 */ +#define REG_USB_HOST_PIPE_BINTERVAL4 (*(RwReg8 *)0x41000183UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 4 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR4 (*(WoReg8 *)0x41000184UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 4 */ +#define REG_USB_HOST_PIPE_PSTATUSSET4 (*(WoReg8 *)0x41000185UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 4 */ +#define REG_USB_HOST_PIPE_PSTATUS4 (*(RoReg8 *)0x41000186UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 4 */ +#define REG_USB_HOST_PIPE_PINTFLAG4 (*(RwReg8 *)0x41000187UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 4 */ +#define REG_USB_HOST_PIPE_PINTENCLR4 (*(RwReg8 *)0x41000188UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 4 */ +#define REG_USB_HOST_PIPE_PINTENSET4 (*(RwReg8 *)0x41000189UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 4 */ +#define REG_USB_HOST_PIPE_PCFG5 (*(RwReg8 *)0x410001A0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 5 */ +#define REG_USB_HOST_PIPE_BINTERVAL5 (*(RwReg8 *)0x410001A3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 5 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR5 (*(WoReg8 *)0x410001A4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 5 */ +#define REG_USB_HOST_PIPE_PSTATUSSET5 (*(WoReg8 *)0x410001A5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 5 */ +#define REG_USB_HOST_PIPE_PSTATUS5 (*(RoReg8 *)0x410001A6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 5 */ +#define REG_USB_HOST_PIPE_PINTFLAG5 (*(RwReg8 *)0x410001A7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 5 */ +#define REG_USB_HOST_PIPE_PINTENCLR5 (*(RwReg8 *)0x410001A8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 5 */ +#define REG_USB_HOST_PIPE_PINTENSET5 (*(RwReg8 *)0x410001A9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 5 */ +#define REG_USB_HOST_PIPE_PCFG6 (*(RwReg8 *)0x410001C0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 6 */ +#define REG_USB_HOST_PIPE_BINTERVAL6 (*(RwReg8 *)0x410001C3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 6 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR6 (*(WoReg8 *)0x410001C4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 6 */ +#define REG_USB_HOST_PIPE_PSTATUSSET6 (*(WoReg8 *)0x410001C5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 6 */ +#define REG_USB_HOST_PIPE_PSTATUS6 (*(RoReg8 *)0x410001C6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 6 */ +#define REG_USB_HOST_PIPE_PINTFLAG6 (*(RwReg8 *)0x410001C7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 6 */ +#define REG_USB_HOST_PIPE_PINTENCLR6 (*(RwReg8 *)0x410001C8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 6 */ +#define REG_USB_HOST_PIPE_PINTENSET6 (*(RwReg8 *)0x410001C9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 6 */ +#define REG_USB_HOST_PIPE_PCFG7 (*(RwReg8 *)0x410001E0UL) /**< \brief (USB) HOST_PIPE End Point Configuration 7 */ +#define REG_USB_HOST_PIPE_BINTERVAL7 (*(RwReg8 *)0x410001E3UL) /**< \brief (USB) HOST_PIPE Bus Access Period of Pipe 7 */ +#define REG_USB_HOST_PIPE_PSTATUSCLR7 (*(WoReg8 *)0x410001E4UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Clear 7 */ +#define REG_USB_HOST_PIPE_PSTATUSSET7 (*(WoReg8 *)0x410001E5UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status Set 7 */ +#define REG_USB_HOST_PIPE_PSTATUS7 (*(RoReg8 *)0x410001E6UL) /**< \brief (USB) HOST_PIPE End Point Pipe Status 7 */ +#define REG_USB_HOST_PIPE_PINTFLAG7 (*(RwReg8 *)0x410001E7UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag 7 */ +#define REG_USB_HOST_PIPE_PINTENCLR7 (*(RwReg8 *)0x410001E8UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Clear 7 */ +#define REG_USB_HOST_PIPE_PINTENSET7 (*(RwReg8 *)0x410001E9UL) /**< \brief (USB) HOST_PIPE Pipe Interrupt Flag Set 7 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/* ========== Instance parameters for USB peripheral ========== */ +#define USB_AHB_2_USB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) +#define USB_AHB_2_USB_RD_DATA_BITS 8 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode +#define USB_AHB_2_USB_WR_DATA_BITS 32 // 8, 16 or 32 : here, AHB transfer is made in word mode +#define USB_AHB_2_USB_WR_THRESHOLD 2 // as soon as there are N bytes-free inside the fifo, ahb read transfer is requested +#define USB_DATA_BUS_16_8 0 // UTMI/SIE data bus size : 0 -> 8 bits, 1 -> 16 bits +#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 10 // Index of Generic Clock +#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value +#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value +#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented +#define USB_PIPE_NUM 8 // Number of USB pipes +#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system +#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) +#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode +#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested +#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode + +#endif /* _SAMD51_USB_INSTANCE_ */ diff --git a/lib/samd51/samd51a/include/instance/wdt.h b/lib/samd51/samd51a/include/instance/wdt.h index f5109be..67fd5fc 100644 --- a/lib/samd51/samd51a/include/instance/wdt.h +++ b/lib/samd51/samd51a/include/instance/wdt.h @@ -1,55 +1,55 @@ -/** - * \file - * - * \brief Instance description for WDT - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_WDT_INSTANCE_ -#define _SAMD51_WDT_INSTANCE_ - -/* ========== Register definition for WDT peripheral ========== */ -#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ -#else -#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ -#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ -#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ -#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ -#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ -#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ -#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ -#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ - - -#endif /* _SAMD51_WDT_INSTANCE_ */ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_WDT_INSTANCE_ +#define _SAMD51_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAMD51_WDT_INSTANCE_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51g18a.h b/lib/samd51/samd51a/include/pio/samd51g18a.h index 92a6c26..ca599ec 100644 --- a/lib/samd51/samd51a/include/pio/samd51g18a.h +++ b/lib/samd51/samd51a/include/pio/samd51g18a.h @@ -1,1359 +1,1359 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51G18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G18A_PIO_ -#define _SAMD51G18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51G18A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G18A_PIO_ +#define _SAMD51G18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51G18A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51g19a.h b/lib/samd51/samd51a/include/pio/samd51g19a.h index 6475e66..e0a8fd2 100644 --- a/lib/samd51/samd51a/include/pio/samd51g19a.h +++ b/lib/samd51/samd51a/include/pio/samd51g19a.h @@ -1,1359 +1,1359 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51G19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G19A_PIO_ -#define _SAMD51G19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51G19A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51G19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G19A_PIO_ +#define _SAMD51G19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51G19A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51j18a.h b/lib/samd51/samd51a/include/pio/samd51j18a.h index 68a982e..23555f6 100644 --- a/lib/samd51/samd51a/include/pio/samd51j18a.h +++ b/lib/samd51/samd51a/include/pio/samd51j18a.h @@ -1,1858 +1,1858 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J18A_PIO_ -#define _SAMD51J18A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J18A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J18A_PIO_ +#define _SAMD51J18A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51J18A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51j19a.h b/lib/samd51/samd51a/include/pio/samd51j19a.h index 3de01a5..a34cd6d 100644 --- a/lib/samd51/samd51a/include/pio/samd51j19a.h +++ b/lib/samd51/samd51a/include/pio/samd51j19a.h @@ -1,1858 +1,1858 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J19A_PIO_ -#define _SAMD51J19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J19A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51J19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J19A_PIO_ +#define _SAMD51J19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51J19A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51j20a.h b/lib/samd51/samd51a/include/pio/samd51j20a.h index abbeeeb..0f2b631 100644 --- a/lib/samd51/samd51a/include/pio/samd51j20a.h +++ b/lib/samd51/samd51a/include/pio/samd51j20a.h @@ -1,1858 +1,1858 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51J20A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J20A_PIO_ -#define _SAMD51J20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) - -#endif /* _SAMD51J20A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51J20A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J20A_PIO_ +#define _SAMD51J20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) + +#endif /* _SAMD51J20A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51n19a.h b/lib/samd51/samd51a/include/pio/samd51n19a.h index e48e112..a50d0e2 100644 --- a/lib/samd51/samd51a/include/pio/samd51n19a.h +++ b/lib/samd51/samd51a/include/pio/samd51n19a.h @@ -1,2565 +1,2565 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51N19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N19A_PIO_ -#define _SAMD51N19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51N19A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51N19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N19A_PIO_ +#define _SAMD51N19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51N19A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51n20a.h b/lib/samd51/samd51a/include/pio/samd51n20a.h index 142eb49..6c3353a 100644 --- a/lib/samd51/samd51a/include/pio/samd51n20a.h +++ b/lib/samd51/samd51a/include/pio/samd51n20a.h @@ -1,2565 +1,2565 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51N20A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N20A_PIO_ -#define _SAMD51N20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51N20A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51N20A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N20A_PIO_ +#define _SAMD51N20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51N20A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51p19a.h b/lib/samd51/samd51a/include/pio/samd51p19a.h index c2148cb..004b1ba 100644 --- a/lib/samd51/samd51a/include/pio/samd51p19a.h +++ b/lib/samd51/samd51a/include/pio/samd51p19a.h @@ -1,2879 +1,2879 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51P19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P19A_PIO_ -#define _SAMD51P19A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ -#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ -#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ -#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ -#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ -#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ -#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ -#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ -#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ -#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ -#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ -#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ -#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ -#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ -#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ -#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ -#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ -#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ -#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ -#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ -#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ -#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ -#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ -#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ -#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ -#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ -#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ -#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ -#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ -#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ -#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ -#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ -#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ -#define MUX_PD00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ -#define MUX_PD01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ -#define MUX_PD08A_EIC_EXTINT3 _L_(0) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ -#define MUX_PC04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ -#define MUX_PD09A_EIC_EXTINT4 _L_(0) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ -#define MUX_PD10A_EIC_EXTINT5 _L_(0) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ -#define MUX_PC22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ -#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ -#define MUX_PD11A_EIC_EXTINT6 _L_(0) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ -#define MUX_PC23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ -#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ -#define MUX_PD12A_EIC_EXTINT7 _L_(0) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ -#define MUX_PD20A_EIC_EXTINT10 _L_(0) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ -#define MUX_PD21A_EIC_EXTINT11 _L_(0) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ -#define MUX_PB26A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ -#define MUX_PB27A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ -#define MUX_PB28A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ -#define MUX_PC30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ -#define MUX_PB29A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ -#define MUX_PC31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ -#define MUX_PC22C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ -#define MUX_PC23C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ -#define MUX_PD20C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ -#define MUX_PD21C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ -#define MUX_PB26C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ -#define MUX_PB27C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ -#define MUX_PB28C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ -#define MUX_PB29C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ -#define MUX_PC23D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ -#define MUX_PC22D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ -#define MUX_PD20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ -#define MUX_PD21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ -#define MUX_PC04F_TCC0_WO0 _L_(5) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ -#define MUX_PD08F_TCC0_WO1 _L_(5) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ -#define MUX_PD09F_TCC0_WO2 _L_(5) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ -#define MUX_PD10F_TCC0_WO3 _L_(5) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ -#define MUX_PD11F_TCC0_WO4 _L_(5) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ -#define MUX_PD12F_TCC0_WO5 _L_(5) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ -#define MUX_PC22F_TCC0_WO6 _L_(5) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ -#define MUX_PC23F_TCC0_WO7 _L_(5) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ -#define MUX_PD20F_TCC1_WO0 _L_(5) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ -#define MUX_PD21F_TCC1_WO1 _L_(5) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ -#define MUX_PB26F_TCC1_WO2 _L_(5) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ -#define MUX_PB27F_TCC1_WO3 _L_(5) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ -#define MUX_PB28F_TCC1_WO4 _L_(5) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ -#define MUX_PB29F_TCC1_WO5 _L_(5) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ -#define MUX_PB27D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ -#define MUX_PB26D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ -#define MUX_PB28D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ -#define MUX_PB29D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ -#define MUX_PD09D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ -#define MUX_PC04C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ -#define MUX_PD08D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ -#define MUX_PD10D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ -#define MUX_PD11D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ -#define MUX_PD08C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ -#define MUX_PD09C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ -#define MUX_PD10C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ -#define MUX_PD11C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ -#define MUX_PC30B_ADC1_AIN12 _L_(1) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) -#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ -#define MUX_PC31B_ADC1_AIN13 _L_(1) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) -#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ -#define MUX_PD00B_ADC1_AIN14 _L_(1) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) -#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ -#define MUX_PD01B_ADC1_AIN15 _L_(1) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ -#define MUX_PB29J_I2S_MCK1 _L_(9) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ -#define MUX_PB28J_I2S_SCK1 _L_(9) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ -#define MUX_PD20I_SDHC1_SDCD _L_(8) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) -#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ -#define MUX_PD21I_SDHC1_SDWP _L_(8) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51P19A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51P19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P19A_PIO_ +#define _SAMD51P19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51P19A_PIO_ */ diff --git a/lib/samd51/samd51a/include/pio/samd51p20a.h b/lib/samd51/samd51a/include/pio/samd51p20a.h index aa321dd..369b316 100644 --- a/lib/samd51/samd51a/include/pio/samd51p20a.h +++ b/lib/samd51/samd51a/include/pio/samd51p20a.h @@ -1,2879 +1,2879 @@ -/** - * \file - * - * \brief Peripheral I/O description for SAMD51P20A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P20A_PIO_ -#define _SAMD51P20A_PIO_ - -#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ -#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ -#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ -#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ -#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ -#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ -#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ -#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ -#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ -#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ -#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ -#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ -#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ -#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ -#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ -#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ -#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ -#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ -#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ -#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ -#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ -#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ -#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ -#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ -#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ -#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ -#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ -#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ -#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ -#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ -#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ -#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ -#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ -#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ -#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ -#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ -#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ -#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ -#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ -#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ -#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ -#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ -#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ -#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ -#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ -#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ -#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ -#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ -#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ -#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ -#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ -#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ -#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ -#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ -#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ -#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ -#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ -#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ -#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ -#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ -#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ -#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ -#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ -#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ -#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ -#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ -#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ -#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ -#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ -#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ -#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ -#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ -#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ -#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ -#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ -#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ -#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ -#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ -#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ -#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ -#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ -#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ -#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ -#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ -#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ -#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ -#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ -#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ -#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ -#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ -#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ -#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ -#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ -#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ -#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ -#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ -#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ -#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ -#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ -#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ -#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ -#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ -#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ -#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ -#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ -#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ -#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ -#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ -#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ -#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ -#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ -#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ -#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ -#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ -#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ -#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ -#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ -#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ -#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ -#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ -#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ -#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ -#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ -#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ -#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ -#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ -#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ -#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ -#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ -#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ -#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ -#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ -#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ -#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ -#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ -#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ -#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ -#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ -#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ -#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ -#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ -#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ -#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ -#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ -#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ -#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ -#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ -#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ -#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ -#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ -#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ -#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ -#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ -#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ -#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ -#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ -#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ -#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ -#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ -#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ -#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ -#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ -#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ -#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ -#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ -#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ -#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ -#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ -#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ -#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ -#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ -#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ -#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ -#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ -#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ -#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ -#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ -#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ -#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ -#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ -#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ -#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ -#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ -#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ -#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ -#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ -#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ -#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ -#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ -#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ -#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ -#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ -#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ -#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ -#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ -#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ -#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ -#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ -/* ========== PORT definition for CM4 peripheral ========== */ -#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ -#define MUX_PA30H_CM4_SWCLK _L_(7) -#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) -#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) -#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ -#define MUX_PC27M_CM4_SWO _L_(12) -#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) -#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) -#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ -#define MUX_PB30H_CM4_SWO _L_(7) -#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) -#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) -#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ -#define MUX_PC27H_CM4_TRACECLK _L_(7) -#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) -#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) -#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ -#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) -#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) -#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) -#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ -#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) -#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) -#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) -#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ -#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) -#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) -#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) -#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ -#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) -#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) -#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) -/* ========== PORT definition for ANAREF peripheral ========== */ -#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ -#define MUX_PA03B_ANAREF_VREF0 _L_(1) -#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) -#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) -#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ -#define MUX_PA04B_ANAREF_VREF1 _L_(1) -#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) -#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) -#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ -#define MUX_PA06B_ANAREF_VREF2 _L_(1) -#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) -#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) -/* ========== PORT definition for GCLK peripheral ========== */ -#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ -#define MUX_PA30M_GCLK_IO0 _L_(12) -#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) -#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) -#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ -#define MUX_PB14M_GCLK_IO0 _L_(12) -#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) -#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ -#define MUX_PA14M_GCLK_IO0 _L_(12) -#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) -#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) -#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ -#define MUX_PB22M_GCLK_IO0 _L_(12) -#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) -#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) -#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ -#define MUX_PB15M_GCLK_IO1 _L_(12) -#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) -#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ -#define MUX_PA15M_GCLK_IO1 _L_(12) -#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) -#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) -#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ -#define MUX_PB23M_GCLK_IO1 _L_(12) -#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) -#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) -#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ -#define MUX_PA27M_GCLK_IO1 _L_(12) -#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) -#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) -#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ -#define MUX_PA16M_GCLK_IO2 _L_(12) -#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) -#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ -#define MUX_PB16M_GCLK_IO2 _L_(12) -#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) -#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) -#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ -#define MUX_PA17M_GCLK_IO3 _L_(12) -#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) -#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ -#define MUX_PB17M_GCLK_IO3 _L_(12) -#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) -#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) -#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ -#define MUX_PA10M_GCLK_IO4 _L_(12) -#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) -#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ -#define MUX_PB10M_GCLK_IO4 _L_(12) -#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) -#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) -#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ -#define MUX_PB18M_GCLK_IO4 _L_(12) -#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) -#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) -#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ -#define MUX_PA11M_GCLK_IO5 _L_(12) -#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) -#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ -#define MUX_PB11M_GCLK_IO5 _L_(12) -#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) -#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) -#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ -#define MUX_PB19M_GCLK_IO5 _L_(12) -#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) -#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) -#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ -#define MUX_PB12M_GCLK_IO6 _L_(12) -#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) -#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) -#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ -#define MUX_PB20M_GCLK_IO6 _L_(12) -#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) -#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) -#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ -#define MUX_PB13M_GCLK_IO7 _L_(12) -#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) -#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) -#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ -#define MUX_PB21M_GCLK_IO7 _L_(12) -#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) -#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) -/* ========== PORT definition for EIC peripheral ========== */ -#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ -#define MUX_PA00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) -#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ -#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ -#define MUX_PA16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) -#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ -#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ -#define MUX_PB00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) -#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ -#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ -#define MUX_PB16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) -#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ -#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ -#define MUX_PC00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) -#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ -#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ -#define MUX_PC16A_EIC_EXTINT0 _L_(0) -#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) -#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) -#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ -#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ -#define MUX_PD00A_EIC_EXTINT0 _L_(0) -#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) -#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) -#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ -#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ -#define MUX_PA01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) -#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ -#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ -#define MUX_PA17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) -#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ -#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ -#define MUX_PB01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) -#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ -#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ -#define MUX_PB17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) -#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ -#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ -#define MUX_PC01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) -#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ -#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ -#define MUX_PC17A_EIC_EXTINT1 _L_(0) -#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) -#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) -#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ -#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ -#define MUX_PD01A_EIC_EXTINT1 _L_(0) -#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) -#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) -#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ -#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ -#define MUX_PA02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) -#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ -#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ -#define MUX_PA18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) -#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ -#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ -#define MUX_PB02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) -#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ -#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ -#define MUX_PB18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) -#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ -#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ -#define MUX_PC02A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) -#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) -#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ -#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ -#define MUX_PC18A_EIC_EXTINT2 _L_(0) -#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) -#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) -#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ -#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ -#define MUX_PA03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) -#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ -#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ -#define MUX_PA19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) -#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ -#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ -#define MUX_PB03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) -#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ -#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ -#define MUX_PB19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) -#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ -#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ -#define MUX_PC03A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) -#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) -#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ -#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ -#define MUX_PC19A_EIC_EXTINT3 _L_(0) -#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) -#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) -#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ -#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ -#define MUX_PD08A_EIC_EXTINT3 _L_(0) -#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) -#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) -#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ -#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ -#define MUX_PA04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) -#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ -#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ -#define MUX_PA20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) -#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ -#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ -#define MUX_PB04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) -#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ -#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ -#define MUX_PB20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) -#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ -#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ -#define MUX_PC04A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) -#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) -#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ -#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ -#define MUX_PC20A_EIC_EXTINT4 _L_(0) -#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) -#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) -#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ -#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ -#define MUX_PD09A_EIC_EXTINT4 _L_(0) -#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) -#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) -#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ -#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ -#define MUX_PA05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) -#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ -#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ -#define MUX_PA21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) -#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ -#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ -#define MUX_PB05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) -#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ -#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ -#define MUX_PB21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) -#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ -#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ -#define MUX_PC05A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) -#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) -#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ -#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ -#define MUX_PC21A_EIC_EXTINT5 _L_(0) -#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) -#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) -#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ -#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ -#define MUX_PD10A_EIC_EXTINT5 _L_(0) -#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) -#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) -#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ -#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ -#define MUX_PA06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) -#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ -#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ -#define MUX_PA22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) -#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ -#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ -#define MUX_PB06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) -#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ -#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ -#define MUX_PB22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) -#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ -#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ -#define MUX_PC06A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) -#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) -#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ -#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ -#define MUX_PC22A_EIC_EXTINT6 _L_(0) -#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) -#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) -#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ -#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ -#define MUX_PD11A_EIC_EXTINT6 _L_(0) -#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) -#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) -#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ -#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ -#define MUX_PA07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) -#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ -#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ -#define MUX_PA23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) -#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ -#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ -#define MUX_PB07A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) -#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) -#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ -#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ -#define MUX_PB23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) -#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ -#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ -#define MUX_PC23A_EIC_EXTINT7 _L_(0) -#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) -#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) -#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ -#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ -#define MUX_PD12A_EIC_EXTINT7 _L_(0) -#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) -#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) -#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ -#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ -#define MUX_PA24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) -#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ -#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ -#define MUX_PB08A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) -#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) -#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ -#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ -#define MUX_PB24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) -#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ -#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ -#define MUX_PC24A_EIC_EXTINT8 _L_(0) -#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) -#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) -#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ -#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ -#define MUX_PA09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) -#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ -#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ -#define MUX_PA25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) -#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ -#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ -#define MUX_PB09A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) -#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) -#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ -#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ -#define MUX_PB25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) -#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ -#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ -#define MUX_PC07A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) -#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) -#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ -#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ -#define MUX_PC25A_EIC_EXTINT9 _L_(0) -#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) -#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) -#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ -#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ -#define MUX_PA10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) -#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ -#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ -#define MUX_PB10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) -#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ -#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ -#define MUX_PC10A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) -#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) -#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ -#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ -#define MUX_PC26A_EIC_EXTINT10 _L_(0) -#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) -#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) -#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ -#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ -#define MUX_PD20A_EIC_EXTINT10 _L_(0) -#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) -#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) -#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ -#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ -#define MUX_PA11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) -#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ -#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ -#define MUX_PA27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) -#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ -#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ -#define MUX_PB11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) -#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ -#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ -#define MUX_PC11A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) -#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) -#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ -#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ -#define MUX_PC27A_EIC_EXTINT11 _L_(0) -#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) -#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) -#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ -#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ -#define MUX_PD21A_EIC_EXTINT11 _L_(0) -#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) -#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) -#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ -#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ -#define MUX_PA12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) -#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ -#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ -#define MUX_PB12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) -#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ -#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ -#define MUX_PB26A_EIC_EXTINT12 _L_(0) -#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) -#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) -#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ -#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ -#define MUX_PC12A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) -#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) -#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ -#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ -#define MUX_PC28A_EIC_EXTINT12 _L_(0) -#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) -#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) -#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ -#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ -#define MUX_PA13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) -#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ -#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ -#define MUX_PB13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) -#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ -#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ -#define MUX_PB27A_EIC_EXTINT13 _L_(0) -#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) -#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) -#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ -#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ -#define MUX_PC13A_EIC_EXTINT13 _L_(0) -#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) -#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) -#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ -#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ -#define MUX_PA30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) -#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ -#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ -#define MUX_PB14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) -#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ -#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ -#define MUX_PB28A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) -#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) -#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ -#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ -#define MUX_PB30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) -#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ -#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ -#define MUX_PC14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) -#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ -#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ -#define MUX_PC30A_EIC_EXTINT14 _L_(0) -#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) -#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) -#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ -#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ -#define MUX_PA14A_EIC_EXTINT14 _L_(0) -#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) -#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) -#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ -#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ -#define MUX_PA15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) -#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ -#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ -#define MUX_PA31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) -#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ -#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ -#define MUX_PB15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) -#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ -#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ -#define MUX_PB29A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) -#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) -#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ -#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ -#define MUX_PB31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) -#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ -#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ -#define MUX_PC15A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) -#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) -#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ -#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ -#define MUX_PC31A_EIC_EXTINT15 _L_(0) -#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) -#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) -#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ -#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ -#define MUX_PA08A_EIC_NMI _L_(0) -#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) -#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) -/* ========== PORT definition for SERCOM0 peripheral ========== */ -#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ -#define MUX_PA04D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) -#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) -#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ -#define MUX_PC17D_SERCOM0_PAD0 _L_(3) -#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) -#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) -#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ -#define MUX_PA08C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) -#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) -#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ -#define MUX_PB24C_SERCOM0_PAD0 _L_(2) -#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) -#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) -#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ -#define MUX_PA05D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) -#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) -#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ -#define MUX_PC16D_SERCOM0_PAD1 _L_(3) -#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) -#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) -#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ -#define MUX_PA09C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) -#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) -#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ -#define MUX_PB25C_SERCOM0_PAD1 _L_(2) -#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) -#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) -#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ -#define MUX_PA06D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) -#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) -#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ -#define MUX_PC18D_SERCOM0_PAD2 _L_(3) -#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) -#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) -#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ -#define MUX_PA10C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) -#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) -#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ -#define MUX_PC24C_SERCOM0_PAD2 _L_(2) -#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) -#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) -#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ -#define MUX_PA07D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) -#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) -#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ -#define MUX_PC19D_SERCOM0_PAD3 _L_(3) -#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) -#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) -#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ -#define MUX_PA11C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) -#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) -#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ -#define MUX_PC25C_SERCOM0_PAD3 _L_(2) -#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) -#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for SERCOM1 peripheral ========== */ -#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ -#define MUX_PA00D_SERCOM1_PAD0 _L_(3) -#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) -#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) -#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ -#define MUX_PA16C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) -#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) -#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ -#define MUX_PC22C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) -#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) -#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ -#define MUX_PC27C_SERCOM1_PAD0 _L_(2) -#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) -#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) -#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ -#define MUX_PA01D_SERCOM1_PAD1 _L_(3) -#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) -#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) -#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ -#define MUX_PA17C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) -#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) -#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ -#define MUX_PC23C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) -#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) -#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ -#define MUX_PC28C_SERCOM1_PAD1 _L_(2) -#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) -#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) -#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ -#define MUX_PA30D_SERCOM1_PAD2 _L_(3) -#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) -#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) -#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ -#define MUX_PA18C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) -#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) -#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ -#define MUX_PB22C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) -#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) -#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ -#define MUX_PD20C_SERCOM1_PAD2 _L_(2) -#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) -#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) -#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ -#define MUX_PA31D_SERCOM1_PAD3 _L_(3) -#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) -#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) -#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ -#define MUX_PA19C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) -#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) -#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ -#define MUX_PB23C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) -#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) -#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ -#define MUX_PD21C_SERCOM1_PAD3 _L_(2) -#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) -#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) -/* ========== PORT definition for TC0 peripheral ========== */ -#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ -#define MUX_PA04E_TC0_WO0 _L_(4) -#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) -#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) -#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ -#define MUX_PA08E_TC0_WO0 _L_(4) -#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) -#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) -#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ -#define MUX_PB30E_TC0_WO0 _L_(4) -#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) -#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) -#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ -#define MUX_PA05E_TC0_WO1 _L_(4) -#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) -#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) -#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ -#define MUX_PA09E_TC0_WO1 _L_(4) -#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) -#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) -#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ -#define MUX_PB31E_TC0_WO1 _L_(4) -#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) -#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC1 peripheral ========== */ -#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ -#define MUX_PA06E_TC1_WO0 _L_(4) -#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) -#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) -#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ -#define MUX_PA10E_TC1_WO0 _L_(4) -#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) -#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) -#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ -#define MUX_PA07E_TC1_WO1 _L_(4) -#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) -#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) -#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ -#define MUX_PA11E_TC1_WO1 _L_(4) -#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) -#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) -/* ========== PORT definition for USB peripheral ========== */ -#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ -#define MUX_PA24H_USB_DM _L_(7) -#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) -#define PORT_PA24H_USB_DM (_UL_(1) << 24) -#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ -#define MUX_PA25H_USB_DP _L_(7) -#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) -#define PORT_PA25H_USB_DP (_UL_(1) << 25) -#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ -#define MUX_PA23H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) -#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) -#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ -#define MUX_PB22H_USB_SOF_1KHZ _L_(7) -#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) -#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) -/* ========== PORT definition for SERCOM2 peripheral ========== */ -#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ -#define MUX_PA09D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) -#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) -#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ -#define MUX_PB25D_SERCOM2_PAD0 _L_(3) -#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) -#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) -#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ -#define MUX_PA12C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) -#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) -#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ -#define MUX_PB26C_SERCOM2_PAD0 _L_(2) -#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) -#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) -#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ -#define MUX_PA08D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) -#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) -#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ -#define MUX_PB24D_SERCOM2_PAD1 _L_(3) -#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) -#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) -#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ -#define MUX_PA13C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) -#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) -#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ -#define MUX_PB27C_SERCOM2_PAD1 _L_(2) -#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) -#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) -#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ -#define MUX_PA10D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) -#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) -#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ -#define MUX_PC24D_SERCOM2_PAD2 _L_(3) -#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) -#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) -#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ -#define MUX_PB28C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) -#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) -#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ -#define MUX_PA14C_SERCOM2_PAD2 _L_(2) -#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) -#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) -#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ -#define MUX_PA11D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) -#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) -#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ -#define MUX_PC25D_SERCOM2_PAD3 _L_(3) -#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) -#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) -#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ -#define MUX_PB29C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) -#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) -#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ -#define MUX_PA15C_SERCOM2_PAD3 _L_(2) -#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) -#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM3 peripheral ========== */ -#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ -#define MUX_PA17D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) -#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) -#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ -#define MUX_PC23D_SERCOM3_PAD0 _L_(3) -#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) -#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) -#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ -#define MUX_PA22C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) -#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) -#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ -#define MUX_PB20C_SERCOM3_PAD0 _L_(2) -#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) -#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) -#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ -#define MUX_PA16D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) -#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) -#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ -#define MUX_PC22D_SERCOM3_PAD1 _L_(3) -#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) -#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) -#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ -#define MUX_PA23C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) -#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) -#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ -#define MUX_PB21C_SERCOM3_PAD1 _L_(2) -#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) -#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) -#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ -#define MUX_PA18D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) -#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) -#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ -#define MUX_PA20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) -#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ -#define MUX_PD20D_SERCOM3_PAD2 _L_(3) -#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) -#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) -#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ -#define MUX_PA24C_SERCOM3_PAD2 _L_(2) -#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) -#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) -#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ -#define MUX_PA19D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) -#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) -#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ -#define MUX_PA21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) -#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ -#define MUX_PD21D_SERCOM3_PAD3 _L_(3) -#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) -#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) -#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ -#define MUX_PA25C_SERCOM3_PAD3 _L_(2) -#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) -#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) -/* ========== PORT definition for TCC0 peripheral ========== */ -#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ -#define MUX_PA20G_TCC0_WO0 _L_(6) -#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) -#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) -#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ -#define MUX_PB12G_TCC0_WO0 _L_(6) -#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) -#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) -#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ -#define MUX_PA08F_TCC0_WO0 _L_(5) -#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) -#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) -#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ -#define MUX_PC04F_TCC0_WO0 _L_(5) -#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) -#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) -#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ -#define MUX_PC10F_TCC0_WO0 _L_(5) -#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) -#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) -#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ -#define MUX_PC16F_TCC0_WO0 _L_(5) -#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) -#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) -#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ -#define MUX_PA21G_TCC0_WO1 _L_(6) -#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) -#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) -#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ -#define MUX_PB13G_TCC0_WO1 _L_(6) -#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) -#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) -#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ -#define MUX_PA09F_TCC0_WO1 _L_(5) -#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) -#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) -#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ -#define MUX_PC11F_TCC0_WO1 _L_(5) -#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) -#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) -#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ -#define MUX_PC17F_TCC0_WO1 _L_(5) -#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) -#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) -#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ -#define MUX_PD08F_TCC0_WO1 _L_(5) -#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) -#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) -#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ -#define MUX_PA22G_TCC0_WO2 _L_(6) -#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) -#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) -#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ -#define MUX_PB14G_TCC0_WO2 _L_(6) -#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) -#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) -#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ -#define MUX_PA10F_TCC0_WO2 _L_(5) -#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) -#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) -#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ -#define MUX_PC12F_TCC0_WO2 _L_(5) -#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) -#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) -#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ -#define MUX_PC18F_TCC0_WO2 _L_(5) -#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) -#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) -#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ -#define MUX_PD09F_TCC0_WO2 _L_(5) -#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) -#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) -#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ -#define MUX_PA23G_TCC0_WO3 _L_(6) -#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) -#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) -#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ -#define MUX_PB15G_TCC0_WO3 _L_(6) -#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) -#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) -#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ -#define MUX_PA11F_TCC0_WO3 _L_(5) -#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) -#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) -#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ -#define MUX_PC13F_TCC0_WO3 _L_(5) -#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) -#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) -#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ -#define MUX_PC19F_TCC0_WO3 _L_(5) -#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) -#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) -#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ -#define MUX_PD10F_TCC0_WO3 _L_(5) -#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) -#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) -#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ -#define MUX_PA16G_TCC0_WO4 _L_(6) -#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) -#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ -#define MUX_PB16G_TCC0_WO4 _L_(6) -#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) -#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) -#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ -#define MUX_PB10F_TCC0_WO4 _L_(5) -#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) -#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) -#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ -#define MUX_PC14F_TCC0_WO4 _L_(5) -#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) -#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) -#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ -#define MUX_PC20F_TCC0_WO4 _L_(5) -#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) -#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) -#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ -#define MUX_PD11F_TCC0_WO4 _L_(5) -#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) -#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) -#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ -#define MUX_PA17G_TCC0_WO5 _L_(6) -#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) -#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ -#define MUX_PB17G_TCC0_WO5 _L_(6) -#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) -#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) -#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ -#define MUX_PB11F_TCC0_WO5 _L_(5) -#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) -#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) -#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ -#define MUX_PC15F_TCC0_WO5 _L_(5) -#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) -#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) -#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ -#define MUX_PC21F_TCC0_WO5 _L_(5) -#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) -#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) -#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ -#define MUX_PD12F_TCC0_WO5 _L_(5) -#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) -#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) -#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ -#define MUX_PA18G_TCC0_WO6 _L_(6) -#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) -#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) -#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ -#define MUX_PB30G_TCC0_WO6 _L_(6) -#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) -#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) -#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ -#define MUX_PA12F_TCC0_WO6 _L_(5) -#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) -#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) -#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ -#define MUX_PC22F_TCC0_WO6 _L_(5) -#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) -#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) -#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ -#define MUX_PA19G_TCC0_WO7 _L_(6) -#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) -#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) -#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ -#define MUX_PB31G_TCC0_WO7 _L_(6) -#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) -#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) -#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ -#define MUX_PA13F_TCC0_WO7 _L_(5) -#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) -#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) -#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ -#define MUX_PC23F_TCC0_WO7 _L_(5) -#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) -#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TCC1 peripheral ========== */ -#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ -#define MUX_PB10G_TCC1_WO0 _L_(6) -#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) -#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) -#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ -#define MUX_PC14G_TCC1_WO0 _L_(6) -#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) -#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) -#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ -#define MUX_PA16F_TCC1_WO0 _L_(5) -#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) -#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) -#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ -#define MUX_PB18F_TCC1_WO0 _L_(5) -#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) -#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) -#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ -#define MUX_PD20F_TCC1_WO0 _L_(5) -#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) -#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) -#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ -#define MUX_PB11G_TCC1_WO1 _L_(6) -#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) -#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) -#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ -#define MUX_PC15G_TCC1_WO1 _L_(6) -#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) -#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) -#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ -#define MUX_PA17F_TCC1_WO1 _L_(5) -#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) -#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) -#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ -#define MUX_PB19F_TCC1_WO1 _L_(5) -#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) -#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) -#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ -#define MUX_PD21F_TCC1_WO1 _L_(5) -#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) -#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) -#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ -#define MUX_PA12G_TCC1_WO2 _L_(6) -#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) -#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) -#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ -#define MUX_PA14G_TCC1_WO2 _L_(6) -#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) -#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) -#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ -#define MUX_PA18F_TCC1_WO2 _L_(5) -#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) -#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) -#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ -#define MUX_PB20F_TCC1_WO2 _L_(5) -#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) -#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) -#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ -#define MUX_PB26F_TCC1_WO2 _L_(5) -#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) -#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) -#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ -#define MUX_PA13G_TCC1_WO3 _L_(6) -#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) -#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) -#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ -#define MUX_PA15G_TCC1_WO3 _L_(6) -#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) -#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) -#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ -#define MUX_PA19F_TCC1_WO3 _L_(5) -#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) -#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) -#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ -#define MUX_PB21F_TCC1_WO3 _L_(5) -#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) -#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) -#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ -#define MUX_PB27F_TCC1_WO3 _L_(5) -#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) -#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) -#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ -#define MUX_PA08G_TCC1_WO4 _L_(6) -#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) -#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) -#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ -#define MUX_PC10G_TCC1_WO4 _L_(6) -#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) -#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) -#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ -#define MUX_PA20F_TCC1_WO4 _L_(5) -#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) -#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) -#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ -#define MUX_PB28F_TCC1_WO4 _L_(5) -#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) -#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) -#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ -#define MUX_PA09G_TCC1_WO5 _L_(6) -#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) -#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) -#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ -#define MUX_PC11G_TCC1_WO5 _L_(6) -#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) -#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) -#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ -#define MUX_PA21F_TCC1_WO5 _L_(5) -#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) -#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) -#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ -#define MUX_PB29F_TCC1_WO5 _L_(5) -#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) -#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) -#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ -#define MUX_PA10G_TCC1_WO6 _L_(6) -#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) -#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) -#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ -#define MUX_PC12G_TCC1_WO6 _L_(6) -#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) -#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) -#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ -#define MUX_PA22F_TCC1_WO6 _L_(5) -#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) -#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) -#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ -#define MUX_PA11G_TCC1_WO7 _L_(6) -#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) -#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) -#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ -#define MUX_PC13G_TCC1_WO7 _L_(6) -#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) -#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) -#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ -#define MUX_PA23F_TCC1_WO7 _L_(5) -#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) -#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) -/* ========== PORT definition for TC2 peripheral ========== */ -#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ -#define MUX_PA12E_TC2_WO0 _L_(4) -#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) -#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) -#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ -#define MUX_PA16E_TC2_WO0 _L_(4) -#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) -#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) -#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ -#define MUX_PA00E_TC2_WO0 _L_(4) -#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) -#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) -#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ -#define MUX_PA01E_TC2_WO1 _L_(4) -#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) -#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) -#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ -#define MUX_PA13E_TC2_WO1 _L_(4) -#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) -#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) -#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ -#define MUX_PA17E_TC2_WO1 _L_(4) -#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) -#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC3 peripheral ========== */ -#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ -#define MUX_PA18E_TC3_WO0 _L_(4) -#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) -#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) -#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ -#define MUX_PA14E_TC3_WO0 _L_(4) -#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) -#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) -#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ -#define MUX_PA15E_TC3_WO1 _L_(4) -#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) -#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) -#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ -#define MUX_PA19E_TC3_WO1 _L_(4) -#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) -#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) -/* ========== PORT definition for TCC2 peripheral ========== */ -#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ -#define MUX_PA14F_TCC2_WO0 _L_(5) -#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) -#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) -#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ -#define MUX_PA30F_TCC2_WO0 _L_(5) -#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) -#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) -#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ -#define MUX_PA15F_TCC2_WO1 _L_(5) -#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) -#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) -#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ -#define MUX_PA31F_TCC2_WO1 _L_(5) -#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) -#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) -#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ -#define MUX_PA24F_TCC2_WO2 _L_(5) -#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) -#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) -#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ -#define MUX_PB02F_TCC2_WO2 _L_(5) -#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) -#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) -/* ========== PORT definition for TCC3 peripheral ========== */ -#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ -#define MUX_PB12F_TCC3_WO0 _L_(5) -#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) -#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) -#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ -#define MUX_PB16F_TCC3_WO0 _L_(5) -#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) -#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) -#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ -#define MUX_PB13F_TCC3_WO1 _L_(5) -#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) -#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) -#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ -#define MUX_PB17F_TCC3_WO1 _L_(5) -#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) -#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC4 peripheral ========== */ -#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ -#define MUX_PA22E_TC4_WO0 _L_(4) -#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) -#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) -#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ -#define MUX_PB08E_TC4_WO0 _L_(4) -#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) -#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) -#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ -#define MUX_PB12E_TC4_WO0 _L_(4) -#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) -#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) -#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ -#define MUX_PA23E_TC4_WO1 _L_(4) -#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) -#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) -#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ -#define MUX_PB09E_TC4_WO1 _L_(4) -#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) -#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) -#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ -#define MUX_PB13E_TC4_WO1 _L_(4) -#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) -#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) -/* ========== PORT definition for TC5 peripheral ========== */ -#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ -#define MUX_PA24E_TC5_WO0 _L_(4) -#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) -#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) -#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ -#define MUX_PB10E_TC5_WO0 _L_(4) -#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) -#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) -#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ -#define MUX_PB14E_TC5_WO0 _L_(4) -#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) -#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) -#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ -#define MUX_PA25E_TC5_WO1 _L_(4) -#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) -#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) -#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ -#define MUX_PB11E_TC5_WO1 _L_(4) -#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) -#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) -#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ -#define MUX_PB15E_TC5_WO1 _L_(4) -#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) -#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) -/* ========== PORT definition for PDEC peripheral ========== */ -#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ -#define MUX_PB18G_PDEC_QDI0 _L_(6) -#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) -#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) -#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ -#define MUX_PB23G_PDEC_QDI0 _L_(6) -#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) -#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) -#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ -#define MUX_PC16G_PDEC_QDI0 _L_(6) -#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) -#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) -#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ -#define MUX_PA24G_PDEC_QDI0 _L_(6) -#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) -#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) -#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ -#define MUX_PB19G_PDEC_QDI1 _L_(6) -#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) -#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) -#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ -#define MUX_PB24G_PDEC_QDI1 _L_(6) -#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) -#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) -#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ -#define MUX_PC17G_PDEC_QDI1 _L_(6) -#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) -#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) -#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ -#define MUX_PA25G_PDEC_QDI1 _L_(6) -#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) -#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) -#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ -#define MUX_PB20G_PDEC_QDI2 _L_(6) -#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) -#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) -#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ -#define MUX_PB25G_PDEC_QDI2 _L_(6) -#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) -#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) -#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ -#define MUX_PC18G_PDEC_QDI2 _L_(6) -#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) -#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) -#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ -#define MUX_PB22G_PDEC_QDI2 _L_(6) -#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) -#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) -/* ========== PORT definition for AC peripheral ========== */ -#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ -#define MUX_PA04B_AC_AIN0 _L_(1) -#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) -#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) -#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ -#define MUX_PA05B_AC_AIN1 _L_(1) -#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) -#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) -#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ -#define MUX_PA06B_AC_AIN2 _L_(1) -#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) -#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) -#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ -#define MUX_PA07B_AC_AIN3 _L_(1) -#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) -#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) -#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ -#define MUX_PA12M_AC_CMP0 _L_(12) -#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) -#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) -#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ -#define MUX_PA18M_AC_CMP0 _L_(12) -#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) -#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) -#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ -#define MUX_PB24M_AC_CMP0 _L_(12) -#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) -#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) -#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ -#define MUX_PA13M_AC_CMP1 _L_(12) -#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) -#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) -#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ -#define MUX_PA19M_AC_CMP1 _L_(12) -#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) -#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) -#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ -#define MUX_PB25M_AC_CMP1 _L_(12) -#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) -#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) -/* ========== PORT definition for QSPI peripheral ========== */ -#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ -#define MUX_PB11H_QSPI_CS _L_(7) -#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) -#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) -#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ -#define MUX_PA08H_QSPI_DATA0 _L_(7) -#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) -#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) -#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ -#define MUX_PA09H_QSPI_DATA1 _L_(7) -#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) -#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) -#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ -#define MUX_PA10H_QSPI_DATA2 _L_(7) -#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) -#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) -#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ -#define MUX_PA11H_QSPI_DATA3 _L_(7) -#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) -#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) -#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ -#define MUX_PB10H_QSPI_SCK _L_(7) -#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) -#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) -/* ========== PORT definition for CCL peripheral ========== */ -#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ -#define MUX_PA04N_CCL_IN0 _L_(13) -#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) -#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) -#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ -#define MUX_PA16N_CCL_IN0 _L_(13) -#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) -#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) -#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ -#define MUX_PB22N_CCL_IN0 _L_(13) -#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) -#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) -#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ -#define MUX_PA05N_CCL_IN1 _L_(13) -#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) -#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) -#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ -#define MUX_PA17N_CCL_IN1 _L_(13) -#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) -#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) -#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ -#define MUX_PB00N_CCL_IN1 _L_(13) -#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) -#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) -#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ -#define MUX_PA06N_CCL_IN2 _L_(13) -#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) -#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) -#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ -#define MUX_PA18N_CCL_IN2 _L_(13) -#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) -#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) -#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ -#define MUX_PB01N_CCL_IN2 _L_(13) -#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) -#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) -#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ -#define MUX_PA08N_CCL_IN3 _L_(13) -#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) -#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) -#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ -#define MUX_PA30N_CCL_IN3 _L_(13) -#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) -#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) -#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ -#define MUX_PA09N_CCL_IN4 _L_(13) -#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) -#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) -#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ -#define MUX_PC27N_CCL_IN4 _L_(13) -#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) -#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) -#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ -#define MUX_PA10N_CCL_IN5 _L_(13) -#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) -#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) -#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ -#define MUX_PC28N_CCL_IN5 _L_(13) -#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) -#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) -#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ -#define MUX_PA22N_CCL_IN6 _L_(13) -#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) -#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) -#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ -#define MUX_PB06N_CCL_IN6 _L_(13) -#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) -#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) -#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ -#define MUX_PA23N_CCL_IN7 _L_(13) -#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) -#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) -#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ -#define MUX_PB07N_CCL_IN7 _L_(13) -#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) -#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) -#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ -#define MUX_PA24N_CCL_IN8 _L_(13) -#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) -#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) -#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ -#define MUX_PB08N_CCL_IN8 _L_(13) -#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) -#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) -#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ -#define MUX_PB14N_CCL_IN9 _L_(13) -#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) -#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) -#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ -#define MUX_PC20N_CCL_IN9 _L_(13) -#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) -#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) -#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ -#define MUX_PB15N_CCL_IN10 _L_(13) -#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) -#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) -#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ -#define MUX_PC21N_CCL_IN10 _L_(13) -#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) -#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) -#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ -#define MUX_PB10N_CCL_IN11 _L_(13) -#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) -#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) -#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ -#define MUX_PB16N_CCL_IN11 _L_(13) -#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) -#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) -#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ -#define MUX_PA07N_CCL_OUT0 _L_(13) -#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) -#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) -#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ -#define MUX_PA19N_CCL_OUT0 _L_(13) -#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) -#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) -#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ -#define MUX_PB02N_CCL_OUT0 _L_(13) -#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) -#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) -#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ -#define MUX_PB23N_CCL_OUT0 _L_(13) -#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) -#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) -#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ -#define MUX_PA11N_CCL_OUT1 _L_(13) -#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) -#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ -#define MUX_PA31N_CCL_OUT1 _L_(13) -#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) -#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) -#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ -#define MUX_PB11N_CCL_OUT1 _L_(13) -#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) -#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) -#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ -#define MUX_PA25N_CCL_OUT2 _L_(13) -#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) -#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) -#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ -#define MUX_PB09N_CCL_OUT2 _L_(13) -#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) -#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) -#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ -#define MUX_PB17N_CCL_OUT3 _L_(13) -#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) -#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) -/* ========== PORT definition for SERCOM4 peripheral ========== */ -#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ -#define MUX_PA13D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) -#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) -#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ -#define MUX_PB08D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) -#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) -#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ -#define MUX_PB27D_SERCOM4_PAD0 _L_(3) -#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) -#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) -#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ -#define MUX_PB12C_SERCOM4_PAD0 _L_(2) -#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) -#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) -#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ -#define MUX_PA12D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) -#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) -#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ -#define MUX_PB09D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) -#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) -#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ -#define MUX_PB26D_SERCOM4_PAD1 _L_(3) -#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) -#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) -#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ -#define MUX_PB13C_SERCOM4_PAD1 _L_(2) -#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) -#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) -#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ -#define MUX_PA14D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) -#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ -#define MUX_PB10D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) -#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) -#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ -#define MUX_PB28D_SERCOM4_PAD2 _L_(3) -#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) -#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) -#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ -#define MUX_PB14C_SERCOM4_PAD2 _L_(2) -#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) -#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) -#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ -#define MUX_PB11D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) -#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) -#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ -#define MUX_PB29D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) -#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) -#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ -#define MUX_PA15D_SERCOM4_PAD3 _L_(3) -#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) -#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) -#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ -#define MUX_PB15C_SERCOM4_PAD3 _L_(2) -#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) -#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) -/* ========== PORT definition for SERCOM5 peripheral ========== */ -#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ -#define MUX_PA23D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) -#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) -#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ -#define MUX_PB02D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) -#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) -#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ -#define MUX_PB31D_SERCOM5_PAD0 _L_(3) -#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) -#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) -#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ -#define MUX_PB16C_SERCOM5_PAD0 _L_(2) -#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) -#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) -#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ -#define MUX_PA22D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) -#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) -#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ -#define MUX_PB03D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) -#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) -#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ -#define MUX_PB30D_SERCOM5_PAD1 _L_(3) -#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) -#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) -#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ -#define MUX_PB17C_SERCOM5_PAD1 _L_(2) -#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) -#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) -#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ -#define MUX_PA24D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) -#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) -#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ -#define MUX_PB00D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) -#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) -#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ -#define MUX_PB22D_SERCOM5_PAD2 _L_(3) -#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) -#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) -#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ -#define MUX_PA20C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) -#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) -#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ -#define MUX_PB18C_SERCOM5_PAD2 _L_(2) -#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) -#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) -#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ -#define MUX_PA25D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) -#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) -#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ -#define MUX_PB01D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) -#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) -#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ -#define MUX_PB23D_SERCOM5_PAD3 _L_(3) -#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) -#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) -#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ -#define MUX_PA21C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) -#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) -#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ -#define MUX_PB19C_SERCOM5_PAD3 _L_(2) -#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) -#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM6 peripheral ========== */ -#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ -#define MUX_PD09D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) -#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) -#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ -#define MUX_PC13D_SERCOM6_PAD0 _L_(3) -#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) -#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) -#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ -#define MUX_PC04C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) -#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) -#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ -#define MUX_PC16C_SERCOM6_PAD0 _L_(2) -#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) -#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) -#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ -#define MUX_PD08D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) -#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) -#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ -#define MUX_PC12D_SERCOM6_PAD1 _L_(3) -#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) -#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) -#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ -#define MUX_PC05C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) -#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) -#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ -#define MUX_PC17C_SERCOM6_PAD1 _L_(2) -#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) -#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) -#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ -#define MUX_PC14D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) -#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) -#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ -#define MUX_PD10D_SERCOM6_PAD2 _L_(3) -#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) -#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ -#define MUX_PC06C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) -#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) -#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ -#define MUX_PC10C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) -#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) -#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ -#define MUX_PC18C_SERCOM6_PAD2 _L_(2) -#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) -#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) -#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ -#define MUX_PC15D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) -#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) -#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ -#define MUX_PD11D_SERCOM6_PAD3 _L_(3) -#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) -#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ -#define MUX_PC07C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) -#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) -#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ -#define MUX_PC11C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) -#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) -#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ -#define MUX_PC19C_SERCOM6_PAD3 _L_(2) -#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) -#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) -/* ========== PORT definition for SERCOM7 peripheral ========== */ -#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ -#define MUX_PB21D_SERCOM7_PAD0 _L_(3) -#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) -#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) -#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ -#define MUX_PD08C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) -#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) -#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ -#define MUX_PB30C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) -#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) -#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ -#define MUX_PC12C_SERCOM7_PAD0 _L_(2) -#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) -#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) -#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ -#define MUX_PB20D_SERCOM7_PAD1 _L_(3) -#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) -#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) -#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ -#define MUX_PD09C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) -#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) -#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ -#define MUX_PB31C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) -#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) -#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ -#define MUX_PC13C_SERCOM7_PAD1 _L_(2) -#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) -#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) -#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ -#define MUX_PB18D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) -#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) -#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ -#define MUX_PC10D_SERCOM7_PAD2 _L_(3) -#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) -#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ -#define MUX_PC14C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) -#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) -#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ -#define MUX_PD10C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) -#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) -#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ -#define MUX_PA30C_SERCOM7_PAD2 _L_(2) -#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) -#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) -#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ -#define MUX_PB19D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) -#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) -#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ -#define MUX_PC11D_SERCOM7_PAD3 _L_(3) -#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) -#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ -#define MUX_PC15C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) -#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) -#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ -#define MUX_PD11C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) -#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) -#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ -#define MUX_PA31C_SERCOM7_PAD3 _L_(2) -#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) -#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) -/* ========== PORT definition for TCC4 peripheral ========== */ -#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ -#define MUX_PB14F_TCC4_WO0 _L_(5) -#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) -#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) -#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ -#define MUX_PB30F_TCC4_WO0 _L_(5) -#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) -#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) -#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ -#define MUX_PB15F_TCC4_WO1 _L_(5) -#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) -#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) -#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ -#define MUX_PB31F_TCC4_WO1 _L_(5) -#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) -#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) -/* ========== PORT definition for TC6 peripheral ========== */ -#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ -#define MUX_PA30E_TC6_WO0 _L_(4) -#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) -#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) -#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ -#define MUX_PB02E_TC6_WO0 _L_(4) -#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) -#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) -#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ -#define MUX_PB16E_TC6_WO0 _L_(4) -#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) -#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) -#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ -#define MUX_PA31E_TC6_WO1 _L_(4) -#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) -#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) -#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ -#define MUX_PB03E_TC6_WO1 _L_(4) -#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) -#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) -#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ -#define MUX_PB17E_TC6_WO1 _L_(4) -#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) -#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) -/* ========== PORT definition for TC7 peripheral ========== */ -#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ -#define MUX_PA20E_TC7_WO0 _L_(4) -#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) -#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) -#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ -#define MUX_PB00E_TC7_WO0 _L_(4) -#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) -#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) -#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ -#define MUX_PB22E_TC7_WO0 _L_(4) -#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) -#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) -#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ -#define MUX_PA21E_TC7_WO1 _L_(4) -#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) -#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) -#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ -#define MUX_PB01E_TC7_WO1 _L_(4) -#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) -#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) -#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ -#define MUX_PB23E_TC7_WO1 _L_(4) -#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) -#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) -/* ========== PORT definition for ADC0 peripheral ========== */ -#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ -#define MUX_PA02B_ADC0_AIN0 _L_(1) -#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) -#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) -#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ -#define MUX_PA03B_ADC0_AIN1 _L_(1) -#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) -#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ -#define MUX_PB08B_ADC0_AIN2 _L_(1) -#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) -#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ -#define MUX_PB09B_ADC0_AIN3 _L_(1) -#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) -#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ -#define MUX_PA04B_ADC0_AIN4 _L_(1) -#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) -#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) -#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ -#define MUX_PA05B_ADC0_AIN5 _L_(1) -#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) -#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) -#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ -#define MUX_PA06B_ADC0_AIN6 _L_(1) -#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) -#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ -#define MUX_PA07B_ADC0_AIN7 _L_(1) -#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) -#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ -#define MUX_PA08B_ADC0_AIN8 _L_(1) -#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) -#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ -#define MUX_PA09B_ADC0_AIN9 _L_(1) -#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) -#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ -#define MUX_PA10B_ADC0_AIN10 _L_(1) -#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) -#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ -#define MUX_PA11B_ADC0_AIN11 _L_(1) -#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) -#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) -#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ -#define MUX_PB00B_ADC0_AIN12 _L_(1) -#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) -#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ -#define MUX_PB01B_ADC0_AIN13 _L_(1) -#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) -#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) -#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ -#define MUX_PB02B_ADC0_AIN14 _L_(1) -#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) -#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ -#define MUX_PB03B_ADC0_AIN15 _L_(1) -#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) -#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) -#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ -#define MUX_PA03O_ADC0_DRV0 _L_(14) -#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) -#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) -#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ -#define MUX_PB08O_ADC0_DRV1 _L_(14) -#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) -#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) -#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ -#define MUX_PB09O_ADC0_DRV2 _L_(14) -#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) -#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) -#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ -#define MUX_PA04O_ADC0_DRV3 _L_(14) -#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) -#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) -#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ -#define MUX_PA06O_ADC0_DRV4 _L_(14) -#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) -#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) -#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ -#define MUX_PA07O_ADC0_DRV5 _L_(14) -#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) -#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) -#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ -#define MUX_PA08O_ADC0_DRV6 _L_(14) -#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) -#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) -#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ -#define MUX_PA09O_ADC0_DRV7 _L_(14) -#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) -#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) -#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ -#define MUX_PA10O_ADC0_DRV8 _L_(14) -#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) -#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) -#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ -#define MUX_PA11O_ADC0_DRV9 _L_(14) -#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) -#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) -#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ -#define MUX_PA16O_ADC0_DRV10 _L_(14) -#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) -#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) -#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ -#define MUX_PA17O_ADC0_DRV11 _L_(14) -#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) -#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) -#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ -#define MUX_PA18O_ADC0_DRV12 _L_(14) -#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) -#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) -#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ -#define MUX_PA19O_ADC0_DRV13 _L_(14) -#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) -#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) -#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ -#define MUX_PA20O_ADC0_DRV14 _L_(14) -#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) -#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) -#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ -#define MUX_PA21O_ADC0_DRV15 _L_(14) -#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) -#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) -#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ -#define MUX_PA22O_ADC0_DRV16 _L_(14) -#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) -#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) -#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ -#define MUX_PA23O_ADC0_DRV17 _L_(14) -#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) -#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) -#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ -#define MUX_PA27O_ADC0_DRV18 _L_(14) -#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) -#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) -#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ -#define MUX_PA30O_ADC0_DRV19 _L_(14) -#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) -#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) -#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ -#define MUX_PB02O_ADC0_DRV20 _L_(14) -#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) -#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) -#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ -#define MUX_PB03O_ADC0_DRV21 _L_(14) -#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) -#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) -#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ -#define MUX_PB04O_ADC0_DRV22 _L_(14) -#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) -#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) -#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ -#define MUX_PB05O_ADC0_DRV23 _L_(14) -#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) -#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) -#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ -#define MUX_PB06O_ADC0_DRV24 _L_(14) -#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) -#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) -#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ -#define MUX_PB07O_ADC0_DRV25 _L_(14) -#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) -#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) -#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ -#define MUX_PB12O_ADC0_DRV26 _L_(14) -#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) -#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) -#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ -#define MUX_PB13O_ADC0_DRV27 _L_(14) -#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) -#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) -#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ -#define MUX_PB14O_ADC0_DRV28 _L_(14) -#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) -#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) -#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ -#define MUX_PB15O_ADC0_DRV29 _L_(14) -#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) -#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) -#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ -#define MUX_PB00O_ADC0_DRV30 _L_(14) -#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) -#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) -#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ -#define MUX_PB01O_ADC0_DRV31 _L_(14) -#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) -#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) -#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ -#define MUX_PA03B_ADC0_PTCXY0 _L_(1) -#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) -#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) -#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ -#define MUX_PB08B_ADC0_PTCXY1 _L_(1) -#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) -#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) -#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ -#define MUX_PB09B_ADC0_PTCXY2 _L_(1) -#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) -#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) -#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ -#define MUX_PA04B_ADC0_PTCXY3 _L_(1) -#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) -#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) -#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ -#define MUX_PA06B_ADC0_PTCXY4 _L_(1) -#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) -#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) -#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ -#define MUX_PA07B_ADC0_PTCXY5 _L_(1) -#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) -#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) -#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ -#define MUX_PA08B_ADC0_PTCXY6 _L_(1) -#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) -#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) -#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ -#define MUX_PA09B_ADC0_PTCXY7 _L_(1) -#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) -#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) -#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ -#define MUX_PA10B_ADC0_PTCXY8 _L_(1) -#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) -#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) -#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ -#define MUX_PA11B_ADC0_PTCXY9 _L_(1) -#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) -#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) -#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ -#define MUX_PA16B_ADC0_PTCXY10 _L_(1) -#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) -#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) -#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ -#define MUX_PA17B_ADC0_PTCXY11 _L_(1) -#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) -#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) -#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ -#define MUX_PA18B_ADC0_PTCXY12 _L_(1) -#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) -#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) -#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ -#define MUX_PA19B_ADC0_PTCXY13 _L_(1) -#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) -#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) -#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ -#define MUX_PA20B_ADC0_PTCXY14 _L_(1) -#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) -#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) -#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ -#define MUX_PA21B_ADC0_PTCXY15 _L_(1) -#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) -#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) -#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ -#define MUX_PA22B_ADC0_PTCXY16 _L_(1) -#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) -#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) -#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ -#define MUX_PA23B_ADC0_PTCXY17 _L_(1) -#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) -#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) -#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ -#define MUX_PA27B_ADC0_PTCXY18 _L_(1) -#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) -#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) -#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ -#define MUX_PA30B_ADC0_PTCXY19 _L_(1) -#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) -#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) -#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ -#define MUX_PB02B_ADC0_PTCXY20 _L_(1) -#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) -#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) -#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ -#define MUX_PB03B_ADC0_PTCXY21 _L_(1) -#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) -#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) -#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ -#define MUX_PB04B_ADC0_PTCXY22 _L_(1) -#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) -#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) -#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ -#define MUX_PB05B_ADC0_PTCXY23 _L_(1) -#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) -#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) -#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ -#define MUX_PB06B_ADC0_PTCXY24 _L_(1) -#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) -#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) -#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ -#define MUX_PB07B_ADC0_PTCXY25 _L_(1) -#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) -#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) -#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ -#define MUX_PB12B_ADC0_PTCXY26 _L_(1) -#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) -#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) -#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ -#define MUX_PB13B_ADC0_PTCXY27 _L_(1) -#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) -#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) -#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ -#define MUX_PB14B_ADC0_PTCXY28 _L_(1) -#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) -#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) -#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ -#define MUX_PB15B_ADC0_PTCXY29 _L_(1) -#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) -#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) -#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ -#define MUX_PB00B_ADC0_PTCXY30 _L_(1) -#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) -#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) -#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ -#define MUX_PB01B_ADC0_PTCXY31 _L_(1) -#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) -#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) -/* ========== PORT definition for ADC1 peripheral ========== */ -#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ -#define MUX_PB08B_ADC1_AIN0 _L_(1) -#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) -#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) -#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ -#define MUX_PB09B_ADC1_AIN1 _L_(1) -#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) -#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) -#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ -#define MUX_PA08B_ADC1_AIN2 _L_(1) -#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) -#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) -#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ -#define MUX_PA09B_ADC1_AIN3 _L_(1) -#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) -#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) -#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ -#define MUX_PC02B_ADC1_AIN4 _L_(1) -#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) -#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) -#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ -#define MUX_PC03B_ADC1_AIN5 _L_(1) -#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) -#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) -#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ -#define MUX_PB04B_ADC1_AIN6 _L_(1) -#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) -#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) -#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ -#define MUX_PB05B_ADC1_AIN7 _L_(1) -#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) -#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) -#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ -#define MUX_PB06B_ADC1_AIN8 _L_(1) -#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) -#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) -#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ -#define MUX_PB07B_ADC1_AIN9 _L_(1) -#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) -#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) -#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ -#define MUX_PC00B_ADC1_AIN10 _L_(1) -#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) -#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) -#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ -#define MUX_PC01B_ADC1_AIN11 _L_(1) -#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) -#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) -#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ -#define MUX_PC30B_ADC1_AIN12 _L_(1) -#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) -#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) -#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ -#define MUX_PC31B_ADC1_AIN13 _L_(1) -#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) -#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) -#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ -#define MUX_PD00B_ADC1_AIN14 _L_(1) -#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) -#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) -#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ -#define MUX_PD01B_ADC1_AIN15 _L_(1) -#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) -#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) -/* ========== PORT definition for DAC peripheral ========== */ -#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ -#define MUX_PA02B_DAC_VOUT0 _L_(1) -#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) -#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) -#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ -#define MUX_PA05B_DAC_VOUT1 _L_(1) -#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) -#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) -/* ========== PORT definition for I2S peripheral ========== */ -#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ -#define MUX_PA09J_I2S_FS0 _L_(9) -#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) -#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) -#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ -#define MUX_PA20J_I2S_FS0 _L_(9) -#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) -#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) -#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ -#define MUX_PA23J_I2S_FS1 _L_(9) -#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) -#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) -#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ -#define MUX_PB11J_I2S_FS1 _L_(9) -#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) -#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) -#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ -#define MUX_PA08J_I2S_MCK0 _L_(9) -#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) -#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) -#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ -#define MUX_PB17J_I2S_MCK0 _L_(9) -#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) -#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) -#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ -#define MUX_PB29J_I2S_MCK1 _L_(9) -#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) -#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) -#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ -#define MUX_PB13J_I2S_MCK1 _L_(9) -#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) -#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) -#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ -#define MUX_PA10J_I2S_SCK0 _L_(9) -#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) -#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) -#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ -#define MUX_PB16J_I2S_SCK0 _L_(9) -#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) -#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) -#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ -#define MUX_PB28J_I2S_SCK1 _L_(9) -#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) -#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) -#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ -#define MUX_PB12J_I2S_SCK1 _L_(9) -#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) -#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) -#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ -#define MUX_PA22J_I2S_SDI _L_(9) -#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) -#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) -#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ -#define MUX_PB10J_I2S_SDI _L_(9) -#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) -#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) -#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ -#define MUX_PA11J_I2S_SDO _L_(9) -#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) -#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) -#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ -#define MUX_PA21J_I2S_SDO _L_(9) -#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) -#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) -/* ========== PORT definition for PCC peripheral ========== */ -#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ -#define MUX_PA14K_PCC_CLK _L_(10) -#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) -#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) -#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ -#define MUX_PA16K_PCC_DATA0 _L_(10) -#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) -#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) -#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ -#define MUX_PA17K_PCC_DATA1 _L_(10) -#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) -#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) -#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ -#define MUX_PA18K_PCC_DATA2 _L_(10) -#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) -#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) -#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ -#define MUX_PA19K_PCC_DATA3 _L_(10) -#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) -#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) -#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ -#define MUX_PA20K_PCC_DATA4 _L_(10) -#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) -#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) -#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ -#define MUX_PA21K_PCC_DATA5 _L_(10) -#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) -#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) -#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ -#define MUX_PA22K_PCC_DATA6 _L_(10) -#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) -#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) -#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ -#define MUX_PA23K_PCC_DATA7 _L_(10) -#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) -#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) -#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ -#define MUX_PB14K_PCC_DATA8 _L_(10) -#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) -#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) -#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ -#define MUX_PB15K_PCC_DATA9 _L_(10) -#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) -#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) -#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ -#define MUX_PC12K_PCC_DATA10 _L_(10) -#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) -#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) -#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ -#define MUX_PC13K_PCC_DATA11 _L_(10) -#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) -#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) -#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ -#define MUX_PC14K_PCC_DATA12 _L_(10) -#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) -#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) -#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ -#define MUX_PC15K_PCC_DATA13 _L_(10) -#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) -#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) -#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ -#define MUX_PA12K_PCC_DEN1 _L_(10) -#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) -#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) -#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ -#define MUX_PA13K_PCC_DEN2 _L_(10) -#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) -#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) -/* ========== PORT definition for SDHC0 peripheral ========== */ -#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ -#define MUX_PA06I_SDHC0_SDCD _L_(8) -#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) -#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ -#define MUX_PA12I_SDHC0_SDCD _L_(8) -#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) -#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ -#define MUX_PB12I_SDHC0_SDCD _L_(8) -#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) -#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) -#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ -#define MUX_PC06I_SDHC0_SDCD _L_(8) -#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) -#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) -#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ -#define MUX_PB11I_SDHC0_SDCK _L_(8) -#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) -#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) -#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ -#define MUX_PA08I_SDHC0_SDCMD _L_(8) -#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) -#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) -#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ -#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) -#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) -#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) -#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ -#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) -#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) -#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) -#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ -#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) -#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) -#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) -#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ -#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) -#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) -#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) -#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ -#define MUX_PA07I_SDHC0_SDWP _L_(8) -#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) -#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) -#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ -#define MUX_PA13I_SDHC0_SDWP _L_(8) -#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) -#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ -#define MUX_PB13I_SDHC0_SDWP _L_(8) -#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) -#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) -#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ -#define MUX_PC07I_SDHC0_SDWP _L_(8) -#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) -#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) -/* ========== PORT definition for SDHC1 peripheral ========== */ -#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ -#define MUX_PB16I_SDHC1_SDCD _L_(8) -#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) -#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) -#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ -#define MUX_PC20I_SDHC1_SDCD _L_(8) -#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) -#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ -#define MUX_PD20I_SDHC1_SDCD _L_(8) -#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) -#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) -#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ -#define MUX_PA21I_SDHC1_SDCK _L_(8) -#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) -#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) -#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ -#define MUX_PA20I_SDHC1_SDCMD _L_(8) -#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) -#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) -#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ -#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) -#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) -#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) -#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ -#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) -#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) -#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) -#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ -#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) -#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) -#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) -#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ -#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) -#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) -#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) -#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ -#define MUX_PB17I_SDHC1_SDWP _L_(8) -#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) -#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) -#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ -#define MUX_PC21I_SDHC1_SDWP _L_(8) -#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) -#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) -#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ -#define MUX_PD21I_SDHC1_SDWP _L_(8) -#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) -#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) - -#endif /* _SAMD51P20A_PIO_ */ +/** + * \file + * + * \brief Peripheral I/O description for SAMD51P20A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P20A_PIO_ +#define _SAMD51P20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAMD51P20A_PIO_ */ diff --git a/lib/samd51/samd51a/include/sam.h b/lib/samd51/samd51a/include/sam.h index 59afcbd..ac52c4d 100644 --- a/lib/samd51/samd51a/include/sam.h +++ b/lib/samd51/samd51a/include/sam.h @@ -1,56 +1,56 @@ -/** - * \file - * - * \brief Top level header file - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \license_stop - * - */ - -#ifndef _SAM_ -#define _SAM_ - -#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) - #include "samd51g18a.h" -#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) - #include "samd51g19a.h" -#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) - #include "samd51j18a.h" -#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) - #include "samd51j19a.h" -#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) - #include "samd51j20a.h" -#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) - #include "samd51n19a.h" -#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) - #include "samd51n20a.h" -#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) - #include "samd51p19a.h" -#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) - #include "samd51p20a.h" -#else - #error Library does not support the specified device -#endif - -#endif /* _SAM_ */ - +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) + #include "samd51g18a.h" +#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) + #include "samd51g19a.h" +#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) + #include "samd51j18a.h" +#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) + #include "samd51j19a.h" +#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) + #include "samd51j20a.h" +#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) + #include "samd51n19a.h" +#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) + #include "samd51n20a.h" +#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) + #include "samd51p19a.h" +#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) + #include "samd51p20a.h" +#else + #error Library does not support the specified device +#endif + +#endif /* _SAM_ */ + diff --git a/lib/samd51/samd51a/include/samd51.h b/lib/samd51/samd51a/include/samd51.h index 62934a8..f023e48 100644 --- a/lib/samd51/samd51a/include/samd51.h +++ b/lib/samd51/samd51a/include/samd51.h @@ -1,64 +1,64 @@ -/** - * \file - * - * \brief Top header file for SAMD51 - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51_ -#define _SAMD51_ - -/** - * \defgroup SAMD51_definitions SAMD51 Device Definitions - * \brief SAMD51 CMSIS Definitions. - */ - -#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) - #include "samd51g18a.h" -#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) - #include "samd51g19a.h" -#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) - #include "samd51j18a.h" -#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) - #include "samd51j19a.h" -#elif defined(__SAMD51J19B__) || defined(__ATSAMD51J19B__) - #include "samd51j19b.h" -#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) - #include "samd51j20a.h" -#elif defined(__SAMD51J20CU__) || defined(__ATSAMD51J20CU__) - #include "samd51j20cu.h" -#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) - #include "samd51n19a.h" -#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) - #include "samd51n20a.h" -#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) - #include "samd51p19a.h" -#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) - #include "samd51p20a.h" -#else - #error Library does not support the specified device. -#endif - -#endif /* _SAMD51_ */ +/** + * \file + * + * \brief Top header file for SAMD51 + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51_ +#define _SAMD51_ + +/** + * \defgroup SAMD51_definitions SAMD51 Device Definitions + * \brief SAMD51 CMSIS Definitions. + */ + +#if defined(__SAMD51G18A__) || defined(__ATSAMD51G18A__) + #include "samd51g18a.h" +#elif defined(__SAMD51G19A__) || defined(__ATSAMD51G19A__) + #include "samd51g19a.h" +#elif defined(__SAMD51J18A__) || defined(__ATSAMD51J18A__) + #include "samd51j18a.h" +#elif defined(__SAMD51J19A__) || defined(__ATSAMD51J19A__) + #include "samd51j19a.h" +#elif defined(__SAMD51J19B__) || defined(__ATSAMD51J19B__) + #include "samd51j19b.h" +#elif defined(__SAMD51J20A__) || defined(__ATSAMD51J20A__) + #include "samd51j20a.h" +#elif defined(__SAMD51J20CU__) || defined(__ATSAMD51J20CU__) + #include "samd51j20cu.h" +#elif defined(__SAMD51N19A__) || defined(__ATSAMD51N19A__) + #include "samd51n19a.h" +#elif defined(__SAMD51N20A__) || defined(__ATSAMD51N20A__) + #include "samd51n20a.h" +#elif defined(__SAMD51P19A__) || defined(__ATSAMD51P19A__) + #include "samd51p19a.h" +#elif defined(__SAMD51P20A__) || defined(__ATSAMD51P20A__) + #include "samd51p20a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMD51_ */ diff --git a/lib/samd51/samd51a/include/samd51g18a.h b/lib/samd51/samd51a/include/samd51g18a.h index 6a13ead..c9b5ddb 100644 --- a/lib/samd51/samd51a/include/samd51g18a.h +++ b/lib/samd51/samd51a/include/samd51g18a.h @@ -1,975 +1,975 @@ -/** - * \file - * - * \brief Header file for SAMD51G18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G18A_ -#define _SAMD51G18A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51G18A_definitions SAMD51G18A definitions - * This file defines all structures and symbols for SAMD51G18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51G18A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51G18A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51G18A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G18A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51G18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51G18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51G18A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51G18A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51G18A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51G18A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51G18A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51G18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51G18A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TC0_IRQn = 107, /**< 107 SAMD51G18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51G18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51G18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51G18A Basic Timer Counter 3 (TC3) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51G18A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - PCC_IRQn = 129, /**< 129 SAMD51G18A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51G18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51G18A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51G18A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51G18A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51G18A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51G18A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pvReserved101; - void* pvReserved102; - void* pvReserved103; - void* pvReserved104; - void* pvReserved105; - void* pvReserved106; - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pvReserved111; - void* pvReserved112; - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pvReserved128; - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51g18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060308) -#define ADC0_TOUCH_LINES_NUM 22 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51G18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51G18A_H */ +/** + * \file + * + * \brief Header file for SAMD51G18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G18A_ +#define _SAMD51G18A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51G18A_definitions SAMD51G18A definitions + * This file defines all structures and symbols for SAMD51G18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51G18A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51G18A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51G18A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G18A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51G18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51G18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51G18A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51G18A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51G18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51G18A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51G18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51G18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51G18A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51G18A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51G18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51G18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51G18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51G18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51G18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51G18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51G18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51G18A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51G18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51G18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51G18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51G18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TC0_IRQn = 107, /**< 107 SAMD51G18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51G18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51G18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51G18A Basic Timer Counter 3 (TC3) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51G18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51G18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51G18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51G18A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51G18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + PCC_IRQn = 129, /**< 129 SAMD51G18A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51G18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51G18A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51G18A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51G18A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51G18A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51G18A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pvReserved101; + void* pvReserved102; + void* pvReserved103; + void* pvReserved104; + void* pvReserved105; + void* pvReserved106; + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pvReserved111; + void* pvReserved112; + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pvReserved128; + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51g18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060308) +#define ADC0_TOUCH_LINES_NUM 22 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51G18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51G18A_H */ diff --git a/lib/samd51/samd51a/include/samd51g19a.h b/lib/samd51/samd51a/include/samd51g19a.h index 510a587..0e09813 100644 --- a/lib/samd51/samd51a/include/samd51g19a.h +++ b/lib/samd51/samd51a/include/samd51g19a.h @@ -1,975 +1,975 @@ -/** - * \file - * - * \brief Header file for SAMD51G19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51G19A_ -#define _SAMD51G19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51G19A_definitions SAMD51G19A definitions - * This file defines all structures and symbols for SAMD51G19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51G19A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51G19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51G19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51G19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51G19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51G19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51G19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51G19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51G19A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51G19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51G19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51G19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TC0_IRQn = 107, /**< 107 SAMD51G19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51G19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51G19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51G19A Basic Timer Counter 3 (TC3) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51G19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - PCC_IRQn = 129, /**< 129 SAMD51G19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51G19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51G19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51G19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51G19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51G19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51G19A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pvReserved101; - void* pvReserved102; - void* pvReserved103; - void* pvReserved104; - void* pvReserved105; - void* pvReserved106; - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pvReserved111; - void* pvReserved112; - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pvReserved128; - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51G19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51g19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060307) -#define ADC0_TOUCH_LINES_NUM 22 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51G19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51G19A_H */ +/** + * \file + * + * \brief Header file for SAMD51G19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51G19A_ +#define _SAMD51G19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51G19A_definitions SAMD51G19A definitions + * This file defines all structures and symbols for SAMD51G19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51G19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51G19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51G19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51G19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51G19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51G19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51G19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51G19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51G19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51G19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51G19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51G19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51G19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51G19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51G19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51G19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51G19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51G19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51G19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51G19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51G19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51G19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51G19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51G19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51G19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51G19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51G19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51G19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TC0_IRQn = 107, /**< 107 SAMD51G19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51G19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51G19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51G19A Basic Timer Counter 3 (TC3) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51G19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51G19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51G19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51G19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51G19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + PCC_IRQn = 129, /**< 129 SAMD51G19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51G19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51G19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51G19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51G19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51G19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51G19A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pvReserved101; + void* pvReserved102; + void* pvReserved103; + void* pvReserved104; + void* pvReserved105; + void* pvReserved106; + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pvReserved111; + void* pvReserved112; + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pvReserved128; + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC_INST_NUM 4 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51G19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51g19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060307) +#define ADC0_TOUCH_LINES_NUM 22 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51G19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51G19A_H */ diff --git a/lib/samd51/samd51a/include/samd51j18a.h b/lib/samd51/samd51a/include/samd51j18a.h index 37c3914..1239317 100644 --- a/lib/samd51/samd51a/include/samd51j18a.h +++ b/lib/samd51/samd51a/include/samd51j18a.h @@ -1,1017 +1,1017 @@ -/** - * \file - * - * \brief Header file for SAMD51J18A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J18A_ -#define _SAMD51J18A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions - * This file defines all structures and symbols for SAMD51J18A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51J18A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51J18A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J18A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J18A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j18a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ -#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 512 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060306) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J18A_H */ +/** + * \file + * + * \brief Header file for SAMD51J18A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J18A_ +#define _SAMD51J18A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51J18A_definitions SAMD51J18A definitions + * This file defines all structures and symbols for SAMD51J18A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51J18A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51J18A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51J18A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J18A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J18A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51J18A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51J18A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51J18A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51J18A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51J18A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51J18A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J18A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51J18A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51J18A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51J18A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51J18A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51J18A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51J18A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51J18A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51J18A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51J18A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51J18A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51J18A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51J18A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51J18A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51J18A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51J18A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51J18A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51J18A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51J18A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51J18A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51J18A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51J18A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51J18A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51J18A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51J18A Basic Timer Counter 5 (TC5) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51J18A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51J18A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51J18A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51J18A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51J18A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51J18A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51J18A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51J18A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51J18A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51J18A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51J18A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51J18A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51J18A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J18A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51j18a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00020000) /* 128 kB */ +#define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 512 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060306) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J18A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51J18A_H */ diff --git a/lib/samd51/samd51a/include/samd51j19a.h b/lib/samd51/samd51a/include/samd51j19a.h index d5a05e1..f6185a6 100644 --- a/lib/samd51/samd51a/include/samd51j19a.h +++ b/lib/samd51/samd51a/include/samd51j19a.h @@ -1,1017 +1,1017 @@ -/** - * \file - * - * \brief Header file for SAMD51J19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J19A_ -#define _SAMD51J19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J19A_definitions SAMD51J19A definitions - * This file defines all structures and symbols for SAMD51J19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51J19A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51J19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J19A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51J19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J19A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J19A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060305) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J19A_H */ +/** + * \file + * + * \brief Header file for SAMD51J19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J19A_ +#define _SAMD51J19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51J19A_definitions SAMD51J19A definitions + * This file defines all structures and symbols for SAMD51J19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51J19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51J19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51J19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51J19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51J19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51J19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51J19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51J19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51J19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51J19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51J19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51J19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51J19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51J19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51J19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51J19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51J19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51J19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51J19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51J19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51J19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51J19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51J19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51J19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51J19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51J19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51J19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51J19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51J19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51J19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51J19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51J19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51J19A Basic Timer Counter 5 (TC5) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51J19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51J19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51J19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51J19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51J19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51J19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51J19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51J19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51J19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51J19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51J19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51J19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51J19A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51j19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060305) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51J19A_H */ diff --git a/lib/samd51/samd51a/include/samd51j20a.h b/lib/samd51/samd51a/include/samd51j20a.h index 28c5369..f7b5c49 100644 --- a/lib/samd51/samd51a/include/samd51j20a.h +++ b/lib/samd51/samd51a/include/samd51j20a.h @@ -1,1017 +1,1017 @@ -/** - * \file - * - * \brief Header file for SAMD51J20A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51J20A_ -#define _SAMD51J20A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51J20A_definitions SAMD51J20A definitions - * This file defines all structures and symbols for SAMD51J20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51J20A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51J20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51J20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51J20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51J20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51J20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51J20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51J20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51J20A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51J20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51J20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51J20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51J20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51J20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51J20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51J20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51J20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51J20A Basic Timer Counter 5 (TC5) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51J20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51J20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51J20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51J20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51J20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51J20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51J20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51J20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51J20A SD/MMC Host Controller 0 (SDHC0) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pvReserved70; - void* pvReserved71; - void* pvReserved72; - void* pvReserved73; - void* pvReserved74; - void* pvReserved75; - void* pvReserved76; - void* pvReserved77; - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pvReserved113; - void* pvReserved114; - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pvReserved136; -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ - -#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51J20A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51j20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060304) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 2 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51J20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51J20A_H */ +/** + * \file + * + * \brief Header file for SAMD51J20A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51J20A_ +#define _SAMD51J20A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51J20A_definitions SAMD51J20A definitions + * This file defines all structures and symbols for SAMD51J20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51J20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51J20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51J20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51J20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51J20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51J20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51J20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51J20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51J20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51J20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51J20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51J20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51J20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51J20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51J20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51J20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51J20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51J20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51J20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51J20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51J20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51J20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51J20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51J20A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51J20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51J20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51J20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51J20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51J20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51J20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51J20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51J20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51J20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51J20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51J20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51J20A Basic Timer Counter 5 (TC5) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51J20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51J20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51J20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51J20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51J20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51J20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51J20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51J20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51J20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51J20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51J20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51J20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51J20A SD/MMC Host Controller 0 (SDHC0) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pvReserved70; + void* pvReserved71; + void* pvReserved72; + void* pvReserved73; + void* pvReserved74; + void* pvReserved75; + void* pvReserved76; + void* pvReserved77; + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pvReserved113; + void* pvReserved114; + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pvReserved136; +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ + +#define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC_INST_NUM 1 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC_INST_NUM 6 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51J20A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51j20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060304) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 2 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51J20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51J20A_H */ diff --git a/lib/samd51/samd51a/include/samd51n19a.h b/lib/samd51/samd51a/include/samd51n19a.h index bd067fa..23a7b82 100644 --- a/lib/samd51/samd51a/include/samd51n19a.h +++ b/lib/samd51/samd51a/include/samd51n19a.h @@ -1,1059 +1,1059 @@ -/** - * \file - * - * \brief Header file for SAMD51N19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N19A_ -#define _SAMD51N19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51N19A_definitions SAMD51N19A definitions - * This file defines all structures and symbols for SAMD51N19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51N19A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51N19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51N19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51N19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51N19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51N19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51N19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51N19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51N19A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51N19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51N19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51N19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51N19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51N19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51N19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51N19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51N19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51N19A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51N19A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51N19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51N19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51N19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51N19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51N19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51N19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51N19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51N19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51N19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51N19A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51N19A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51n19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060303) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51N19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51N19A_H */ +/** + * \file + * + * \brief Header file for SAMD51N19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N19A_ +#define _SAMD51N19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51N19A_definitions SAMD51N19A definitions + * This file defines all structures and symbols for SAMD51N19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51N19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51N19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51N19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51N19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51N19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51N19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51N19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51N19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51N19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51N19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51N19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51N19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51N19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51N19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51N19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51N19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51N19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51N19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51N19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51N19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51N19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51N19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51N19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51N19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51N19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51N19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51N19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51N19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51N19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51N19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51N19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51N19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51N19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51N19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51N19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51N19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51N19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51N19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51N19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51N19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51N19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51N19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51N19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51N19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51N19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51N19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51N19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51N19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51N19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51N19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51N19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51n19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060303) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51N19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51N19A_H */ diff --git a/lib/samd51/samd51a/include/samd51n20a.h b/lib/samd51/samd51a/include/samd51n20a.h index fabcb00..846f5e8 100644 --- a/lib/samd51/samd51a/include/samd51n20a.h +++ b/lib/samd51/samd51a/include/samd51n20a.h @@ -1,1059 +1,1059 @@ -/** - * \file - * - * \brief Header file for SAMD51N20A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51N20A_ -#define _SAMD51N20A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51N20A_definitions SAMD51N20A definitions - * This file defines all structures and symbols for SAMD51N20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51N20A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51N20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51N20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51N20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51N20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51N20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51N20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51N20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51N20A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51N20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51N20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51N20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51N20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51N20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51N20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51N20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51N20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51N20A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51N20A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51N20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51N20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51N20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51N20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51N20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51N20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51N20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51N20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51N20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51N20A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51N20A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51N20A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51n20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060302) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 3 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51N20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51N20A_H */ +/** + * \file + * + * \brief Header file for SAMD51N20A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51N20A_ +#define _SAMD51N20A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51N20A_definitions SAMD51N20A definitions + * This file defines all structures and symbols for SAMD51N20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51N20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51N20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51N20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51N20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51N20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51N20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51N20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51N20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51N20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51N20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51N20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51N20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51N20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51N20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51N20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51N20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51N20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51N20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51N20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51N20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51N20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51N20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51N20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51N20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51N20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51N20A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51N20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51N20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51N20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51N20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51N20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51N20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51N20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51N20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51N20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51N20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51N20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51N20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51N20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51N20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51N20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51N20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51N20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51N20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51N20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51N20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51N20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51N20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51N20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51N20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51N20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51N20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51N20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51N20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51N20A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51n20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060302) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51N20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51N20A_H */ diff --git a/lib/samd51/samd51a/include/samd51p19a.h b/lib/samd51/samd51a/include/samd51p19a.h index 39bb9de..f3a5936 100644 --- a/lib/samd51/samd51a/include/samd51p19a.h +++ b/lib/samd51/samd51a/include/samd51p19a.h @@ -1,1059 +1,1059 @@ -/** - * \file - * - * \brief Header file for SAMD51P19A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P19A_ -#define _SAMD51P19A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51P19A_definitions SAMD51P19A definitions - * This file defines all structures and symbols for SAMD51P19A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51P19A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51P19A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51P19A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P19A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51P19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51P19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51P19A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51P19A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51P19A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51P19A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51P19A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51P19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51P19A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51P19A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51P19A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51P19A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51P19A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51P19A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51P19A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51P19A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51P19A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51P19A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51P19A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51P19A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51P19A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51P19A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51P19A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51P19A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51P19A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51P19A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51P19A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P19A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51p19a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ -#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 1024 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060301) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 4 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51P19A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51P19A_H */ +/** + * \file + * + * \brief Header file for SAMD51P19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P19A_ +#define _SAMD51P19A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51P19A_definitions SAMD51P19A definitions + * This file defines all structures and symbols for SAMD51P19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51P19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51P19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51P19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P19A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51P19A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51P19A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51P19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51P19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51P19A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51P19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P19A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51P19A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51P19A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51P19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51P19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51P19A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51P19A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51P19A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51P19A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51P19A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51P19A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51P19A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51P19A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51P19A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51P19A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51P19A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51P19A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51P19A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51P19A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51P19A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51P19A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51P19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51P19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51P19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51P19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51P19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51P19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51P19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51P19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51P19A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51P19A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51P19A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51P19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51P19A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51P19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51P19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51P19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51P19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51P19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51P19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51P19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51P19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51P19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P19A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51p19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060301) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51P19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51P19A_H */ diff --git a/lib/samd51/samd51a/include/samd51p20a.h b/lib/samd51/samd51a/include/samd51p20a.h index 9e157ed..2ba63d6 100644 --- a/lib/samd51/samd51a/include/samd51p20a.h +++ b/lib/samd51/samd51a/include/samd51p20a.h @@ -1,1059 +1,1059 @@ -/** - * \file - * - * \brief Header file for SAMD51P20A - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SAMD51P20A_ -#define _SAMD51P20A_ - -/** - * \ingroup SAMD51_definitions - * \addtogroup SAMD51P20A_definitions SAMD51P20A definitions - * This file defines all structures and symbols for SAMD51P20A: - * - registers and bitfields - * - peripheral base address - * - peripheral ID - * - PIO definitions -*/ -/*@{*/ - -#ifdef __cplusplus - extern "C" { -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -#include -#ifndef __cplusplus -typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#else -typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ -typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ -typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ -#endif -typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ -typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ -typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ -typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ -#endif - -#if !defined(SKIP_INTEGER_LITERALS) -#if defined(_U_) || defined(_L_) || defined(_UL_) - #error "Integer Literals macros already defined elsewhere" -#endif - -#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) -/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ -#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ -#define _L_(x) x ## L /**< C code: Long integer literal constant value */ -#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ -#else /* Assembler */ -#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ -#define _L_(x) x /**< Assembler: Long integer literal constant value */ -#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ -#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -#endif /* SKIP_INTEGER_LITERALS */ - -/* ************************************************************************** */ -/** CMSIS DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_cmsis CMSIS Definitions */ -/*@{*/ - -/** Interrupt Number Definition */ -typedef enum IRQn -{ - /****** Cortex-M4 Processor Exceptions Numbers *******************/ - NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ - MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ - BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ - UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ - SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ - DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ - PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ - SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ - /****** SAMD51P20A-specific Interrupt Numbers *********************/ - PM_IRQn = 0, /**< 0 SAMD51P20A Power Manager (PM) */ - MCLK_IRQn = 1, /**< 1 SAMD51P20A Main Clock (MCLK) */ - OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ - OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ - OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ - OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ - OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ - OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P20A 32kHz Oscillators Control (OSC32KCTRL) */ - SUPC_0_IRQn = 8, /**< 8 SAMD51P20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ - SUPC_1_IRQn = 9, /**< 9 SAMD51P20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ - WDT_IRQn = 10, /**< 10 SAMD51P20A Watchdog Timer (WDT) */ - RTC_IRQn = 11, /**< 11 SAMD51P20A Real-Time Counter (RTC) */ - EIC_0_IRQn = 12, /**< 12 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ - EIC_1_IRQn = 13, /**< 13 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ - EIC_2_IRQn = 14, /**< 14 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ - EIC_3_IRQn = 15, /**< 15 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ - EIC_4_IRQn = 16, /**< 16 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ - EIC_5_IRQn = 17, /**< 17 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ - EIC_6_IRQn = 18, /**< 18 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ - EIC_7_IRQn = 19, /**< 19 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ - EIC_8_IRQn = 20, /**< 20 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ - EIC_9_IRQn = 21, /**< 21 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ - EIC_10_IRQn = 22, /**< 22 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ - EIC_11_IRQn = 23, /**< 23 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ - EIC_12_IRQn = 24, /**< 24 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ - EIC_13_IRQn = 25, /**< 25 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ - EIC_14_IRQn = 26, /**< 26 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ - EIC_15_IRQn = 27, /**< 27 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ - FREQM_IRQn = 28, /**< 28 SAMD51P20A Frequency Meter (FREQM) */ - NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ - NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ - DMAC_0_IRQn = 31, /**< 31 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ - DMAC_1_IRQn = 32, /**< 32 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ - DMAC_2_IRQn = 33, /**< 33 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ - DMAC_3_IRQn = 34, /**< 34 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ - DMAC_4_IRQn = 35, /**< 35 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ - EVSYS_0_IRQn = 36, /**< 36 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ - EVSYS_1_IRQn = 37, /**< 37 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ - EVSYS_2_IRQn = 38, /**< 38 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ - EVSYS_3_IRQn = 39, /**< 39 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ - EVSYS_4_IRQn = 40, /**< 40 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ - PAC_IRQn = 41, /**< 41 SAMD51P20A Peripheral Access Controller (PAC) */ - RAMECC_IRQn = 45, /**< 45 SAMD51P20A RAM ECC (RAMECC) */ - SERCOM0_0_IRQn = 46, /**< 46 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ - SERCOM0_1_IRQn = 47, /**< 47 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ - SERCOM0_2_IRQn = 48, /**< 48 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ - SERCOM0_3_IRQn = 49, /**< 49 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ - SERCOM1_0_IRQn = 50, /**< 50 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ - SERCOM1_1_IRQn = 51, /**< 51 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ - SERCOM1_2_IRQn = 52, /**< 52 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ - SERCOM1_3_IRQn = 53, /**< 53 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ - SERCOM2_0_IRQn = 54, /**< 54 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ - SERCOM2_1_IRQn = 55, /**< 55 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ - SERCOM2_2_IRQn = 56, /**< 56 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ - SERCOM2_3_IRQn = 57, /**< 57 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ - SERCOM3_0_IRQn = 58, /**< 58 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ - SERCOM3_1_IRQn = 59, /**< 59 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ - SERCOM3_2_IRQn = 60, /**< 60 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ - SERCOM3_3_IRQn = 61, /**< 61 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ - SERCOM4_0_IRQn = 62, /**< 62 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ - SERCOM4_1_IRQn = 63, /**< 63 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ - SERCOM4_2_IRQn = 64, /**< 64 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ - SERCOM4_3_IRQn = 65, /**< 65 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ - SERCOM5_0_IRQn = 66, /**< 66 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ - SERCOM5_1_IRQn = 67, /**< 67 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ - SERCOM5_2_IRQn = 68, /**< 68 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ - SERCOM5_3_IRQn = 69, /**< 69 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ - SERCOM6_0_IRQn = 70, /**< 70 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ - SERCOM6_1_IRQn = 71, /**< 71 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ - SERCOM6_2_IRQn = 72, /**< 72 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ - SERCOM6_3_IRQn = 73, /**< 73 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ - SERCOM7_0_IRQn = 74, /**< 74 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ - SERCOM7_1_IRQn = 75, /**< 75 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ - SERCOM7_2_IRQn = 76, /**< 76 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ - SERCOM7_3_IRQn = 77, /**< 77 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ - USB_0_IRQn = 80, /**< 80 SAMD51P20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ - USB_1_IRQn = 81, /**< 81 SAMD51P20A Universal Serial Bus (USB): USB_SOF_HSOF */ - USB_2_IRQn = 82, /**< 82 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ - USB_3_IRQn = 83, /**< 83 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ - TCC0_0_IRQn = 85, /**< 85 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ - TCC0_1_IRQn = 86, /**< 86 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ - TCC0_2_IRQn = 87, /**< 87 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ - TCC0_3_IRQn = 88, /**< 88 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ - TCC0_4_IRQn = 89, /**< 89 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ - TCC0_5_IRQn = 90, /**< 90 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ - TCC0_6_IRQn = 91, /**< 91 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ - TCC1_0_IRQn = 92, /**< 92 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ - TCC1_1_IRQn = 93, /**< 93 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ - TCC1_2_IRQn = 94, /**< 94 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ - TCC1_3_IRQn = 95, /**< 95 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ - TCC1_4_IRQn = 96, /**< 96 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ - TCC2_0_IRQn = 97, /**< 97 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ - TCC2_1_IRQn = 98, /**< 98 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ - TCC2_2_IRQn = 99, /**< 99 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ - TCC2_3_IRQn = 100, /**< 100 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ - TCC3_0_IRQn = 101, /**< 101 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ - TCC3_1_IRQn = 102, /**< 102 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ - TCC3_2_IRQn = 103, /**< 103 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ - TCC4_0_IRQn = 104, /**< 104 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ - TCC4_1_IRQn = 105, /**< 105 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ - TCC4_2_IRQn = 106, /**< 106 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ - TC0_IRQn = 107, /**< 107 SAMD51P20A Basic Timer Counter 0 (TC0) */ - TC1_IRQn = 108, /**< 108 SAMD51P20A Basic Timer Counter 1 (TC1) */ - TC2_IRQn = 109, /**< 109 SAMD51P20A Basic Timer Counter 2 (TC2) */ - TC3_IRQn = 110, /**< 110 SAMD51P20A Basic Timer Counter 3 (TC3) */ - TC4_IRQn = 111, /**< 111 SAMD51P20A Basic Timer Counter 4 (TC4) */ - TC5_IRQn = 112, /**< 112 SAMD51P20A Basic Timer Counter 5 (TC5) */ - TC6_IRQn = 113, /**< 113 SAMD51P20A Basic Timer Counter 6 (TC6) */ - TC7_IRQn = 114, /**< 114 SAMD51P20A Basic Timer Counter 7 (TC7) */ - PDEC_0_IRQn = 115, /**< 115 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ - PDEC_1_IRQn = 116, /**< 116 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ - PDEC_2_IRQn = 117, /**< 117 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ - ADC0_0_IRQn = 118, /**< 118 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ - ADC0_1_IRQn = 119, /**< 119 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ - ADC1_0_IRQn = 120, /**< 120 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ - ADC1_1_IRQn = 121, /**< 121 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ - AC_IRQn = 122, /**< 122 SAMD51P20A Analog Comparators (AC) */ - DAC_0_IRQn = 123, /**< 123 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ - DAC_1_IRQn = 124, /**< 124 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ - DAC_2_IRQn = 125, /**< 125 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ - DAC_3_IRQn = 126, /**< 126 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ - DAC_4_IRQn = 127, /**< 127 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ - I2S_IRQn = 128, /**< 128 SAMD51P20A Inter-IC Sound Interface (I2S) */ - PCC_IRQn = 129, /**< 129 SAMD51P20A Parallel Capture Controller (PCC) */ - AES_IRQn = 130, /**< 130 SAMD51P20A Advanced Encryption Standard (AES) */ - TRNG_IRQn = 131, /**< 131 SAMD51P20A True Random Generator (TRNG) */ - ICM_IRQn = 132, /**< 132 SAMD51P20A Integrity Check Monitor (ICM) */ - PUKCC_IRQn = 133, /**< 133 SAMD51P20A PUblic-Key Cryptography Controller (PUKCC) */ - QSPI_IRQn = 134, /**< 134 SAMD51P20A Quad SPI interface (QSPI) */ - SDHC0_IRQn = 135, /**< 135 SAMD51P20A SD/MMC Host Controller 0 (SDHC0) */ - SDHC1_IRQn = 136, /**< 136 SAMD51P20A SD/MMC Host Controller 1 (SDHC1) */ - - PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ -} IRQn_Type; - -typedef struct _DeviceVectors -{ - /* Stack pointer */ - void* pvStack; - - /* Cortex-M handlers */ - void* pfnReset_Handler; - void* pfnNonMaskableInt_Handler; - void* pfnHardFault_Handler; - void* pfnMemManagement_Handler; - void* pfnBusFault_Handler; - void* pfnUsageFault_Handler; - void* pvReservedM9; - void* pvReservedM8; - void* pvReservedM7; - void* pvReservedM6; - void* pfnSVCall_Handler; - void* pfnDebugMonitor_Handler; - void* pvReservedM3; - void* pfnPendSV_Handler; - void* pfnSysTick_Handler; - - /* Peripheral handlers */ - void* pfnPM_Handler; /* 0 Power Manager */ - void* pfnMCLK_Handler; /* 1 Main Clock */ - void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ - void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ - void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ - void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ - void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ - void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ - void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ - void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ - void* pfnWDT_Handler; /* 10 Watchdog Timer */ - void* pfnRTC_Handler; /* 11 Real-Time Counter */ - void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ - void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ - void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ - void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ - void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ - void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ - void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ - void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ - void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ - void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ - void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ - void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ - void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ - void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ - void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ - void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ - void* pfnFREQM_Handler; /* 28 Frequency Meter */ - void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ - void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ - void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ - void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ - void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ - void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ - void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ - void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ - void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ - void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ - void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ - void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ - void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ - void* pvReserved42; - void* pvReserved43; - void* pvReserved44; - void* pfnRAMECC_Handler; /* 45 RAM ECC */ - void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ - void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ - void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ - void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ - void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ - void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ - void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ - void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ - void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ - void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ - void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ - void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ - void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ - void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ - void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ - void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ - void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ - void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ - void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ - void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ - void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ - void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ - void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ - void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ - void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ - void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ - void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ - void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ - void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ - void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ - void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ - void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ - void* pvReserved78; - void* pvReserved79; - void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ - void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ - void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ - void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ - void* pvReserved84; - void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ - void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ - void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ - void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ - void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ - void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ - void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ - void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ - void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ - void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ - void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ - void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ - void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ - void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ - void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ - void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ - void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ - void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ - void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ - void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ - void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ - void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ - void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ - void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ - void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ - void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ - void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ - void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ - void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ - void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ - void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ - void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ - void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ - void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ - void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ - void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ - void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ - void* pfnAC_Handler; /* 122 Analog Comparators */ - void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ - void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ - void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ - void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ - void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ - void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ - void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ - void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ - void* pfnTRNG_Handler; /* 131 True Random Generator */ - void* pfnICM_Handler; /* 132 Integrity Check Monitor */ - void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ - void* pfnQSPI_Handler; /* 134 Quad SPI interface */ - void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ - void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ -} DeviceVectors; - -/* Cortex-M4 processor handlers */ -void Reset_Handler ( void ); -void NonMaskableInt_Handler ( void ); -void HardFault_Handler ( void ); -void MemManagement_Handler ( void ); -void BusFault_Handler ( void ); -void UsageFault_Handler ( void ); -void SVCall_Handler ( void ); -void DebugMonitor_Handler ( void ); -void PendSV_Handler ( void ); -void SysTick_Handler ( void ); - -/* Peripherals handlers */ -void PM_Handler ( void ); -void MCLK_Handler ( void ); -void OSCCTRL_0_Handler ( void ); -void OSCCTRL_1_Handler ( void ); -void OSCCTRL_2_Handler ( void ); -void OSCCTRL_3_Handler ( void ); -void OSCCTRL_4_Handler ( void ); -void OSC32KCTRL_Handler ( void ); -void SUPC_0_Handler ( void ); -void SUPC_1_Handler ( void ); -void WDT_Handler ( void ); -void RTC_Handler ( void ); -void EIC_0_Handler ( void ); -void EIC_1_Handler ( void ); -void EIC_2_Handler ( void ); -void EIC_3_Handler ( void ); -void EIC_4_Handler ( void ); -void EIC_5_Handler ( void ); -void EIC_6_Handler ( void ); -void EIC_7_Handler ( void ); -void EIC_8_Handler ( void ); -void EIC_9_Handler ( void ); -void EIC_10_Handler ( void ); -void EIC_11_Handler ( void ); -void EIC_12_Handler ( void ); -void EIC_13_Handler ( void ); -void EIC_14_Handler ( void ); -void EIC_15_Handler ( void ); -void FREQM_Handler ( void ); -void NVMCTRL_0_Handler ( void ); -void NVMCTRL_1_Handler ( void ); -void DMAC_0_Handler ( void ); -void DMAC_1_Handler ( void ); -void DMAC_2_Handler ( void ); -void DMAC_3_Handler ( void ); -void DMAC_4_Handler ( void ); -void EVSYS_0_Handler ( void ); -void EVSYS_1_Handler ( void ); -void EVSYS_2_Handler ( void ); -void EVSYS_3_Handler ( void ); -void EVSYS_4_Handler ( void ); -void PAC_Handler ( void ); -void RAMECC_Handler ( void ); -void SERCOM0_0_Handler ( void ); -void SERCOM0_1_Handler ( void ); -void SERCOM0_2_Handler ( void ); -void SERCOM0_3_Handler ( void ); -void SERCOM1_0_Handler ( void ); -void SERCOM1_1_Handler ( void ); -void SERCOM1_2_Handler ( void ); -void SERCOM1_3_Handler ( void ); -void SERCOM2_0_Handler ( void ); -void SERCOM2_1_Handler ( void ); -void SERCOM2_2_Handler ( void ); -void SERCOM2_3_Handler ( void ); -void SERCOM3_0_Handler ( void ); -void SERCOM3_1_Handler ( void ); -void SERCOM3_2_Handler ( void ); -void SERCOM3_3_Handler ( void ); -void SERCOM4_0_Handler ( void ); -void SERCOM4_1_Handler ( void ); -void SERCOM4_2_Handler ( void ); -void SERCOM4_3_Handler ( void ); -void SERCOM5_0_Handler ( void ); -void SERCOM5_1_Handler ( void ); -void SERCOM5_2_Handler ( void ); -void SERCOM5_3_Handler ( void ); -void SERCOM6_0_Handler ( void ); -void SERCOM6_1_Handler ( void ); -void SERCOM6_2_Handler ( void ); -void SERCOM6_3_Handler ( void ); -void SERCOM7_0_Handler ( void ); -void SERCOM7_1_Handler ( void ); -void SERCOM7_2_Handler ( void ); -void SERCOM7_3_Handler ( void ); -void USB_0_Handler ( void ); -void USB_1_Handler ( void ); -void USB_2_Handler ( void ); -void USB_3_Handler ( void ); -void TCC0_0_Handler ( void ); -void TCC0_1_Handler ( void ); -void TCC0_2_Handler ( void ); -void TCC0_3_Handler ( void ); -void TCC0_4_Handler ( void ); -void TCC0_5_Handler ( void ); -void TCC0_6_Handler ( void ); -void TCC1_0_Handler ( void ); -void TCC1_1_Handler ( void ); -void TCC1_2_Handler ( void ); -void TCC1_3_Handler ( void ); -void TCC1_4_Handler ( void ); -void TCC2_0_Handler ( void ); -void TCC2_1_Handler ( void ); -void TCC2_2_Handler ( void ); -void TCC2_3_Handler ( void ); -void TCC3_0_Handler ( void ); -void TCC3_1_Handler ( void ); -void TCC3_2_Handler ( void ); -void TCC4_0_Handler ( void ); -void TCC4_1_Handler ( void ); -void TCC4_2_Handler ( void ); -void TC0_Handler ( void ); -void TC1_Handler ( void ); -void TC2_Handler ( void ); -void TC3_Handler ( void ); -void TC4_Handler ( void ); -void TC5_Handler ( void ); -void TC6_Handler ( void ); -void TC7_Handler ( void ); -void PDEC_0_Handler ( void ); -void PDEC_1_Handler ( void ); -void PDEC_2_Handler ( void ); -void ADC0_0_Handler ( void ); -void ADC0_1_Handler ( void ); -void ADC1_0_Handler ( void ); -void ADC1_1_Handler ( void ); -void AC_Handler ( void ); -void DAC_0_Handler ( void ); -void DAC_1_Handler ( void ); -void DAC_2_Handler ( void ); -void DAC_3_Handler ( void ); -void DAC_4_Handler ( void ); -void I2S_Handler ( void ); -void PCC_Handler ( void ); -void AES_Handler ( void ); -void TRNG_Handler ( void ); -void ICM_Handler ( void ); -void PUKCC_Handler ( void ); -void QSPI_Handler ( void ); -void SDHC0_Handler ( void ); -void SDHC1_Handler ( void ); - -/* - * \brief Configuration of the Cortex-M4 Processor and Core Peripherals - */ - -#define __CM4_REV 1 /*!< Core revision r0p1 */ -#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ -#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ -#define __VTOR_PRESENT 1 /*!< VTOR present or not */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/** - * \brief CMSIS includes - */ - -#include -#if !defined DONT_USE_CMSIS_INIT -#include "system_samd51.h" -#endif /* DONT_USE_CMSIS_INIT */ - -/*@}*/ - -/* ************************************************************************** */ -/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_api Peripheral Software API */ -/*@{*/ - -#include "component/ac.h" -#include "component/adc.h" -#include "component/aes.h" -#include "component/ccl.h" -#include "component/cmcc.h" -#include "component/dac.h" -#include "component/dmac.h" -#include "component/dsu.h" -#include "component/eic.h" -#include "component/evsys.h" -#include "component/freqm.h" -#include "component/gclk.h" -#include "component/hmatrixb.h" -#include "component/icm.h" -#include "component/i2s.h" -#include "component/mclk.h" -#include "component/nvmctrl.h" -#include "component/oscctrl.h" -#include "component/osc32kctrl.h" -#include "component/pac.h" -#include "component/pcc.h" -#include "component/pdec.h" -#include "component/pm.h" -#include "component/port.h" -#include "component/qspi.h" -#include "component/ramecc.h" -#include "component/rstc.h" -#include "component/rtc.h" -#include "component/sdhc.h" -#include "component/sercom.h" -#include "component/supc.h" -#include "component/tc.h" -#include "component/tcc.h" -#include "component/trng.h" -#include "component/usb.h" -#include "component/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_reg Registers Access Definitions */ -/*@{*/ - -#include "instance/ac.h" -#include "instance/adc0.h" -#include "instance/adc1.h" -#include "instance/aes.h" -#include "instance/ccl.h" -#include "instance/cmcc.h" -#include "instance/dac.h" -#include "instance/dmac.h" -#include "instance/dsu.h" -#include "instance/eic.h" -#include "instance/evsys.h" -#include "instance/freqm.h" -#include "instance/gclk.h" -#include "instance/hmatrix.h" -#include "instance/icm.h" -#include "instance/i2s.h" -#include "instance/mclk.h" -#include "instance/nvmctrl.h" -#include "instance/oscctrl.h" -#include "instance/osc32kctrl.h" -#include "instance/pac.h" -#include "instance/pcc.h" -#include "instance/pdec.h" -#include "instance/pm.h" -#include "instance/port.h" -#include "instance/pukcc.h" -#include "instance/qspi.h" -#include "instance/ramecc.h" -#include "instance/rstc.h" -#include "instance/rtc.h" -#include "instance/sdhc0.h" -#include "instance/sdhc1.h" -#include "instance/sercom0.h" -#include "instance/sercom1.h" -#include "instance/sercom2.h" -#include "instance/sercom3.h" -#include "instance/sercom4.h" -#include "instance/sercom5.h" -#include "instance/sercom6.h" -#include "instance/sercom7.h" -#include "instance/supc.h" -#include "instance/tc0.h" -#include "instance/tc1.h" -#include "instance/tc2.h" -#include "instance/tc3.h" -#include "instance/tc4.h" -#include "instance/tc5.h" -#include "instance/tc6.h" -#include "instance/tc7.h" -#include "instance/tcc0.h" -#include "instance/tcc1.h" -#include "instance/tcc2.h" -#include "instance/tcc3.h" -#include "instance/tcc4.h" -#include "instance/trng.h" -#include "instance/usb.h" -#include "instance/wdt.h" -/*@}*/ - -/* ************************************************************************** */ -/** PERIPHERAL ID DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_id Peripheral Ids Definitions */ -/*@{*/ - -// Peripheral instances on HPB0 bridge -#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ -#define ID_PM 1 /**< \brief Power Manager (PM) */ -#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ -#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ -#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ -#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ -#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ -#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ -#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ -#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ -#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ -#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ -#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ -#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ -#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ -#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ - -// Peripheral instances on HPB1 bridge -#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ -#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ -#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ -#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ -#define ID_PORT 36 /**< \brief Port Module (PORT) */ -#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ -#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ -#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ -#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ -#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ -#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ -#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ -#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ -#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ -#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ - -// Peripheral instances on HPB2 bridge -#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ -#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ -#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ -#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ -#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ -#define ID_AC 72 /**< \brief Analog Comparators (AC) */ -#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ -#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ -#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ -#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ -#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ -#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ - -// Peripheral instances on HPB3 bridge -#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ -#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ -#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ -#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ -#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ -#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ -#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ -#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ -#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ -#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ -#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ -#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ - -// Peripheral instances on AHB (as if on bridge 4) -#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ -#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ - -#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ -/*@}*/ - -/* ************************************************************************** */ -/** BASE ADDRESS DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_base Peripheral Base Address Definitions */ -/*@{*/ - -#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) -#define AC (0x42002000) /**< \brief (AC) APB Base Address */ -#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ -#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ -#define AES (0x42002400) /**< \brief (AES) APB Base Address */ -#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ -#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ -#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ -#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ -#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ -#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ -#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ -#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ -#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ -#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ -#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ -#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ -#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ -#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ -#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ -#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ -#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ -#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ -#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ -#define PM (0x40000400) /**< \brief (PM) APB Base Address */ -#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ -#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ -#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ -#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ -#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ -#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ -#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ -#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ -#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ -#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ -#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ -#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ -#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ -#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ -#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ -#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ -#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ -#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ -#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ -#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ -#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ -#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ -#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ -#define USB (0x41000000) /**< \brief (USB) APB Base Address */ -#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ -#else -#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ -#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ -#define AC_INSTS { AC } /**< \brief (AC) Instances List */ - -#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ -#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ -#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ -#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ - -#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ -#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ -#define AES_INSTS { AES } /**< \brief (AES) Instances List */ - -#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ -#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ -#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ - -#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ -#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ -#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ -#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ - -#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ -#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ -#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ - -#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ -#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ -#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ - -#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ -#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ -#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ - -#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ -#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ -#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ - -#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ -#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ -#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ - -#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ -#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ -#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ - -#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ -#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ -#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ - -#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ -#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ -#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ - -#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ -#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ -#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ - -#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ -#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ -#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ - -#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ -#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ -#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ - -#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ -#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ -#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ -#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ -#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ -#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ - -#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ -#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ -#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ - -#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ -#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ -#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ - -#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ -#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ -#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ - -#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ -#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ -#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ - -#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ -#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ -#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ - -#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ -#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ -#define PM_INSTS { PM } /**< \brief (PM) Instances List */ - -#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ -#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ -#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ - -#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ -#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ -#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ -#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ - -#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ -#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ -#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ -#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ - -#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ -#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ -#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ - -#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ -#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ -#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ - -#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ -#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ -#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ - -#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ -#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ -#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ -#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ - -#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ -#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ -#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ -#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ -#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ -#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ -#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ -#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ -#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ -#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ - -#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ -#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ -#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ - -#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ -#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ -#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ -#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ -#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ -#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ -#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ -#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ -#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ -#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ - -#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ -#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ -#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ -#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ -#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ -#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ -#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ - -#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ -#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ -#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ - -#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ -#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ -#define USB_INSTS { USB } /**< \brief (USB) Instances List */ - -#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ -#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ -#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ - -#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ -/*@}*/ - -/* ************************************************************************** */ -/** PORT DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ -/** \defgroup SAMD51P20A_port PORT Definitions */ -/*@{*/ - -#include "pio/samd51p20a.h" -/*@}*/ - -/* ************************************************************************** */ -/** MEMORY MAPPING DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ - -#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ -#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ -#define FLASH_PAGE_SIZE 512 -#define FLASH_NB_OF_PAGES 2048 -#define FLASH_USER_PAGE_SIZE 512 -#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ -#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ - -#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ -#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ -#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ -#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ -#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ -#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ -#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ -#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ -#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ -#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ -#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ -#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ -#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ -#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ -#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ -#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ -#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ -#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ -#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ - -#define DSU_DID_RESETVALUE _UL_(0x60060300) -#define ADC0_TOUCH_LINES_NUM 32 -#define PORT_GROUPS 4 - -/* ************************************************************************** */ -/** ELECTRICAL DEFINITIONS FOR SAMD51P20A */ -/* ************************************************************************** */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ - -#endif /* SAMD51P20A_H */ +/** + * \file + * + * \brief Header file for SAMD51P20A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAMD51P20A_ +#define _SAMD51P20A_ + +/** + * \ingroup SAMD51_definitions + * \addtogroup SAMD51P20A_definitions SAMD51P20A definitions + * This file defines all structures and symbols for SAMD51P20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAMD51P20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAMD51P20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAMD51P20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY */ + OSCCTRL_3_IRQn = 5, /**< 5 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAMD51P20A Oscillators Control (OSCCTRL): OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAMD51P20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAMD51P20A Supply Controller (SUPC): SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY */ + SUPC_1_IRQn = 9, /**< 9 SAMD51P20A Supply Controller (SUPC): SUPC_BOD12DET, SUPC_BOD33DET */ + WDT_IRQn = 10, /**< 10 SAMD51P20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAMD51P20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_0 */ + EIC_1_IRQn = 13, /**< 13 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_1 */ + EIC_2_IRQn = 14, /**< 14 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_2 */ + EIC_3_IRQn = 15, /**< 15 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_3 */ + EIC_4_IRQn = 16, /**< 16 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_4 */ + EIC_5_IRQn = 17, /**< 17 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_5 */ + EIC_6_IRQn = 18, /**< 18 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_6 */ + EIC_7_IRQn = 19, /**< 19 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_7 */ + EIC_8_IRQn = 20, /**< 20 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_8 */ + EIC_9_IRQn = 21, /**< 21 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_9 */ + EIC_10_IRQn = 22, /**< 22 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_10 */ + EIC_11_IRQn = 23, /**< 23 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_11 */ + EIC_12_IRQn = 24, /**< 24 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_12 */ + EIC_13_IRQn = 25, /**< 25 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_13 */ + EIC_14_IRQn = 26, /**< 26 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_14 */ + EIC_15_IRQn = 27, /**< 27 SAMD51P20A External Interrupt Controller (EIC): EIC_EXTINT_15 */ + FREQM_IRQn = 28, /**< 28 SAMD51P20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAMD51P20A Non-Volatile Memory Controller (NVMCTRL): NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + DMAC_0_IRQn = 31, /**< 31 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + DMAC_1_IRQn = 32, /**< 32 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + DMAC_2_IRQn = 33, /**< 33 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + DMAC_3_IRQn = 34, /**< 34 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + DMAC_4_IRQn = 35, /**< 35 SAMD51P20A Direct Memory Access Controller (DMAC): DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + EVSYS_0_IRQn = 36, /**< 36 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_0, EVSYS_OVR_0 */ + EVSYS_1_IRQn = 37, /**< 37 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_1, EVSYS_OVR_1 */ + EVSYS_2_IRQn = 38, /**< 38 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_2, EVSYS_OVR_2 */ + EVSYS_3_IRQn = 39, /**< 39 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_3, EVSYS_OVR_3 */ + EVSYS_4_IRQn = 40, /**< 40 SAMD51P20A Event System Interface (EVSYS): EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + PAC_IRQn = 41, /**< 41 SAMD51P20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAMD51P20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAMD51P20A Serial Communication Interface 0 (SERCOM0): SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + SERCOM1_0_IRQn = 50, /**< 50 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAMD51P20A Serial Communication Interface 1 (SERCOM1): SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + SERCOM2_0_IRQn = 54, /**< 54 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAMD51P20A Serial Communication Interface 2 (SERCOM2): SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + SERCOM3_0_IRQn = 58, /**< 58 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAMD51P20A Serial Communication Interface 3 (SERCOM3): SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ + SERCOM4_0_IRQn = 62, /**< 62 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAMD51P20A Serial Communication Interface 4 (SERCOM4): SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ + SERCOM5_0_IRQn = 66, /**< 66 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAMD51P20A Serial Communication Interface 5 (SERCOM5): SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ + SERCOM6_0_IRQn = 70, /**< 70 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAMD51P20A Serial Communication Interface 6 (SERCOM6): SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ + SERCOM7_0_IRQn = 74, /**< 74 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAMD51P20A Serial Communication Interface 7 (SERCOM7): SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ + USB_0_IRQn = 80, /**< 80 SAMD51P20A Universal Serial Bus (USB): USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + USB_1_IRQn = 81, /**< 81 SAMD51P20A Universal Serial Bus (USB): USB_SOF_HSOF */ + USB_2_IRQn = 82, /**< 82 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + USB_3_IRQn = 83, /**< 83 SAMD51P20A Universal Serial Bus (USB): USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ + TCC0_0_IRQn = 85, /**< 85 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + TCC0_1_IRQn = 86, /**< 86 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_0 */ + TCC0_2_IRQn = 87, /**< 87 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_1 */ + TCC0_3_IRQn = 88, /**< 88 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_2 */ + TCC0_4_IRQn = 89, /**< 89 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_3 */ + TCC0_5_IRQn = 90, /**< 90 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_4 */ + TCC0_6_IRQn = 91, /**< 91 SAMD51P20A Timer Counter Control 0 (TCC0): TCC0_MC_5 */ + TCC1_0_IRQn = 92, /**< 92 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + TCC1_1_IRQn = 93, /**< 93 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_0 */ + TCC1_2_IRQn = 94, /**< 94 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_1 */ + TCC1_3_IRQn = 95, /**< 95 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_2 */ + TCC1_4_IRQn = 96, /**< 96 SAMD51P20A Timer Counter Control 1 (TCC1): TCC1_MC_3 */ + TCC2_0_IRQn = 97, /**< 97 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + TCC2_1_IRQn = 98, /**< 98 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_0 */ + TCC2_2_IRQn = 99, /**< 99 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_1 */ + TCC2_3_IRQn = 100, /**< 100 SAMD51P20A Timer Counter Control 2 (TCC2): TCC2_MC_2 */ + TCC3_0_IRQn = 101, /**< 101 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + TCC3_1_IRQn = 102, /**< 102 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_0 */ + TCC3_2_IRQn = 103, /**< 103 SAMD51P20A Timer Counter Control 3 (TCC3): TCC3_MC_1 */ + TCC4_0_IRQn = 104, /**< 104 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + TCC4_1_IRQn = 105, /**< 105 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_0 */ + TCC4_2_IRQn = 106, /**< 106 SAMD51P20A Timer Counter Control 4 (TCC4): TCC4_MC_1 */ + TC0_IRQn = 107, /**< 107 SAMD51P20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAMD51P20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAMD51P20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAMD51P20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAMD51P20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAMD51P20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAMD51P20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAMD51P20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + PDEC_1_IRQn = 116, /**< 116 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_0 */ + PDEC_2_IRQn = 117, /**< 117 SAMD51P20A Quadrature Decodeur (PDEC): PDEC_MC_1 */ + ADC0_0_IRQn = 118, /**< 118 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_OVERRUN, ADC0_WINMON */ + ADC0_1_IRQn = 119, /**< 119 SAMD51P20A Analog Digital Converter 0 (ADC0): ADC0_RESRDY */ + ADC1_0_IRQn = 120, /**< 120 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_OVERRUN, ADC1_WINMON */ + ADC1_1_IRQn = 121, /**< 121 SAMD51P20A Analog Digital Converter 1 (ADC1): ADC1_RESRDY */ + AC_IRQn = 122, /**< 122 SAMD51P20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + DAC_1_IRQn = 124, /**< 124 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_0 */ + DAC_2_IRQn = 125, /**< 125 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_EMPTY_1 */ + DAC_3_IRQn = 126, /**< 126 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_0 */ + DAC_4_IRQn = 127, /**< 127 SAMD51P20A Digital-to-Analog Converter (DAC): DAC_RESRDY_1 */ + I2S_IRQn = 128, /**< 128 SAMD51P20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAMD51P20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAMD51P20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAMD51P20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAMD51P20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAMD51P20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAMD51P20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAMD51P20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAMD51P20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pvReserved78; + void* pvReserved79; + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pvReserved84; + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samd51.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ +/** \defgroup SAMD51P20A_port PORT Definitions */ +/*@{*/ + +#include "pio/samd51p20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x60060300) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAMD51P20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAMD51P20A_H */ diff --git a/lib/samd51/samd51a/include/system_samd51.h b/lib/samd51/samd51a/include/system_samd51.h index dcb8564..1f6123d 100644 --- a/lib/samd51/samd51a/include/system_samd51.h +++ b/lib/samd51/samd51a/include/system_samd51.h @@ -1,48 +1,48 @@ -/** - * \file - * - * \brief Low-level initialization functions called upon chip startup - * - * Copyright (c) 2018 Microchip Technology Inc. - * - * \asf_license_start - * - * \page License - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the Licence at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * \asf_license_stop - * - */ - -#ifndef _SYSTEM_SAMD51_H_INCLUDED_ -#define _SYSTEM_SAMD51_H_INCLUDED_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -void SystemInit(void); -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_SAMD51_H_INCLUDED */ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAMD51_H_INCLUDED_ +#define _SYSTEM_SAMD51_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAMD51_H_INCLUDED */ diff --git a/out/autoconf.h b/out/autoconf.h deleted file mode 100644 index 060e648..0000000 --- a/out/autoconf.h +++ /dev/null @@ -1,208 +0,0 @@ -#define CONFIG_LOW_LEVEL_OPTIONS 0 -#define CONFIG_MACH_AVR 0 -#define CONFIG_MACH_ATSAM 0 -#define CONFIG_MACH_ATSAMD 0 -#define CONFIG_MACH_LPC176X 0 -#define CONFIG_MACH_STM32 0 -#define CONFIG_MACH_RP2040 0 -#define CONFIG_MACH_PRU 0 -#define CONFIG_MACH_LINUX 1 -#define CONFIG_MACH_SIMU 0 -#define CONFIG_AVR_SELECT 0 -#define CONFIG_BOARD_DIRECTORY "linux" -#define CONFIG_MACH_atmega2560 0 -#define CONFIG_MACH_atmega1280 0 -#define CONFIG_MACH_at90usb1286 0 -#define CONFIG_MACH_at90usb646 0 -#define CONFIG_MACH_atmega32u4 0 -#define CONFIG_MACH_atmega1284p 0 -#define CONFIG_MACH_atmega644p 0 -#define CONFIG_MACH_atmega328p 0 -#define CONFIG_MACH_atmega328 0 -#define CONFIG_MACH_atmega168 0 -#define CONFIG_MCU "" -#define CONFIG_AVRDUDE_PROTOCOL "" -#define CONFIG_AVR_FREQ_16000000 0 -#define CONFIG_AVR_FREQ_20000000 0 -#define CONFIG_AVR_FREQ_8000000 0 -#define CONFIG_CLOCK_FREQ 50000000 -#define CONFIG_CLEAR_PRESCALER 0 -#define CONFIG_AVR_CLKPR 0 -#define CONFIG_AVR_STACK_SIZE 0 -#define CONFIG_AVR_WATCHDOG 0 -#define CONFIG_USBSERIAL 0 -#define CONFIG_SERIAL 0 -#define CONFIG_AVR_USB 0 -#define CONFIG_AVR_SERIAL_UART0 0 -#define CONFIG_AVR_SERIAL_UART1 0 -#define CONFIG_AVR_SERIAL_UART2 0 -#define CONFIG_AVR_SERIAL_UART3 0 -#define CONFIG_SERIAL_BAUD_U2X 0 -#define CONFIG_SERIAL_PORT 0 -#define CONFIG_SIMULAVR 0 -#define CONFIG_ATSAM_SELECT 0 -#define CONFIG_MACH_SAM3X8E 0 -#define CONFIG_MACH_SAM3X8C 0 -#define CONFIG_MACH_SAM4S8C 0 -#define CONFIG_MACH_SAM4E8E 0 -#define CONFIG_MACH_SAME70Q20B 0 -#define CONFIG_MACH_SAM3X 0 -#define CONFIG_MACH_SAM4 0 -#define CONFIG_MACH_SAM4S 0 -#define CONFIG_MACH_SAM4E 0 -#define CONFIG_MACH_SAME70 0 -#define CONFIG_FLASH_START 0x -#define CONFIG_FLASH_SIZE 0x -#define CONFIG_RAM_START 0x -#define CONFIG_RAM_SIZE 0x -#define CONFIG_STACK_SIZE 0 -#define CONFIG_ATSAM_USB 0 -#define CONFIG_ATSAM_SERIAL 0 -#define CONFIG_ATSAMD_SELECT 0 -#define CONFIG_HAVE_SERCOM 0 -#define CONFIG_MACH_SAMD21G18 0 -#define CONFIG_MACH_SAMD21E18 0 -#define CONFIG_MACH_SAMD21E15 0 -#define CONFIG_MACH_SAMD51G19 0 -#define CONFIG_MACH_SAMD51J19 0 -#define CONFIG_MACH_SAMD51N19 0 -#define CONFIG_MACH_SAMD51P20 0 -#define CONFIG_MACH_SAMD21 0 -#define CONFIG_MACH_SAMD51 0 -#define CONFIG_CLOCK_REF_X32K 0 -#define CONFIG_CLOCK_REF_X25M 0 -#define CONFIG_CLOCK_REF_INTERNAL 0 -#define CONFIG_SAMD51_FREQ_120 0 -#define CONFIG_SAMD51_FREQ_150 0 -#define CONFIG_SAMD51_FREQ_180 0 -#define CONFIG_SAMD51_FREQ_200 0 -#define CONFIG_FLASH_START_2000 0 -#define CONFIG_FLASH_START_4000 0 -#define CONFIG_FLASH_START_0000 0 -#define CONFIG_ATSAMD_USB 0 -#define CONFIG_ATSAMD_SERIAL 0 -#define CONFIG_LPC_SELECT 0 -#define CONFIG_MACH_LPC1768 0 -#define CONFIG_MACH_LPC1769 0 -#define CONFIG_SMOOTHIEWARE_BOOTLOADER 0 -#define CONFIG_LPC_USB 0 -#define CONFIG_LPC_SERIAL_UART0_P03_P02 0 -#define CONFIG_LPC_SERIAL_UART3_P429_P428 0 -#define CONFIG_STM32_SELECT 0 -#define CONFIG_MACH_STM32F103 0 -#define CONFIG_MACH_STM32F207 0 -#define CONFIG_MACH_STM32F401 0 -#define CONFIG_MACH_STM32F405 0 -#define CONFIG_MACH_STM32F407 0 -#define CONFIG_MACH_STM32F429 0 -#define CONFIG_MACH_STM32F446 0 -#define CONFIG_MACH_STM32F031 0 -#define CONFIG_MACH_STM32F042 0 -#define CONFIG_MACH_STM32F070 0 -#define CONFIG_MACH_STM32F072 0 -#define CONFIG_MACH_STM32G0B1 0 -#define CONFIG_MACH_STM32H743 0 -#define CONFIG_MACH_STM32H750 0 -#define CONFIG_MACH_STM32F103x6 0 -#define CONFIG_MACH_STM32F0 0 -#define CONFIG_MACH_STM32F1 0 -#define CONFIG_MACH_STM32F2 0 -#define CONFIG_MACH_STM32F4 0 -#define CONFIG_MACH_STM32G0 0 -#define CONFIG_MACH_STM32H7 0 -#define CONFIG_MACH_STM32F0x2 0 -#define CONFIG_MACH_STM32F4x5 0 -#define CONFIG_HAVE_STM32_USBFS 0 -#define CONFIG_HAVE_STM32_USBOTG 0 -#define CONFIG_HAVE_STM32_CANBUS 0 -#define CONFIG_HAVE_STM32_FDCANBUS 0 -#define CONFIG_HAVE_STM32_USBCANBUS 0 -#define CONFIG_STM32F103GD_DISABLE_SWD 0 -#define CONFIG_STM32_FLASH_START_2000 0 -#define CONFIG_STM32_FLASH_START_5000 0 -#define CONFIG_STM32_FLASH_START_7000 0 -#define CONFIG_STM32_FLASH_START_8000 0 -#define CONFIG_STM32_FLASH_START_8800 0 -#define CONFIG_STM32_FLASH_START_20200 0 -#define CONFIG_STM32_FLASH_START_C000 0 -#define CONFIG_STM32_FLASH_START_10000 0 -#define CONFIG_STM32_FLASH_START_800 0 -#define CONFIG_STM32_FLASH_START_1000 0 -#define CONFIG_STM32_FLASH_START_4000 0 -#define CONFIG_STM32_FLASH_START_20000 0 -#define CONFIG_STM32_FLASH_START_0000 0 -#define CONFIG_ARMCM_RAM_VECTORTABLE 0 -#define CONFIG_STM32_CLOCK_REF_8M 0 -#define CONFIG_STM32_CLOCK_REF_12M 0 -#define CONFIG_STM32_CLOCK_REF_16M 0 -#define CONFIG_STM32_CLOCK_REF_25M 0 -#define CONFIG_STM32_CLOCK_REF_INTERNAL 0 -#define CONFIG_CLOCK_REF_FREQ 0 -#define CONFIG_STM32F0_TRIM 0 -#define CONFIG_STM32_USB_PA11_PA12 0 -#define CONFIG_STM32_USB_PA11_PA12_REMAP 0 -#define CONFIG_STM32_USB_PB14_PB15 0 -#define CONFIG_STM32_SERIAL_USART1 0 -#define CONFIG_STM32_SERIAL_USART1_ALT_PB7_PB6 0 -#define CONFIG_STM32_SERIAL_USART2 0 -#define CONFIG_STM32_SERIAL_USART2_ALT_PA15_PA14 0 -#define CONFIG_STM32_SERIAL_USART2_ALT_PD6_PD5 0 -#define CONFIG_STM32_SERIAL_USART3 0 -#define CONFIG_STM32_SERIAL_USART3_ALT_PD9_PD8 0 -#define CONFIG_STM32_SERIAL_UART4 0 -#define CONFIG_STM32_CANBUS_PA11_PA12 0 -#define CONFIG_STM32_CANBUS_PA11_PA12_REMAP 0 -#define CONFIG_STM32_MMENU_CANBUS_PB8_PB9 0 -#define CONFIG_STM32_MMENU_CANBUS_PI9_PH13 0 -#define CONFIG_STM32_MMENU_CANBUS_PB5_PB6 0 -#define CONFIG_STM32_MMENU_CANBUS_PB12_PB13 0 -#define CONFIG_STM32_MMENU_CANBUS_PD0_PD1 0 -#define CONFIG_STM32_MMENU_CANBUS_PB0_PB1 0 -#define CONFIG_STM32_USBCANBUS_PA11_PA12 0 -#define CONFIG_STM32_CMENU_CANBUS_PB8_PB9 0 -#define CONFIG_STM32_CMENU_CANBUS_PI9_PH13 0 -#define CONFIG_STM32_CMENU_CANBUS_PB5_PB6 0 -#define CONFIG_STM32_CMENU_CANBUS_PB12_PB13 0 -#define CONFIG_STM32_CMENU_CANBUS_PD0_PD1 0 -#define CONFIG_STM32_CMENU_CANBUS_PB0_PB1 0 -#define CONFIG_STM32_CANBUS_PB8_PB9 0 -#define CONFIG_STM32_CANBUS_PI9_PH13 0 -#define CONFIG_STM32_CANBUS_PB5_PB6 0 -#define CONFIG_STM32_CANBUS_PB12_PB13 0 -#define CONFIG_STM32_CANBUS_PD0_PD1 0 -#define CONFIG_STM32_CANBUS_PB0_PB1 0 -#define CONFIG_RP2040_SELECT 0 -#define CONFIG_RP2040_FLASH_W25Q080 0 -#define CONFIG_RP2040_FLASH_GENERIC_03 0 -#define CONFIG_RP2040_STAGE2_FILE "" -#define CONFIG_RP2040_STAGE2_CLKDIV 0 -#define CONFIG_RP2040_USB 0 -#define CONFIG_RP2040_SERIAL_UART0 0 -#define CONFIG_RP2040_CANBUS 0 -#define CONFIG_RP2040_USBCANBUS 0 -#define CONFIG_RP2040_CANBUS_GPIO_RX 0 -#define CONFIG_RP2040_CANBUS_GPIO_TX 0 -#define CONFIG_PRU_SELECT 0 -#define CONFIG_LINUX_SELECT 1 -#define CONFIG_SIMULATOR_SELECT 0 -#define CONFIG_SERIAL_BAUD 0 -#define CONFIG_USBCANBUS 0 -#define CONFIG_USB_VENDOR_ID 0x1d50 -#define CONFIG_USB_DEVICE_ID 0x614e -#define CONFIG_USB_SERIAL_NUMBER_CHIPID 0 -#define CONFIG_USB_SERIAL_NUMBER "12345" -#define CONFIG_CANSERIAL 0 -#define CONFIG_CANBUS 0 -#define CONFIG_CANBUS_FREQUENCY 500000 -#define CONFIG_CANBUS_FILTER 0 -#define CONFIG_INITIAL_PINS "" -#define CONFIG_HAVE_GPIO 1 -#define CONFIG_HAVE_GPIO_ADC 1 -#define CONFIG_HAVE_GPIO_SPI 1 -#define CONFIG_HAVE_GPIO_I2C 1 -#define CONFIG_HAVE_GPIO_HARD_PWM 1 -#define CONFIG_HAVE_GPIO_BITBANGING 1 -#define CONFIG_HAVE_STRICT_TIMING 0 -#define CONFIG_HAVE_CHIPID 0 -#define CONFIG_HAVE_STEPPER_BOTH_EDGE 0 -#define CONFIG_INLINE_STEPPER_HACK 1 diff --git a/out/board-link b/out/board-link deleted file mode 100644 index 7c13d22..0000000 --- a/out/board-link +++ /dev/null @@ -1 +0,0 @@ -# Makefile board-link rule diff --git a/out/compile_time_request.c b/out/compile_time_request.c deleted file mode 100644 index b686301..0000000 --- a/out/compile_time_request.c +++ /dev/null @@ -1,1747 +0,0 @@ - -/* DO NOT EDIT! This is an autogenerated file. See scripts/buildcommands.py. */ - -#include "board/irq.h" -#include "board/pgm.h" -#include "command.h" -#include "compiler.h" -#include "initial_pins.h" - -void -ctr_run_initfuncs(void) -{ - extern void alloc_init(void); - alloc_init(); - extern void initial_pins_setup(void); - initial_pins_setup(); - extern void timer_init(void); - timer_init(); -} - -void -ctr_run_shutdownfuncs(void) -{ - extern void sendf_shutdown(void); - sendf_shutdown(); - extern void move_reset(void); - move_reset(); - extern void digital_out_shutdown(void); - digital_out_shutdown(); - extern void stepper_shutdown(void); - stepper_shutdown(); - extern void trsync_shutdown(void); - trsync_shutdown(); - extern void analog_in_shutdown(void); - analog_in_shutdown(); - extern void spidev_shutdown(void); - spidev_shutdown(); - extern void pwm_shutdown(void); - pwm_shutdown(); - extern void st7920_shutdown(void); - st7920_shutdown(); - extern void hd44780_shutdown(void); - hd44780_shutdown(); - extern void tmcuart_shutdown(void); - tmcuart_shutdown(); - extern void pca9685_shutdown(void); - pca9685_shutdown(); -} - -void -ctr_run_taskfuncs(void) -{ - irq_poll(); - extern void trsync_task(void); - trsync_task(); - irq_poll(); - extern void analog_in_task(void); - analog_in_task(); - irq_poll(); - extern void thermocouple_task(void); - thermocouple_task(); - irq_poll(); - extern void adxl345_task(void); - adxl345_task(); - irq_poll(); - extern void spi_angle_task(void); - spi_angle_task(); - irq_poll(); - extern void mpu9250_task(void); - mpu9250_task(); - irq_poll(); - extern void buttons_task(void); - buttons_task(); - irq_poll(); - extern void tmcuart_task(void); - tmcuart_task(); - irq_poll(); - extern void counter_task(void); - counter_task(); - irq_poll(); - extern void console_task(void); - console_task(); - irq_poll(); - extern void watchdog_task(void); - watchdog_task(); - irq_poll(); - extern void ds18_task(void); - ds18_task(); - irq_poll(); -} - -uint8_t __always_inline -ctr_lookup_static_string(const char *str) -{ - if (__builtin_strcmp(str, "Shutdown cleared when not shutdown") == 0) - return 2; - if (__builtin_strcmp(str, "Timer too close") == 0) - return 3; - if (__builtin_strcmp(str, "sentinel timer called") == 0) - return 4; - if (__builtin_strcmp(str, "Invalid command") == 0) - return 5; - if (__builtin_strcmp(str, "Message encode error") == 0) - return 6; - if (__builtin_strcmp(str, "Command parser error") == 0) - return 7; - if (__builtin_strcmp(str, "Command request") == 0) - return 8; - if (__builtin_strcmp(str, "config_reset only available when shutdown") == 0) - return 9; - if (__builtin_strcmp(str, "oids already allocated") == 0) - return 10; - if (__builtin_strcmp(str, "Can't assign oid") == 0) - return 11; - if (__builtin_strcmp(str, "Invalid oid type") == 0) - return 12; - if (__builtin_strcmp(str, "Already finalized") == 0) - return 13; - if (__builtin_strcmp(str, "Invalid move request size") == 0) - return 14; - if (__builtin_strcmp(str, "Move queue overflow") == 0) - return 15; - if (__builtin_strcmp(str, "alloc_chunks failed") == 0) - return 16; - if (__builtin_strcmp(str, "alloc_chunk failed") == 0) - return 17; - if (__builtin_strcmp(str, "update_digital_out not valid with active queue") == 0) - return 18; - if (__builtin_strcmp(str, "Scheduled digital out event will exceed max_duration") == 0) - return 19; - if (__builtin_strcmp(str, "Can not set soft pwm cycle ticks while updates pending") == 0) - return 20; - if (__builtin_strcmp(str, "Missed scheduling of next digital out event") == 0) - return 21; - if (__builtin_strcmp(str, "Can't reset time when stepper active") == 0) - return 22; - if (__builtin_strcmp(str, "Invalid count parameter") == 0) - return 23; - if (__builtin_strcmp(str, "Stepper too far in past") == 0) - return 24; - if (__builtin_strcmp(str, "Can't add signal that is already active") == 0) - return 25; - if (__builtin_strcmp(str, "ADC out of range") == 0) - return 26; - if (__builtin_strcmp(str, "Invalid spi config") == 0) - return 27; - if (__builtin_strcmp(str, "Thermocouple reader fault") == 0) - return 28; - if (__builtin_strcmp(str, "Thermocouple ADC out of range") == 0) - return 29; - if (__builtin_strcmp(str, "Invalid thermocouple chip type") == 0) - return 30; - if (__builtin_strcmp(str, "i2c_modify_bits: Odd number of bits!") == 0) - return 31; - if (__builtin_strcmp(str, "Scheduled pwm event will exceed max_duration") == 0) - return 32; - if (__builtin_strcmp(str, "Missed scheduling of next hard pwm event") == 0) - return 33; - if (__builtin_strcmp(str, "angle sensor requires cs pin") == 0) - return 34; - if (__builtin_strcmp(str, "Invalid spi_angle chip type") == 0) - return 35; - if (__builtin_strcmp(str, "Invalid buttons retransmit count") == 0) - return 36; - if (__builtin_strcmp(str, "Set button past maximum button count") == 0) - return 37; - if (__builtin_strcmp(str, "Max of 8 buttons") == 0) - return 38; - if (__builtin_strcmp(str, "tmcuart data too large") == 0) - return 39; - if (__builtin_strcmp(str, "Invalid neopixel update command") == 0) - return 40; - if (__builtin_strcmp(str, "Invalid neopixel data_size") == 0) - return 41; - if (__builtin_strcmp(str, "Rescheduled timer in the past") == 0) - return 42; - if (__builtin_strcmp(str, "Force shutdown command") == 0) - return 43; - if (__builtin_strcmp(str, "Invalid pca9685 channel or value") == 0) - return 44; - if (__builtin_strcmp(str, "Scheduled pca9685 event will exceed max_duration") == 0) - return 45; - if (__builtin_strcmp(str, "Invalid pca9685 value") == 0) - return 46; - if (__builtin_strcmp(str, "Missed scheduling of next pca9685 event") == 0) - return 47; - if (__builtin_strcmp(str, "Unable to open and init PCA9685 device") == 0) - return 48; - if (__builtin_strcmp(str, "Too many i2c devices") == 0) - return 49; - if (__builtin_strcmp(str, "All PCA9685 channels must have the same cycle_ticks") == 0) - return 50; - if (__builtin_strcmp(str, "Unable to update PCA9685 value") == 0) - return 51; - if (__builtin_strcmp(str, "Unable to write to spi") == 0) - return 52; - if (__builtin_strcmp(str, "Unable to issue spi ioctl") == 0) - return 53; - if (__builtin_strcmp(str, "Unable to set SPI mode") == 0) - return 54; - if (__builtin_strcmp(str, "Unable to set SPI speed") == 0) - return 55; - if (__builtin_strcmp(str, "Unable to set non-blocking on spi device") == 0) - return 56; - if (__builtin_strcmp(str, "Unable to open spi device") == 0) - return 57; - if (__builtin_strcmp(str, "Too many spi devices") == 0) - return 58; - if (__builtin_strcmp(str, "Error on analog read") == 0) - return 59; - if (__builtin_strcmp(str, "Unable to open adc device") == 0) - return 60; - if (__builtin_strcmp(str, "Unable to config pwm device") == 0) - return 61; - if (__builtin_strcmp(str, "Unable to read i2c device") == 0) - return 62; - if (__builtin_strcmp(str, "Unable write i2c device") == 0) - return 63; - if (__builtin_strcmp(str, "Unable to open i2c device") == 0) - return 64; - if (__builtin_strcmp(str, "Unable to open in GPIO chip line") == 0) - return 65; - if (__builtin_strcmp(str, "Unable to open out GPIO chip line") == 0) - return 66; - if (__builtin_strcmp(str, "Unable to open GPIO chip device") == 0) - return 67; - if (__builtin_strcmp(str, "GPIO chip device not found") == 0) - return 68; - if (__builtin_strcmp(str, "DS18B20 sensor didn't respond in time") == 0) - return 69; - if (__builtin_strcmp(str, "DS18B20 out of range") == 0) - return 70; - if (__builtin_strcmp(str, "Error reading DS18B20 sensor") == 0) - return 71; - if (__builtin_strcmp(str, "Error getting monotonic clock time") == 0) - return 72; - if (__builtin_strcmp(str, "Could not start DS18B20 reader thread") == 0) - return 73; - if (__builtin_strcmp(str, "Could not start DS18B20 reader thread (cond init)") == 0) - return 74; - if (__builtin_strcmp(str, "Could not start DS18B20 reader thread (mutex init)") == 0) - return 75; - if (__builtin_strcmp(str, "Invalid DS18B20 serial id, could not open for reading") == 0) - return 76; - if (__builtin_strcmp(str, "Invalid DS18B20 serial id, must not contain '/'") == 0) - return 77; - return 0xff; -} - -const struct initial_pin_s initial_pins[] PROGMEM = { -}; -const int initial_pins_size PROGMEM = ARRAY_SIZE(initial_pins); - -static const uint8_t command_parameters0[] PROGMEM = { - PT_uint16 }; -static const uint8_t command_parameters1[] PROGMEM = { - PT_uint32, PT_uint16 }; -static const uint8_t command_parameters2[] PROGMEM = { - PT_uint32, PT_progmem_buffer }; -static const uint8_t command_parameters3[] PROGMEM = { - PT_uint32, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters4[] PROGMEM = { - PT_uint32, PT_uint32 }; -static const uint8_t command_parameters5[] PROGMEM = { - PT_uint32 }; -static const uint8_t command_parameters6[] PROGMEM = { - PT_byte, PT_uint32, PT_byte, PT_uint16 }; -static const uint8_t command_parameters7[] PROGMEM = { - PT_buffer }; -static const uint8_t command_parameters8[] PROGMEM = { - PT_byte, PT_int32 }; -static const uint8_t command_parameters9[] PROGMEM = { - PT_byte, PT_byte, PT_uint32, PT_byte }; -static const uint8_t command_parameters10[] PROGMEM = { - PT_byte, PT_byte, PT_byte, PT_uint32 }; -static const uint8_t command_parameters11[] PROGMEM = { - PT_byte, PT_uint32, PT_uint16 }; -static const uint8_t command_parameters12[] PROGMEM = { - PT_byte, PT_buffer }; -static const uint8_t command_parameters13[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_byte }; -static const uint8_t command_parameters14[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint16, PT_byte, PT_byte, PT_uint16 }; -static const uint8_t command_parameters15[] PROGMEM = { - PT_byte, PT_uint16, PT_buffer }; -static const uint8_t command_parameters16[] PROGMEM = { - PT_byte, PT_uint32, PT_buffer }; -static const uint8_t command_parameters17[] PROGMEM = { - PT_byte, PT_uint16 }; -static const uint8_t command_parameters18[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint16, PT_byte, PT_uint32, PT_uint16 }; -static const uint8_t command_parameters19[] PROGMEM = { - PT_byte, PT_byte, PT_buffer }; -static const uint8_t command_parameters20[] PROGMEM = { - PT_byte, PT_byte }; -static const uint8_t command_parameters21[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters22[] PROGMEM = { - PT_byte, PT_uint32, PT_int32, PT_uint32 }; -static const uint8_t command_parameters23[] PROGMEM = { - PT_uint32, PT_byte }; -static const uint8_t command_parameters24[] PROGMEM = { - PT_byte }; -static const uint8_t command_parameters25[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters26[] PROGMEM = { - PT_byte, PT_uint32 }; -static const uint8_t command_parameters27[] PROGMEM = { - PT_byte, PT_uint32, PT_byte, PT_byte, PT_uint32 }; -static const uint8_t command_parameters28[] PROGMEM = { - PT_byte, PT_uint32, PT_uint16, PT_int16 }; -static const uint8_t command_parameters29[] PROGMEM = { - PT_byte, PT_byte, PT_byte, PT_byte, PT_uint32 }; -static const uint8_t command_parameters30[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_byte, PT_uint32, PT_byte, PT_byte, PT_byte }; -static const uint8_t command_parameters31[] PROGMEM = { - PT_byte, PT_byte, PT_byte }; -static const uint8_t command_parameters32[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_byte, PT_uint32, PT_uint16, PT_uint16, PT_byte }; -static const uint8_t command_parameters33[] PROGMEM = { - PT_byte, PT_uint32, PT_byte }; -static const uint8_t command_parameters34[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters35[] PROGMEM = { - PT_byte, PT_buffer, PT_buffer }; -static const uint8_t command_parameters36[] PROGMEM = { - PT_byte, PT_buffer, PT_uint32 }; -static const uint8_t command_parameters37[] PROGMEM = { - PT_uint32, PT_uint32, PT_uint16 }; -static const uint8_t command_parameters38[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint16, PT_uint16, PT_uint32 }; -static const uint8_t command_parameters39[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint32, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters40[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_uint32, PT_uint32, PT_uint32, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters41[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_byte, PT_byte }; -static const uint8_t command_parameters42[] PROGMEM = { - PT_byte, PT_buffer, PT_byte }; -static const uint8_t command_parameters43[] PROGMEM = { - PT_byte, PT_uint32, PT_byte, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters44[] PROGMEM = { - PT_byte, PT_uint32, PT_uint16, PT_uint32, PT_uint32 }; -static const uint8_t command_parameters45[] PROGMEM = { - PT_byte, PT_byte, PT_byte, PT_uint32, PT_uint16 }; -static const uint8_t command_parameters46[] PROGMEM = { - PT_byte, PT_byte, PT_byte, PT_byte, PT_uint32, PT_uint16, PT_uint16, PT_uint32 }; -static const uint8_t command_parameters47[] PROGMEM = { - PT_byte, PT_uint32, PT_uint32, PT_int32, PT_int32 }; - -const struct command_encoder command_encoder_81 PROGMEM = { - // starting - .msg_id=81, - .num_params=0, - .param_types = 0, - .max_size=6, -}; -const struct command_encoder command_encoder_82 PROGMEM = { - // is_shutdown static_string_id=%hu - .msg_id=82, - .num_params=1, - .param_types = command_parameters0, - .max_size=9, -}; -const struct command_encoder command_encoder_83 PROGMEM = { - // shutdown clock=%u static_string_id=%hu - .msg_id=83, - .num_params=2, - .param_types = command_parameters1, - .max_size=14, -}; -const struct command_encoder command_encoder_0 PROGMEM = { - // identify_response offset=%u data=%.*s - .msg_id=0, - .num_params=2, - .param_types = command_parameters2, - .max_size=64, -}; -const struct command_encoder command_encoder_84 PROGMEM = { - // stats count=%u sum=%u sumsq=%u - .msg_id=84, - .num_params=3, - .param_types = command_parameters3, - .max_size=21, -}; -const struct command_encoder command_encoder_85 PROGMEM = { - // uptime high=%u clock=%u - .msg_id=85, - .num_params=2, - .param_types = command_parameters4, - .max_size=16, -}; -const struct command_encoder command_encoder_86 PROGMEM = { - // clock clock=%u - .msg_id=86, - .num_params=1, - .param_types = command_parameters5, - .max_size=11, -}; -const struct command_encoder command_encoder_87 PROGMEM = { - // config is_config=%c crc=%u is_shutdown=%c move_count=%hu - .msg_id=87, - .num_params=4, - .param_types = command_parameters6, - .max_size=18, -}; -const struct command_encoder command_encoder_88 PROGMEM = { - // pong data=%*s - .msg_id=88, - .num_params=1, - .param_types = command_parameters7, - .max_size=64, -}; -const struct command_encoder command_encoder_89 PROGMEM = { - // debug_result val=%u - .msg_id=89, - .num_params=1, - .param_types = command_parameters5, - .max_size=11, -}; -const struct command_encoder command_encoder_90 PROGMEM = { - // stepper_position oid=%c pos=%i - .msg_id=90, - .num_params=2, - .param_types = command_parameters8, - .max_size=13, -}; -const struct command_encoder command_encoder_91 PROGMEM = { - // endstop_state oid=%c homing=%c next_clock=%u pin_value=%c - .msg_id=91, - .num_params=4, - .param_types = command_parameters9, - .max_size=17, -}; -const struct command_encoder command_encoder_92 PROGMEM = { - // trsync_state oid=%c can_trigger=%c trigger_reason=%c clock=%u - .msg_id=92, - .num_params=4, - .param_types = command_parameters10, - .max_size=17, -}; -const struct command_encoder command_encoder_93 PROGMEM = { - // analog_in_state oid=%c next_clock=%u value=%hu - .msg_id=93, - .num_params=3, - .param_types = command_parameters11, - .max_size=16, -}; -const struct command_encoder command_encoder_94 PROGMEM = { - // spi_transfer_response oid=%c response=%*s - .msg_id=94, - .num_params=2, - .param_types = command_parameters12, - .max_size=64, -}; -const struct command_encoder command_encoder_95 PROGMEM = { - // thermocouple_result oid=%c next_clock=%u value=%u fault=%c - .msg_id=95, - .num_params=4, - .param_types = command_parameters13, - .max_size=20, -}; -const struct command_encoder command_encoder_96 PROGMEM = { - // i2c_read_response oid=%c response=%*s - .msg_id=96, - .num_params=2, - .param_types = command_parameters12, - .max_size=64, -}; -const struct command_encoder command_encoder_97 PROGMEM = { - // adxl345_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%c limit_count=%hu - .msg_id=97, - .num_params=7, - .param_types = command_parameters14, - .max_size=28, -}; -const struct command_encoder command_encoder_98 PROGMEM = { - // adxl345_data oid=%c sequence=%hu data=%*s - .msg_id=98, - .num_params=3, - .param_types = command_parameters15, - .max_size=64, -}; -const struct command_encoder command_encoder_99 PROGMEM = { - // spi_angle_transfer_response oid=%c clock=%u response=%*s - .msg_id=99, - .num_params=3, - .param_types = command_parameters16, - .max_size=64, -}; -const struct command_encoder command_encoder_100 PROGMEM = { - // spi_angle_end oid=%c sequence=%hu - .msg_id=100, - .num_params=2, - .param_types = command_parameters17, - .max_size=11, -}; -const struct command_encoder command_encoder_101 PROGMEM = { - // spi_angle_data oid=%c sequence=%hu data=%*s - .msg_id=101, - .num_params=3, - .param_types = command_parameters15, - .max_size=64, -}; -const struct command_encoder command_encoder_102 PROGMEM = { - // mpu9250_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%u limit_count=%hu - .msg_id=102, - .num_params=7, - .param_types = command_parameters18, - .max_size=31, -}; -const struct command_encoder command_encoder_103 PROGMEM = { - // mpu9250_data oid=%c sequence=%hu data=%*s - .msg_id=103, - .num_params=3, - .param_types = command_parameters15, - .max_size=64, -}; -const struct command_encoder command_encoder_104 PROGMEM = { - // buttons_state oid=%c ack_count=%c state=%*s - .msg_id=104, - .num_params=3, - .param_types = command_parameters19, - .max_size=64, -}; -const struct command_encoder command_encoder_105 PROGMEM = { - // tmcuart_response oid=%c read=%*s - .msg_id=105, - .num_params=2, - .param_types = command_parameters12, - .max_size=64, -}; -const struct command_encoder command_encoder_106 PROGMEM = { - // neopixel_result oid=%c success=%c - .msg_id=106, - .num_params=2, - .param_types = command_parameters20, - .max_size=10, -}; -const struct command_encoder command_encoder_107 PROGMEM = { - // counter_state oid=%c next_clock=%u count=%u count_clock=%u - .msg_id=107, - .num_params=4, - .param_types = command_parameters21, - .max_size=23, -}; -const struct command_encoder command_encoder_108 PROGMEM = { - // ds18b20_result oid=%c next_clock=%u value=%i fault=%u - .msg_id=108, - .num_params=4, - .param_types = command_parameters22, - .max_size=23, -}; - -const __always_inline struct command_encoder * -ctr_lookup_encoder(const char *str) -{ - if (__builtin_strcmp(str, "starting") == 0) - return &command_encoder_81; - if (__builtin_strcmp(str, "is_shutdown static_string_id=%hu") == 0) - return &command_encoder_82; - if (__builtin_strcmp(str, "shutdown clock=%u static_string_id=%hu") == 0) - return &command_encoder_83; - if (__builtin_strcmp(str, "identify_response offset=%u data=%.*s") == 0) - return &command_encoder_0; - if (__builtin_strcmp(str, "stats count=%u sum=%u sumsq=%u") == 0) - return &command_encoder_84; - if (__builtin_strcmp(str, "uptime high=%u clock=%u") == 0) - return &command_encoder_85; - if (__builtin_strcmp(str, "clock clock=%u") == 0) - return &command_encoder_86; - if (__builtin_strcmp(str, "config is_config=%c crc=%u is_shutdown=%c move_count=%hu") == 0) - return &command_encoder_87; - if (__builtin_strcmp(str, "pong data=%*s") == 0) - return &command_encoder_88; - if (__builtin_strcmp(str, "debug_result val=%u") == 0) - return &command_encoder_89; - if (__builtin_strcmp(str, "stepper_position oid=%c pos=%i") == 0) - return &command_encoder_90; - if (__builtin_strcmp(str, "endstop_state oid=%c homing=%c next_clock=%u pin_value=%c") == 0) - return &command_encoder_91; - if (__builtin_strcmp(str, "trsync_state oid=%c can_trigger=%c trigger_reason=%c clock=%u") == 0) - return &command_encoder_92; - if (__builtin_strcmp(str, "analog_in_state oid=%c next_clock=%u value=%hu") == 0) - return &command_encoder_93; - if (__builtin_strcmp(str, "spi_transfer_response oid=%c response=%*s") == 0) - return &command_encoder_94; - if (__builtin_strcmp(str, "thermocouple_result oid=%c next_clock=%u value=%u fault=%c") == 0) - return &command_encoder_95; - if (__builtin_strcmp(str, "i2c_read_response oid=%c response=%*s") == 0) - return &command_encoder_96; - if (__builtin_strcmp(str, "adxl345_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%c limit_count=%hu") == 0) - return &command_encoder_97; - if (__builtin_strcmp(str, "adxl345_data oid=%c sequence=%hu data=%*s") == 0) - return &command_encoder_98; - if (__builtin_strcmp(str, "spi_angle_transfer_response oid=%c clock=%u response=%*s") == 0) - return &command_encoder_99; - if (__builtin_strcmp(str, "spi_angle_end oid=%c sequence=%hu") == 0) - return &command_encoder_100; - if (__builtin_strcmp(str, "spi_angle_data oid=%c sequence=%hu data=%*s") == 0) - return &command_encoder_101; - if (__builtin_strcmp(str, "mpu9250_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%u limit_count=%hu") == 0) - return &command_encoder_102; - if (__builtin_strcmp(str, "mpu9250_data oid=%c sequence=%hu data=%*s") == 0) - return &command_encoder_103; - if (__builtin_strcmp(str, "buttons_state oid=%c ack_count=%c state=%*s") == 0) - return &command_encoder_104; - if (__builtin_strcmp(str, "tmcuart_response oid=%c read=%*s") == 0) - return &command_encoder_105; - if (__builtin_strcmp(str, "neopixel_result oid=%c success=%c") == 0) - return &command_encoder_106; - if (__builtin_strcmp(str, "counter_state oid=%c next_clock=%u count=%u count_clock=%u") == 0) - return &command_encoder_107; - if (__builtin_strcmp(str, "ds18b20_result oid=%c next_clock=%u value=%i fault=%u") == 0) - return &command_encoder_108; - return NULL; -} - -const __always_inline struct command_encoder * -ctr_lookup_output(const char *str) -{ - - return NULL; -} - -extern void command_allocate_oids(uint32_t*); -extern void command_buttons_ack(uint32_t*); -extern void command_buttons_add(uint32_t*); -extern void command_buttons_query(uint32_t*); -extern void command_clear_shutdown(uint32_t*); -extern void command_config_adxl345(uint32_t*); -extern void command_config_analog_in(uint32_t*); -extern void command_config_buttons(uint32_t*); -extern void command_config_counter(uint32_t*); -extern void command_config_digital_out(uint32_t*); -extern void command_config_ds18b20(uint32_t*); -extern void command_config_endstop(uint32_t*); -extern void command_config_hd44780(uint32_t*); -extern void command_config_i2c(uint32_t*); -extern void command_config_mpu9250(uint32_t*); -extern void command_config_neopixel(uint32_t*); -extern void command_config_pca9685(uint32_t*); -extern void command_config_pwm_out(uint32_t*); -extern void command_config_reset(uint32_t*); -extern void command_config_spi(uint32_t*); -extern void command_config_spi_angle(uint32_t*); -extern void command_config_spi_shutdown(uint32_t*); -extern void command_config_spi_without_cs(uint32_t*); -extern void command_config_st7920(uint32_t*); -extern void command_config_stepper(uint32_t*); -extern void command_config_thermocouple(uint32_t*); -extern void command_config_tmcuart(uint32_t*); -extern void command_config_trsync(uint32_t*); -extern void command_debug_nop(uint32_t*); -extern void command_debug_ping(uint32_t*); -extern void command_debug_read(uint32_t*); -extern void command_debug_write(uint32_t*); -extern void command_emergency_stop(uint32_t*); -extern void command_endstop_home(uint32_t*); -extern void command_endstop_query_state(uint32_t*); -extern void command_finalize_config(uint32_t*); -extern void command_get_clock(uint32_t*); -extern void command_get_config(uint32_t*); -extern void command_get_uptime(uint32_t*); -extern void command_hd44780_send_cmds(uint32_t*); -extern void command_hd44780_send_data(uint32_t*); -extern void command_i2c_modify_bits(uint32_t*); -extern void command_i2c_read(uint32_t*); -extern void command_i2c_write(uint32_t*); -extern void command_identify(uint32_t*); -extern void command_neopixel_send(uint32_t*); -extern void command_neopixel_update(uint32_t*); -extern void command_query_adxl345(uint32_t*); -extern void command_query_adxl345_status(uint32_t*); -extern void command_query_analog_in(uint32_t*); -extern void command_query_counter(uint32_t*); -extern void command_query_ds18b20(uint32_t*); -extern void command_query_mpu9250(uint32_t*); -extern void command_query_mpu9250_status(uint32_t*); -extern void command_query_spi_angle(uint32_t*); -extern void command_query_thermocouple(uint32_t*); -extern void command_queue_digital_out(uint32_t*); -extern void command_queue_pca9685_out(uint32_t*); -extern void command_queue_pwm_out(uint32_t*); -extern void command_queue_step(uint32_t*); -extern void command_reset_step_clock(uint32_t*); -extern void command_set_digital_out(uint32_t*); -extern void command_set_digital_out_pwm_cycle(uint32_t*); -extern void command_set_next_step_dir(uint32_t*); -extern void command_set_pca9685_out(uint32_t*); -extern void command_set_pwm_out(uint32_t*); -extern void command_spi_angle_transfer(uint32_t*); -extern void command_spi_send(uint32_t*); -extern void command_spi_set_bus(uint32_t*); -extern void command_spi_set_software_bus(uint32_t*); -extern void command_spi_transfer(uint32_t*); -extern void command_st7920_send_cmds(uint32_t*); -extern void command_st7920_send_data(uint32_t*); -extern void command_stepper_get_position(uint32_t*); -extern void command_stepper_stop_on_trigger(uint32_t*); -extern void command_tmcuart_send(uint32_t*); -extern void command_trsync_set_timeout(uint32_t*); -extern void command_trsync_start(uint32_t*); -extern void command_trsync_trigger(uint32_t*); -extern void command_update_digital_out(uint32_t*); - -const struct command_parser command_index[] PROGMEM = { -{ -}, { - // identify offset=%u count=%c - .msg_id=1, - .num_params=2, - .param_types = command_parameters23, - .num_args=2, - .flags=0x01, - .func=command_identify -}, { - // clear_shutdown - .msg_id=2, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_clear_shutdown -}, { - // emergency_stop - .msg_id=3, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_emergency_stop -}, { - // get_uptime - .msg_id=4, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_get_uptime -}, { - // get_clock - .msg_id=5, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_get_clock -}, { - // finalize_config crc=%u - .msg_id=6, - .num_params=1, - .param_types = command_parameters5, - .num_args=1, - .flags=0, - .func=command_finalize_config -}, { - // get_config - .msg_id=7, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_get_config -}, { - // allocate_oids count=%c - .msg_id=8, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_allocate_oids -}, { - // debug_nop - .msg_id=9, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_debug_nop -}, { - // debug_ping data=%*s - .msg_id=10, - .num_params=1, - .param_types = command_parameters7, - .num_args=2, - .flags=0x01, - .func=command_debug_ping -}, { - // debug_write order=%c addr=%u val=%u - .msg_id=11, - .num_params=3, - .param_types = command_parameters25, - .num_args=3, - .flags=0x01, - .func=command_debug_write -}, { - // debug_read order=%c addr=%u - .msg_id=12, - .num_params=2, - .param_types = command_parameters26, - .num_args=2, - .flags=0x01, - .func=command_debug_read -}, { - // set_digital_out pin=%u value=%c - .msg_id=13, - .num_params=2, - .param_types = command_parameters23, - .num_args=2, - .flags=0, - .func=command_set_digital_out -}, { - // update_digital_out oid=%c value=%c - .msg_id=14, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_update_digital_out -}, { - // queue_digital_out oid=%c clock=%u on_ticks=%u - .msg_id=15, - .num_params=3, - .param_types = command_parameters25, - .num_args=3, - .flags=0, - .func=command_queue_digital_out -}, { - // set_digital_out_pwm_cycle oid=%c cycle_ticks=%u - .msg_id=16, - .num_params=2, - .param_types = command_parameters26, - .num_args=2, - .flags=0, - .func=command_set_digital_out_pwm_cycle -}, { - // config_digital_out oid=%c pin=%u value=%c default_value=%c max_duration=%u - .msg_id=17, - .num_params=5, - .param_types = command_parameters27, - .num_args=5, - .flags=0, - .func=command_config_digital_out -}, { - // stepper_stop_on_trigger oid=%c trsync_oid=%c - .msg_id=18, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_stepper_stop_on_trigger -}, { - // stepper_get_position oid=%c - .msg_id=19, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_stepper_get_position -}, { - // reset_step_clock oid=%c clock=%u - .msg_id=20, - .num_params=2, - .param_types = command_parameters26, - .num_args=2, - .flags=0, - .func=command_reset_step_clock -}, { - // set_next_step_dir oid=%c dir=%c - .msg_id=21, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_set_next_step_dir -}, { - // queue_step oid=%c interval=%u count=%hu add=%hi - .msg_id=22, - .num_params=4, - .param_types = command_parameters28, - .num_args=4, - .flags=0, - .func=command_queue_step -}, { - // config_stepper oid=%c step_pin=%c dir_pin=%c invert_step=%c step_pulse_ticks=%u - .msg_id=23, - .num_params=5, - .param_types = command_parameters29, - .num_args=5, - .flags=0, - .func=command_config_stepper -}, { - // endstop_query_state oid=%c - .msg_id=24, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_endstop_query_state -}, { - // endstop_home oid=%c clock=%u sample_ticks=%u sample_count=%c rest_ticks=%u pin_value=%c trsync_oid=%c trigger_reason=%c - .msg_id=25, - .num_params=8, - .param_types = command_parameters30, - .num_args=8, - .flags=0, - .func=command_endstop_home -}, { - // config_endstop oid=%c pin=%c pull_up=%c - .msg_id=26, - .num_params=3, - .param_types = command_parameters31, - .num_args=3, - .flags=0, - .func=command_config_endstop -}, { - // trsync_trigger oid=%c reason=%c - .msg_id=27, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_trsync_trigger -}, { - // trsync_set_timeout oid=%c clock=%u - .msg_id=28, - .num_params=2, - .param_types = command_parameters26, - .num_args=2, - .flags=0, - .func=command_trsync_set_timeout -}, { - // trsync_start oid=%c report_clock=%u report_ticks=%u expire_reason=%c - .msg_id=29, - .num_params=4, - .param_types = command_parameters13, - .num_args=4, - .flags=0, - .func=command_trsync_start -}, { - // config_trsync oid=%c - .msg_id=30, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_config_trsync -}, { - // query_analog_in oid=%c clock=%u sample_ticks=%u sample_count=%c rest_ticks=%u min_value=%hu max_value=%hu range_check_count=%c - .msg_id=31, - .num_params=8, - .param_types = command_parameters32, - .num_args=8, - .flags=0, - .func=command_query_analog_in -}, { - // config_analog_in oid=%c pin=%u - .msg_id=32, - .num_params=2, - .param_types = command_parameters26, - .num_args=2, - .flags=0, - .func=command_config_analog_in -}, { - // config_spi_shutdown oid=%c spi_oid=%c shutdown_msg=%*s - .msg_id=33, - .num_params=3, - .param_types = command_parameters19, - .num_args=4, - .flags=0, - .func=command_config_spi_shutdown -}, { - // spi_send oid=%c data=%*s - .msg_id=34, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_spi_send -}, { - // spi_transfer oid=%c data=%*s - .msg_id=35, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_spi_transfer -}, { - // spi_set_bus oid=%c spi_bus=%u mode=%u rate=%u - .msg_id=36, - .num_params=4, - .param_types = command_parameters21, - .num_args=4, - .flags=0, - .func=command_spi_set_bus -}, { - // config_spi_without_cs oid=%c - .msg_id=37, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_config_spi_without_cs -}, { - // config_spi oid=%c pin=%u cs_active_high=%c - .msg_id=38, - .num_params=3, - .param_types = command_parameters33, - .num_args=3, - .flags=0, - .func=command_config_spi -}, { - // query_thermocouple oid=%c clock=%u rest_ticks=%u min_value=%u max_value=%u - .msg_id=39, - .num_params=5, - .param_types = command_parameters34, - .num_args=5, - .flags=0, - .func=command_query_thermocouple -}, { - // config_thermocouple oid=%c spi_oid=%c thermocouple_type=%c - .msg_id=40, - .num_params=3, - .param_types = command_parameters31, - .num_args=3, - .flags=0, - .func=command_config_thermocouple -}, { - // i2c_modify_bits oid=%c reg=%*s clear_set_bits=%*s - .msg_id=41, - .num_params=3, - .param_types = command_parameters35, - .num_args=5, - .flags=0, - .func=command_i2c_modify_bits -}, { - // i2c_read oid=%c reg=%*s read_len=%u - .msg_id=42, - .num_params=3, - .param_types = command_parameters36, - .num_args=4, - .flags=0, - .func=command_i2c_read -}, { - // i2c_write oid=%c data=%*s - .msg_id=43, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_i2c_write -}, { - // config_i2c oid=%c i2c_bus=%u rate=%u address=%u - .msg_id=44, - .num_params=4, - .param_types = command_parameters21, - .num_args=4, - .flags=0, - .func=command_config_i2c -}, { - // set_pwm_out pin=%u cycle_ticks=%u value=%hu - .msg_id=45, - .num_params=3, - .param_types = command_parameters37, - .num_args=3, - .flags=0, - .func=command_set_pwm_out -}, { - // queue_pwm_out oid=%c clock=%u value=%hu - .msg_id=46, - .num_params=3, - .param_types = command_parameters11, - .num_args=3, - .flags=0, - .func=command_queue_pwm_out -}, { - // config_pwm_out oid=%c pin=%u cycle_ticks=%u value=%hu default_value=%hu max_duration=%u - .msg_id=47, - .num_params=6, - .param_types = command_parameters38, - .num_args=6, - .flags=0, - .func=command_config_pwm_out -}, { - // spi_set_software_bus oid=%c miso_pin=%u mosi_pin=%u sclk_pin=%u mode=%u rate=%u - .msg_id=48, - .num_params=6, - .param_types = command_parameters39, - .num_args=6, - .flags=0, - .func=command_spi_set_software_bus -}, { - // query_adxl345_status oid=%c - .msg_id=49, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_query_adxl345_status -}, { - // query_adxl345 oid=%c clock=%u rest_ticks=%u - .msg_id=50, - .num_params=3, - .param_types = command_parameters25, - .num_args=3, - .flags=0, - .func=command_query_adxl345 -}, { - // config_adxl345 oid=%c spi_oid=%c - .msg_id=51, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_config_adxl345 -}, { - // spi_angle_transfer oid=%c data=%*s - .msg_id=52, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_spi_angle_transfer -}, { - // query_spi_angle oid=%c clock=%u rest_ticks=%u time_shift=%c - .msg_id=53, - .num_params=4, - .param_types = command_parameters13, - .num_args=4, - .flags=0, - .func=command_query_spi_angle -}, { - // config_spi_angle oid=%c spi_oid=%c spi_angle_type=%c - .msg_id=54, - .num_params=3, - .param_types = command_parameters31, - .num_args=3, - .flags=0, - .func=command_config_spi_angle -}, { - // query_mpu9250_status oid=%c - .msg_id=55, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_query_mpu9250_status -}, { - // query_mpu9250 oid=%c clock=%u rest_ticks=%u - .msg_id=56, - .num_params=3, - .param_types = command_parameters25, - .num_args=3, - .flags=0, - .func=command_query_mpu9250 -}, { - // config_mpu9250 oid=%c i2c_oid=%c - .msg_id=57, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_config_mpu9250 -}, { - // st7920_send_data oid=%c data=%*s - .msg_id=58, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_st7920_send_data -}, { - // st7920_send_cmds oid=%c cmds=%*s - .msg_id=59, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_st7920_send_cmds -}, { - // config_st7920 oid=%c cs_pin=%u sclk_pin=%u sid_pin=%u sync_delay_ticks=%u cmd_delay_ticks=%u - .msg_id=60, - .num_params=6, - .param_types = command_parameters39, - .num_args=6, - .flags=0, - .func=command_config_st7920 -}, { - // hd44780_send_data oid=%c data=%*s - .msg_id=61, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_hd44780_send_data -}, { - // hd44780_send_cmds oid=%c cmds=%*s - .msg_id=62, - .num_params=2, - .param_types = command_parameters12, - .num_args=3, - .flags=0, - .func=command_hd44780_send_cmds -}, { - // config_hd44780 oid=%c rs_pin=%u e_pin=%u d4_pin=%u d5_pin=%u d6_pin=%u d7_pin=%u delay_ticks=%u - .msg_id=63, - .num_params=8, - .param_types = command_parameters40, - .num_args=8, - .flags=0, - .func=command_config_hd44780 -}, { - // buttons_ack oid=%c count=%c - .msg_id=64, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_buttons_ack -}, { - // buttons_query oid=%c clock=%u rest_ticks=%u retransmit_count=%c invert=%c - .msg_id=65, - .num_params=5, - .param_types = command_parameters41, - .num_args=5, - .flags=0, - .func=command_buttons_query -}, { - // buttons_add oid=%c pos=%c pin=%u pull_up=%c - .msg_id=66, - .num_params=4, - .param_types = command_parameters9, - .num_args=4, - .flags=0, - .func=command_buttons_add -}, { - // config_buttons oid=%c button_count=%c - .msg_id=67, - .num_params=2, - .param_types = command_parameters20, - .num_args=2, - .flags=0, - .func=command_config_buttons -}, { - // tmcuart_send oid=%c write=%*s read=%c - .msg_id=68, - .num_params=3, - .param_types = command_parameters42, - .num_args=4, - .flags=0, - .func=command_tmcuart_send -}, { - // config_tmcuart oid=%c rx_pin=%u pull_up=%c tx_pin=%u bit_time=%u - .msg_id=69, - .num_params=5, - .param_types = command_parameters43, - .num_args=5, - .flags=0, - .func=command_config_tmcuart -}, { - // neopixel_send oid=%c - .msg_id=70, - .num_params=1, - .param_types = command_parameters24, - .num_args=1, - .flags=0, - .func=command_neopixel_send -}, { - // neopixel_update oid=%c pos=%hu data=%*s - .msg_id=71, - .num_params=3, - .param_types = command_parameters15, - .num_args=4, - .flags=0, - .func=command_neopixel_update -}, { - // config_neopixel oid=%c pin=%u data_size=%hu bit_max_ticks=%u reset_min_ticks=%u - .msg_id=72, - .num_params=5, - .param_types = command_parameters44, - .num_args=5, - .flags=0, - .func=command_config_neopixel -}, { - // query_counter oid=%c clock=%u poll_ticks=%u sample_ticks=%u - .msg_id=73, - .num_params=4, - .param_types = command_parameters21, - .num_args=4, - .flags=0, - .func=command_query_counter -}, { - // config_counter oid=%c pin=%u pull_up=%c - .msg_id=74, - .num_params=3, - .param_types = command_parameters33, - .num_args=3, - .flags=0, - .func=command_config_counter -}, { - // config_reset - .msg_id=75, - .num_params=0, - .param_types = 0, - .num_args=0, - .flags=0x01, - .func=command_config_reset -}, { - // set_pca9685_out bus=%c addr=%c channel=%c cycle_ticks=%u value=%hu - .msg_id=76, - .num_params=5, - .param_types = command_parameters45, - .num_args=5, - .flags=0, - .func=command_set_pca9685_out -}, { - // queue_pca9685_out oid=%c clock=%u value=%hu - .msg_id=77, - .num_params=3, - .param_types = command_parameters11, - .num_args=3, - .flags=0, - .func=command_queue_pca9685_out -}, { - // config_pca9685 oid=%c bus=%c addr=%c channel=%c cycle_ticks=%u value=%hu default_value=%hu max_duration=%u - .msg_id=78, - .num_params=8, - .param_types = command_parameters46, - .num_args=8, - .flags=0, - .func=command_config_pca9685 -}, { - // query_ds18b20 oid=%c clock=%u rest_ticks=%u min_value=%i max_value=%i - .msg_id=79, - .num_params=5, - .param_types = command_parameters47, - .num_args=5, - .flags=0, - .func=command_query_ds18b20 -}, { - // config_ds18b20 oid=%c serial=%*s max_error_count=%c - .msg_id=80, - .num_params=3, - .param_types = command_parameters42, - .num_args=4, - .flags=0, - .func=command_config_ds18b20 -}, -}; - -const uint8_t command_index_size PROGMEM = ARRAY_SIZE(command_index); - -// version: v0.10.0-530-g3387a9c2 -// build_versions: gcc: (Debian 8.3.0-6) 8.3.0 binutils: (GNU Binutils for Debian) 2.31.1 - -const uint8_t command_identify_data[] PROGMEM = { - 0x78, 0xda, 0xa5, 0x1a, 0x6b, 0x6f, 0xdb, 0x38, - 0xf2, 0xaf, 0xf0, 0x0c, 0x14, 0xdd, 0x1e, 0x12, - 0xaf, 0xad, 0x87, 0x2d, 0x1b, 0xe8, 0x87, 0x34, - 0xed, 0x2e, 0x8a, 0xbb, 0x5c, 0xbb, 0x9b, 0x16, - 0x77, 0xc0, 0x61, 0x21, 0x28, 0x12, 0x6d, 0x13, - 0xd1, 0x6b, 0x45, 0x29, 0x8f, 0x5b, 0xe4, 0xbf, - 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0x97, 0x08, 0xd6, 0x3e, 0x85, 0xd7, 0x1a, 0xf3, - 0x09, 0x10, 0x2f, 0x39, 0xd5, 0xd0, 0x3c, 0xba, - 0x60, 0xbf, 0x1b, 0xee, 0xdf, 0x34, 0xa6, 0x12, - 0x7e, 0x07, 0xf1, 0x1b, 0x9a, 0xb1, 0x89, 0x54, - 0x45, 0xdd, 0xf5, 0xaa, 0xaa, 0x48, 0x96, 0x54, - 0x5f, 0x4b, 0x67, 0x0a, 0x72, 0xa8, 0xf4, 0x8f, - 0xfc, 0x9d, 0x34, 0x3e, 0x72, 0x3d, 0xc1, 0x49, - 0xc3, 0x90, 0xde, 0x71, 0x20, 0xce, 0x6c, 0x16, - 0x13, 0xc7, 0xf8, 0x1d, 0xa6, 0x31, 0x18, 0xd3, - 0x40, 0xd5, 0x8e, 0x5d, 0x17, 0xf1, 0x98, 0x7f, - 0xec, 0x1f, 0xd2, 0x59, 0x43, 0xbf, 0x33, 0xe8, - 0xec, 0x27, 0xcf, 0x6c, 0x9b, 0xf2, 0xe4, 0xcb, - 0x9f, 0xe7, 0x57, 0x36, 0x01, 0xfa, 0x7d, 0x55, - 0x4e, 0xd3, 0x33, 0xf8, 0xe0, 0x3b, 0x9d, 0x18, - 0xdc, 0xb2, 0xfe, 0xdf, 0x9d, 0xd9, 0x76, 0x76, - 0xb7, 0x98, 0x2f, 0x17, 0xf3, 0xc5, 0x79, 0x1c, - 0x2e, 0xce, 0xf7, 0x61, 0x98, 0xac, 0xb3, 0x4d, - 0x1e, 0xcc, 0x9e, 0xfe, 0x0b, 0xee, 0xa1, 0xf0, - 0x3a, -}; - -// Identify size = 3073 (9189 uncompressed) -const uint32_t command_identify_size PROGMEM - = ARRAY_SIZE(command_identify_data); diff --git a/out/compile_time_request.d b/out/compile_time_request.d deleted file mode 100644 index 5bff05d..0000000 --- a/out/compile_time_request.d +++ /dev/null @@ -1,18 +0,0 @@ -out/compile_time_request.o: out/compile_time_request.c \ - /usr/include/stdc-predef.h out/board-generic/board/irq.h \ - out/board-generic/board/pgm.h src/command.h \ - /usr/lib/gcc/aarch64-linux-gnu/8/include/stdarg.h \ - /usr/lib/gcc/aarch64-linux-gnu/8/include/stddef.h \ - /usr/lib/gcc/aarch64-linux-gnu/8/include/stdint.h /usr/include/stdint.h \ - /usr/include/aarch64-linux-gnu/bits/libc-header-start.h \ - /usr/include/features.h /usr/include/aarch64-linux-gnu/sys/cdefs.h \ - /usr/include/aarch64-linux-gnu/bits/wordsize.h \ - /usr/include/aarch64-linux-gnu/bits/long-double.h \ - /usr/include/aarch64-linux-gnu/gnu/stubs.h \ - /usr/include/aarch64-linux-gnu/gnu/stubs-lp64.h \ - /usr/include/aarch64-linux-gnu/bits/types.h \ - /usr/include/aarch64-linux-gnu/bits/typesizes.h \ - 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a/out/compile_time_request.txt b/out/compile_time_request.txt deleted file mode 100644 index 551d451..0000000 --- a/out/compile_time_request.txt +++ /dev/null @@ -1,263 +0,0 @@ -_DECL_ENCODER starting -_DECL_ENCODER is_shutdown static_string_id=%hu -_DECL_ENCODER shutdown clock=%u static_string_id=%hu -_DECL_STATIC_STR Shutdown cleared when not shutdown -_DECL_STATIC_STR Timer too close -_DECL_STATIC_STR sentinel timer called -_DECL_STATIC_STR Invalid command -_DECL_CALLLIST ctr_run_shutdownfuncs sendf_shutdown -_DECL_STATIC_STR Message encode error -_DECL_STATIC_STR Command parser error -DECL_COMMAND_FLAGS command_identify 0x01 identify offset=%u count=%c -_DECL_ENCODER identify_response offset=%u data=%.*s -DECL_COMMAND_FLAGS command_clear_shutdown 0x01 clear_shutdown -DECL_COMMAND_FLAGS command_emergency_stop 0x01 emergency_stop -_DECL_STATIC_STR Command request -_DECL_ENCODER stats count=%u sum=%u sumsq=%u -DECL_CONSTANT STATS_SUMSQ_BASE +0x00000100 -DECL_COMMAND_FLAGS command_get_uptime 0x01 get_uptime -_DECL_ENCODER uptime high=%u clock=%u -DECL_COMMAND_FLAGS command_get_clock 0x01 get_clock -_DECL_ENCODER clock clock=%u -_DECL_STATIC_STR config_reset only available when shutdown -DECL_COMMAND_FLAGS command_finalize_config 0 finalize_config crc=%u -DECL_COMMAND_FLAGS command_get_config 0x01 get_config -_DECL_ENCODER config is_config=%c crc=%u is_shutdown=%c move_count=%hu -DECL_COMMAND_FLAGS command_allocate_oids 0 allocate_oids count=%c -_DECL_STATIC_STR oids already allocated -_DECL_STATIC_STR Can't assign oid -_DECL_STATIC_STR Invalid oid type -_DECL_STATIC_STR Already finalized -_DECL_CALLLIST ctr_run_shutdownfuncs move_reset -_DECL_STATIC_STR Invalid move request size -_DECL_STATIC_STR Move queue overflow -_DECL_STATIC_STR alloc_chunks failed -_DECL_STATIC_STR alloc_chunk failed -_DECL_CALLLIST ctr_run_initfuncs alloc_init -DECL_COMMAND_FLAGS command_debug_nop 0x01 debug_nop -DECL_COMMAND_FLAGS command_debug_ping 0x01 debug_ping data=%*s -_DECL_ENCODER pong data=%*s -DECL_COMMAND_FLAGS command_debug_write 0x01 debug_write order=%c addr=%u val=%u -DECL_COMMAND_FLAGS command_debug_read 0x01 debug_read order=%c addr=%u -_DECL_ENCODER debug_result val=%u -_DECL_CALLLIST ctr_run_initfuncs initial_pins_setup -DECL_INITIAL_PINS "" -DECL_COMMAND_FLAGS command_set_digital_out 0 set_digital_out pin=%u value=%c -_DECL_CALLLIST ctr_run_shutdownfuncs digital_out_shutdown -DECL_COMMAND_FLAGS command_update_digital_out 0 update_digital_out oid=%c value=%c -_DECL_STATIC_STR update_digital_out not valid with active queue -DECL_COMMAND_FLAGS command_queue_digital_out 0 queue_digital_out oid=%c clock=%u on_ticks=%u -_DECL_STATIC_STR Scheduled digital out event will exceed max_duration -DECL_COMMAND_FLAGS command_set_digital_out_pwm_cycle 0 set_digital_out_pwm_cycle oid=%c cycle_ticks=%u -_DECL_STATIC_STR Can not set soft pwm cycle ticks while updates pending -DECL_COMMAND_FLAGS command_config_digital_out 0 config_digital_out oid=%c pin=%u value=%c default_value=%c max_duration=%u -_DECL_STATIC_STR Scheduled digital out event will exceed max_duration -_DECL_STATIC_STR Missed scheduling of next digital out event -_DECL_CALLLIST ctr_run_shutdownfuncs stepper_shutdown -DECL_COMMAND_FLAGS command_stepper_stop_on_trigger 0 stepper_stop_on_trigger oid=%c trsync_oid=%c -DECL_COMMAND_FLAGS command_stepper_get_position 0 stepper_get_position oid=%c -_DECL_ENCODER stepper_position oid=%c pos=%i -DECL_COMMAND_FLAGS command_reset_step_clock 0 reset_step_clock oid=%c clock=%u -_DECL_STATIC_STR Can't reset time when stepper active -DECL_COMMAND_FLAGS command_set_next_step_dir 0 set_next_step_dir oid=%c dir=%c -DECL_COMMAND_FLAGS command_queue_step 0 queue_step oid=%c interval=%u count=%hu add=%hi -_DECL_STATIC_STR Invalid count parameter -DECL_COMMAND_FLAGS command_config_stepper 0 config_stepper oid=%c step_pin=%c dir_pin=%c invert_step=%c step_pulse_ticks=%u -_DECL_STATIC_STR Stepper too far in past -DECL_COMMAND_FLAGS command_endstop_query_state 0 endstop_query_state oid=%c -_DECL_ENCODER endstop_state oid=%c homing=%c next_clock=%u pin_value=%c -DECL_COMMAND_FLAGS command_endstop_home 0 endstop_home oid=%c clock=%u sample_ticks=%u sample_count=%c rest_ticks=%u pin_value=%c trsync_oid=%c trigger_reason=%c -DECL_COMMAND_FLAGS command_config_endstop 0 config_endstop oid=%c pin=%c pull_up=%c -_DECL_CALLLIST ctr_run_shutdownfuncs trsync_shutdown -_DECL_CALLLIST ctr_run_taskfuncs trsync_task -DECL_COMMAND_FLAGS command_trsync_trigger 0 trsync_trigger oid=%c reason=%c -_DECL_ENCODER trsync_state oid=%c can_trigger=%c trigger_reason=%c clock=%u -DECL_COMMAND_FLAGS command_trsync_set_timeout 0 trsync_set_timeout oid=%c clock=%u -DECL_COMMAND_FLAGS command_trsync_start 0 trsync_start oid=%c report_clock=%u report_ticks=%u expire_reason=%c -_DECL_STATIC_STR Can't add signal that is already active -DECL_COMMAND_FLAGS command_config_trsync 0 config_trsync oid=%c -_DECL_CALLLIST ctr_run_shutdownfuncs analog_in_shutdown -_DECL_CALLLIST ctr_run_taskfuncs analog_in_task -_DECL_ENCODER analog_in_state oid=%c next_clock=%u value=%hu -DECL_COMMAND_FLAGS command_query_analog_in 0 query_analog_in oid=%c clock=%u sample_ticks=%u sample_count=%c rest_ticks=%u min_value=%hu max_value=%hu range_check_count=%c -DECL_COMMAND_FLAGS command_config_analog_in 0 config_analog_in oid=%c pin=%u -_DECL_STATIC_STR ADC out of range -_DECL_CALLLIST ctr_run_shutdownfuncs spidev_shutdown -DECL_COMMAND_FLAGS command_config_spi_shutdown 0 config_spi_shutdown oid=%c spi_oid=%c shutdown_msg=%*s -DECL_COMMAND_FLAGS command_spi_send 0 spi_send oid=%c data=%*s -DECL_COMMAND_FLAGS command_spi_transfer 0 spi_transfer oid=%c data=%*s -_DECL_ENCODER spi_transfer_response oid=%c response=%*s -_DECL_STATIC_STR Invalid spi config -DECL_COMMAND_FLAGS command_spi_set_bus 0 spi_set_bus oid=%c spi_bus=%u mode=%u rate=%u -_DECL_STATIC_STR Invalid spi config -DECL_COMMAND_FLAGS command_config_spi_without_cs 0 config_spi_without_cs oid=%c -DECL_COMMAND_FLAGS command_config_spi 0 config_spi oid=%c pin=%u cs_active_high=%c -_DECL_CALLLIST ctr_run_taskfuncs thermocouple_task -_DECL_STATIC_STR Thermocouple reader fault -_DECL_STATIC_STR Thermocouple reader fault -_DECL_STATIC_STR Thermocouple reader fault -_DECL_STATIC_STR Thermocouple ADC out of range -_DECL_ENCODER thermocouple_result oid=%c next_clock=%u value=%u fault=%c -DECL_COMMAND_FLAGS command_query_thermocouple 0 query_thermocouple oid=%c clock=%u rest_ticks=%u min_value=%u max_value=%u -DECL_COMMAND_FLAGS command_config_thermocouple 0 config_thermocouple oid=%c spi_oid=%c thermocouple_type=%c -_DECL_STATIC_STR Invalid thermocouple chip type -DECL_ENUMERATION thermocouple_type MAX6675 +0x00000003 -DECL_ENUMERATION thermocouple_type MAX31865 +0x00000002 -DECL_ENUMERATION thermocouple_type MAX31856 +0x00000001 -DECL_ENUMERATION thermocouple_type MAX31855 +0x00000000 -DECL_COMMAND_FLAGS command_i2c_modify_bits 0 i2c_modify_bits oid=%c reg=%*s clear_set_bits=%*s -_DECL_STATIC_STR i2c_modify_bits: Odd number of bits! -DECL_COMMAND_FLAGS command_i2c_read 0 i2c_read oid=%c reg=%*s read_len=%u -_DECL_ENCODER i2c_read_response oid=%c response=%*s -DECL_COMMAND_FLAGS command_i2c_write 0 i2c_write oid=%c data=%*s -DECL_COMMAND_FLAGS command_config_i2c 0 config_i2c oid=%c i2c_bus=%u rate=%u address=%u -DECL_COMMAND_FLAGS command_set_pwm_out 0 set_pwm_out pin=%u cycle_ticks=%u value=%hu -_DECL_CALLLIST ctr_run_shutdownfuncs pwm_shutdown -DECL_COMMAND_FLAGS command_queue_pwm_out 0 queue_pwm_out oid=%c clock=%u value=%hu -_DECL_STATIC_STR Scheduled pwm event will exceed max_duration -DECL_COMMAND_FLAGS command_config_pwm_out 0 config_pwm_out oid=%c pin=%u cycle_ticks=%u value=%hu default_value=%hu max_duration=%u -_DECL_STATIC_STR Scheduled pwm event will exceed max_duration -_DECL_STATIC_STR Missed scheduling of next hard pwm event -DECL_COMMAND_FLAGS command_spi_set_software_bus 0 spi_set_software_bus oid=%c miso_pin=%u mosi_pin=%u sclk_pin=%u mode=%u rate=%u -_DECL_STATIC_STR Invalid spi config -_DECL_CALLLIST ctr_run_taskfuncs adxl345_task -DECL_COMMAND_FLAGS command_query_adxl345_status 0 query_adxl345_status oid=%c -DECL_COMMAND_FLAGS command_query_adxl345 0 query_adxl345 oid=%c clock=%u rest_ticks=%u -_DECL_ENCODER adxl345_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%c limit_count=%hu -_DECL_ENCODER adxl345_data oid=%c sequence=%hu data=%*s -DECL_COMMAND_FLAGS command_config_adxl345 0 config_adxl345 oid=%c spi_oid=%c -_DECL_CALLLIST ctr_run_taskfuncs spi_angle_task -DECL_COMMAND_FLAGS command_spi_angle_transfer 0 spi_angle_transfer oid=%c data=%*s -_DECL_ENCODER spi_angle_transfer_response oid=%c clock=%u response=%*s -DECL_COMMAND_FLAGS command_query_spi_angle 0 query_spi_angle oid=%c clock=%u rest_ticks=%u time_shift=%c -_DECL_ENCODER spi_angle_end oid=%c sequence=%hu -_DECL_ENCODER spi_angle_data oid=%c sequence=%hu data=%*s -DECL_COMMAND_FLAGS command_config_spi_angle 0 config_spi_angle oid=%c spi_oid=%c spi_angle_type=%c -_DECL_STATIC_STR angle sensor requires cs pin -_DECL_STATIC_STR Invalid spi_angle chip type -DECL_ENUMERATION spi_angle_type tle5012b +0x00000002 -DECL_ENUMERATION spi_angle_type as5047d +0x00000001 -DECL_ENUMERATION spi_angle_type a1333 +0x00000000 -_DECL_CALLLIST ctr_run_taskfuncs mpu9250_task -DECL_COMMAND_FLAGS command_query_mpu9250_status 0 query_mpu9250_status oid=%c -DECL_COMMAND_FLAGS command_query_mpu9250 0 query_mpu9250 oid=%c clock=%u rest_ticks=%u -_DECL_ENCODER mpu9250_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%u limit_count=%hu -_DECL_ENCODER mpu9250_data oid=%c sequence=%hu data=%*s -DECL_COMMAND_FLAGS command_config_mpu9250 0 config_mpu9250 oid=%c i2c_oid=%c -_DECL_CALLLIST ctr_run_shutdownfuncs st7920_shutdown -DECL_COMMAND_FLAGS command_st7920_send_data 0 st7920_send_data oid=%c data=%*s -DECL_COMMAND_FLAGS command_st7920_send_cmds 0 st7920_send_cmds oid=%c cmds=%*s -DECL_COMMAND_FLAGS command_config_st7920 0 config_st7920 oid=%c cs_pin=%u sclk_pin=%u sid_pin=%u sync_delay_ticks=%u cmd_delay_ticks=%u -_DECL_CALLLIST ctr_run_shutdownfuncs hd44780_shutdown -DECL_COMMAND_FLAGS command_hd44780_send_data 0 hd44780_send_data oid=%c data=%*s -DECL_COMMAND_FLAGS command_hd44780_send_cmds 0 hd44780_send_cmds oid=%c cmds=%*s -DECL_COMMAND_FLAGS command_config_hd44780 0 config_hd44780 oid=%c rs_pin=%u e_pin=%u d4_pin=%u d5_pin=%u d6_pin=%u d7_pin=%u delay_ticks=%u -_DECL_CALLLIST ctr_run_taskfuncs buttons_task -_DECL_ENCODER buttons_state oid=%c ack_count=%c state=%*s -DECL_COMMAND_FLAGS command_buttons_ack 0 buttons_ack oid=%c count=%c -DECL_COMMAND_FLAGS command_buttons_query 0 buttons_query oid=%c clock=%u rest_ticks=%u retransmit_count=%c invert=%c -_DECL_STATIC_STR Invalid buttons retransmit count -DECL_COMMAND_FLAGS command_buttons_add 0 buttons_add oid=%c pos=%c pin=%u pull_up=%c -_DECL_STATIC_STR Set button past maximum button count -DECL_COMMAND_FLAGS command_config_buttons 0 config_buttons oid=%c button_count=%c -_DECL_STATIC_STR Max of 8 buttons -_DECL_CALLLIST ctr_run_shutdownfuncs tmcuart_shutdown -_DECL_CALLLIST ctr_run_taskfuncs tmcuart_task -_DECL_ENCODER tmcuart_response oid=%c read=%*s -DECL_COMMAND_FLAGS command_tmcuart_send 0 tmcuart_send oid=%c write=%*s read=%c -_DECL_STATIC_STR tmcuart data too large -DECL_COMMAND_FLAGS command_config_tmcuart 0 config_tmcuart oid=%c rx_pin=%u pull_up=%c tx_pin=%u bit_time=%u -DECL_COMMAND_FLAGS command_neopixel_send 0 neopixel_send oid=%c -_DECL_ENCODER neopixel_result oid=%c success=%c -DECL_COMMAND_FLAGS command_neopixel_update 0 neopixel_update oid=%c pos=%hu data=%*s -_DECL_STATIC_STR Invalid neopixel update command -DECL_COMMAND_FLAGS command_config_neopixel 0 config_neopixel oid=%c pin=%u data_size=%hu bit_max_ticks=%u reset_min_ticks=%u -_DECL_STATIC_STR Invalid neopixel data_size -_DECL_CALLLIST ctr_run_taskfuncs counter_task -_DECL_ENCODER counter_state oid=%c next_clock=%u count=%u count_clock=%u -DECL_COMMAND_FLAGS command_query_counter 0 query_counter oid=%c clock=%u poll_ticks=%u sample_ticks=%u -DECL_COMMAND_FLAGS command_config_counter 0 config_counter oid=%c pin=%u pull_up=%c -DECL_COMMAND_FLAGS command_config_reset 0x01 config_reset -_DECL_STATIC_STR config_reset only available when shutdown -DECL_CONSTANT_STR MCU linux -_DECL_CALLLIST ctr_run_initfuncs timer_init -_DECL_STATIC_STR Rescheduled timer in the past -DECL_CONSTANT CLOCK_FREQ +0x02FAF080 -_DECL_CALLLIST ctr_run_taskfuncs console_task -_DECL_STATIC_STR Force shutdown command -_DECL_CALLLIST ctr_run_taskfuncs watchdog_task -_DECL_CALLLIST ctr_run_shutdownfuncs pca9685_shutdown -DECL_COMMAND_FLAGS command_set_pca9685_out 0 set_pca9685_out bus=%c addr=%c channel=%c cycle_ticks=%u value=%hu -_DECL_STATIC_STR Invalid pca9685 channel or value -DECL_COMMAND_FLAGS command_queue_pca9685_out 0 queue_pca9685_out oid=%c clock=%u value=%hu -_DECL_STATIC_STR Scheduled pca9685 event will exceed max_duration -_DECL_STATIC_STR Invalid pca9685 value -DECL_COMMAND_FLAGS command_config_pca9685 0 config_pca9685 oid=%c bus=%c addr=%c channel=%c cycle_ticks=%u value=%hu default_value=%hu max_duration=%u -_DECL_STATIC_STR Invalid pca9685 channel or value -_DECL_STATIC_STR Scheduled pca9685 event will exceed max_duration -_DECL_STATIC_STR Missed scheduling of next pca9685 event -DECL_CONSTANT PCA9685_MAX +0x00001000 -_DECL_STATIC_STR Unable to open and init PCA9685 device -_DECL_STATIC_STR Too many i2c devices -_DECL_STATIC_STR All PCA9685 channels must have the same cycle_ticks -_DECL_STATIC_STR Unable to update PCA9685 value -_DECL_STATIC_STR Unable to write to spi -_DECL_STATIC_STR Unable to issue spi ioctl -_DECL_STATIC_STR Unable to set SPI mode -_DECL_STATIC_STR Unable to set SPI speed -_DECL_STATIC_STR Unable to set non-blocking on spi device -_DECL_STATIC_STR Unable to open spi device -_DECL_STATIC_STR Too many spi devices -DECL_ENUMERATION_RANGE spi_bus spidev7.0 +0x00000700 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev6.0 +0x00000600 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev5.0 +0x00000500 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev4.0 +0x00000400 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev3.0 +0x00000300 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev2.0 +0x00000200 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev1.0 +0x00000100 +0x00000010 -DECL_ENUMERATION_RANGE spi_bus spidev0.0 +0x00000000 +0x00000010 -_DECL_STATIC_STR Error on analog read -_DECL_STATIC_STR Unable to open adc device -DECL_ENUMERATION_RANGE pin analog0 +0x00001000 +0x00000008 -DECL_CONSTANT ADC_MAX +0x00000FFF -_DECL_STATIC_STR Unable to config pwm device -DECL_ENUMERATION_RANGE pin pwmchip7/pwm0 +0x00010070 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip6/pwm0 +0x00010060 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip5/pwm0 +0x00010050 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip4/pwm0 +0x00010040 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip3/pwm0 +0x00010030 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip2/pwm0 +0x00010020 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip1/pwm0 +0x00010010 +0x00000010 -DECL_ENUMERATION_RANGE pin pwmchip0/pwm0 +0x00010000 +0x00000010 -DECL_CONSTANT PWM_MAX +0x00008000 -_DECL_STATIC_STR Unable to read i2c device -_DECL_STATIC_STR Unable write i2c device -_DECL_STATIC_STR Unable to open i2c device -DECL_ENUMERATION_RANGE i2c_bus i2c.0 +0x00000000 +0x00000007 -_DECL_STATIC_STR Unable to open in GPIO chip line -_DECL_STATIC_STR Unable to open out GPIO chip line -_DECL_STATIC_STR Unable to open GPIO chip device -_DECL_STATIC_STR GPIO chip device not found -DECL_ENUMERATION_RANGE pin gpiochip7/gpio0 +0x00000700 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip6/gpio0 +0x00000600 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip5/gpio0 +0x00000500 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip4/gpio0 +0x00000400 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip3/gpio0 +0x00000300 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip2/gpio0 +0x00000200 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip1/gpio0 +0x00000100 +0x00000100 -DECL_ENUMERATION_RANGE pin gpiochip0/gpio0 +0x00000000 +0x00000100 -DECL_ENUMERATION_RANGE pin gpio0 +0x00000000 +0x00000100 -_DECL_CALLLIST ctr_run_taskfuncs ds18_task -_DECL_STATIC_STR DS18B20 sensor didn't respond in time -_DECL_STATIC_STR DS18B20 out of range -_DECL_ENCODER ds18b20_result oid=%c next_clock=%u value=%i fault=%u -_DECL_ENCODER ds18b20_result oid=%c next_clock=%u value=%i fault=%u -_DECL_STATIC_STR Error reading DS18B20 sensor -_DECL_STATIC_STR Error getting monotonic clock time -DECL_COMMAND_FLAGS command_query_ds18b20 0 query_ds18b20 oid=%c clock=%u rest_ticks=%u min_value=%i max_value=%i -DECL_COMMAND_FLAGS command_config_ds18b20 0 config_ds18b20 oid=%c serial=%*s max_error_count=%c -_DECL_STATIC_STR Could not start DS18B20 reader thread -_DECL_STATIC_STR Could not start DS18B20 reader thread (cond init) -_DECL_STATIC_STR Could not start DS18B20 reader thread (mutex init) -_DECL_STATIC_STR Invalid DS18B20 serial id, could not open for reading -_DECL_STATIC_STR Invalid DS18B20 serial id, must not contain '/' diff --git a/out/klipper.dict b/out/klipper.dict deleted file mode 100644 index a07e3af..0000000 --- a/out/klipper.dict +++ /dev/null @@ -1 +0,0 @@ -{"build_versions":"gcc: (Debian 8.3.0-6) 8.3.0 binutils: (GNU Binutils for Debian) 2.31.1","commands":{"allocate_oids count=%c":8,"buttons_ack oid=%c count=%c":64,"buttons_add oid=%c pos=%c pin=%u pull_up=%c":66,"buttons_query oid=%c clock=%u rest_ticks=%u retransmit_count=%c invert=%c":65,"clear_shutdown":2,"config_adxl345 oid=%c spi_oid=%c":51,"config_analog_in oid=%c pin=%u":32,"config_buttons oid=%c button_count=%c":67,"config_counter oid=%c pin=%u pull_up=%c":74,"config_digital_out oid=%c pin=%u value=%c default_value=%c max_duration=%u":17,"config_ds18b20 oid=%c serial=%*s max_error_count=%c":80,"config_endstop oid=%c pin=%c pull_up=%c":26,"config_hd44780 oid=%c rs_pin=%u e_pin=%u d4_pin=%u d5_pin=%u d6_pin=%u d7_pin=%u delay_ticks=%u":63,"config_i2c oid=%c i2c_bus=%u rate=%u address=%u":44,"config_mpu9250 oid=%c i2c_oid=%c":57,"config_neopixel oid=%c pin=%u data_size=%hu bit_max_ticks=%u reset_min_ticks=%u":72,"config_pca9685 oid=%c bus=%c addr=%c channel=%c cycle_ticks=%u value=%hu default_value=%hu max_duration=%u":78,"config_pwm_out oid=%c pin=%u cycle_ticks=%u value=%hu default_value=%hu max_duration=%u":47,"config_reset":75,"config_spi oid=%c pin=%u cs_active_high=%c":38,"config_spi_angle oid=%c spi_oid=%c spi_angle_type=%c":54,"config_spi_shutdown oid=%c spi_oid=%c shutdown_msg=%*s":33,"config_spi_without_cs oid=%c":37,"config_st7920 oid=%c cs_pin=%u sclk_pin=%u sid_pin=%u sync_delay_ticks=%u cmd_delay_ticks=%u":60,"config_stepper oid=%c step_pin=%c dir_pin=%c invert_step=%c step_pulse_ticks=%u":23,"config_thermocouple oid=%c spi_oid=%c thermocouple_type=%c":40,"config_tmcuart oid=%c rx_pin=%u pull_up=%c tx_pin=%u bit_time=%u":69,"config_trsync oid=%c":30,"debug_nop":9,"debug_ping data=%*s":10,"debug_read order=%c addr=%u":12,"debug_write order=%c addr=%u val=%u":11,"emergency_stop":3,"endstop_home oid=%c clock=%u sample_ticks=%u sample_count=%c rest_ticks=%u pin_value=%c trsync_oid=%c trigger_reason=%c":25,"endstop_query_state oid=%c":24,"finalize_config crc=%u":6,"get_clock":5,"get_config":7,"get_uptime":4,"hd44780_send_cmds oid=%c cmds=%*s":62,"hd44780_send_data oid=%c data=%*s":61,"i2c_modify_bits oid=%c reg=%*s clear_set_bits=%*s":41,"i2c_read oid=%c reg=%*s read_len=%u":42,"i2c_write oid=%c data=%*s":43,"identify offset=%u count=%c":1,"neopixel_send oid=%c":70,"neopixel_update oid=%c pos=%hu data=%*s":71,"query_adxl345 oid=%c clock=%u rest_ticks=%u":50,"query_adxl345_status oid=%c":49,"query_analog_in oid=%c clock=%u sample_ticks=%u sample_count=%c rest_ticks=%u min_value=%hu max_value=%hu range_check_count=%c":31,"query_counter oid=%c clock=%u poll_ticks=%u sample_ticks=%u":73,"query_ds18b20 oid=%c clock=%u rest_ticks=%u min_value=%i max_value=%i":79,"query_mpu9250 oid=%c clock=%u rest_ticks=%u":56,"query_mpu9250_status oid=%c":55,"query_spi_angle oid=%c clock=%u rest_ticks=%u time_shift=%c":53,"query_thermocouple oid=%c clock=%u rest_ticks=%u min_value=%u max_value=%u":39,"queue_digital_out oid=%c clock=%u on_ticks=%u":15,"queue_pca9685_out oid=%c clock=%u value=%hu":77,"queue_pwm_out oid=%c clock=%u value=%hu":46,"queue_step oid=%c interval=%u count=%hu add=%hi":22,"reset_step_clock oid=%c clock=%u":20,"set_digital_out pin=%u value=%c":13,"set_digital_out_pwm_cycle oid=%c cycle_ticks=%u":16,"set_next_step_dir oid=%c dir=%c":21,"set_pca9685_out bus=%c addr=%c channel=%c cycle_ticks=%u value=%hu":76,"set_pwm_out pin=%u cycle_ticks=%u value=%hu":45,"spi_angle_transfer oid=%c data=%*s":52,"spi_send oid=%c data=%*s":34,"spi_set_bus oid=%c spi_bus=%u mode=%u rate=%u":36,"spi_set_software_bus oid=%c miso_pin=%u mosi_pin=%u sclk_pin=%u mode=%u rate=%u":48,"spi_transfer oid=%c data=%*s":35,"st7920_send_cmds oid=%c cmds=%*s":59,"st7920_send_data oid=%c data=%*s":58,"stepper_get_position oid=%c":19,"stepper_stop_on_trigger oid=%c trsync_oid=%c":18,"tmcuart_send oid=%c write=%*s read=%c":68,"trsync_set_timeout oid=%c clock=%u":28,"trsync_start oid=%c report_clock=%u report_ticks=%u expire_reason=%c":29,"trsync_trigger oid=%c reason=%c":27,"update_digital_out oid=%c value=%c":14},"config":{"ADC_MAX":4095,"CLOCK_FREQ":50000000,"MCU":"linux","PCA9685_MAX":4096,"PWM_MAX":32768,"STATS_SUMSQ_BASE":256},"enumerations":{"i2c_bus":{"i2c.0":[0,7]},"pin":{"analog0":[4096,8],"gpio0":[0,256],"gpiochip0/gpio0":[0,256],"gpiochip1/gpio0":[256,256],"gpiochip2/gpio0":[512,256],"gpiochip3/gpio0":[768,256],"gpiochip4/gpio0":[1024,256],"gpiochip5/gpio0":[1280,256],"gpiochip6/gpio0":[1536,256],"gpiochip7/gpio0":[1792,256],"pwmchip0/pwm0":[65536,16],"pwmchip1/pwm0":[65552,16],"pwmchip2/pwm0":[65568,16],"pwmchip3/pwm0":[65584,16],"pwmchip4/pwm0":[65600,16],"pwmchip5/pwm0":[65616,16],"pwmchip6/pwm0":[65632,16],"pwmchip7/pwm0":[65648,16]},"spi_angle_type":{"a1333":0,"as5047d":1,"tle5012b":2},"spi_bus":{"spidev0.0":[0,16],"spidev1.0":[256,16],"spidev2.0":[512,16],"spidev3.0":[768,16],"spidev4.0":[1024,16],"spidev5.0":[1280,16],"spidev6.0":[1536,16],"spidev7.0":[1792,16]},"static_string_id":{"ADC out of range":26,"All PCA9685 channels must have the same cycle_ticks":50,"Already finalized":13,"Can not set soft pwm cycle ticks while updates pending":20,"Can't add signal that is already active":25,"Can't assign oid":11,"Can't reset time when stepper active":22,"Command parser error":7,"Command request":8,"Could not start DS18B20 reader thread":73,"Could not start DS18B20 reader thread (cond init)":74,"Could not start DS18B20 reader thread (mutex init)":75,"DS18B20 out of range":70,"DS18B20 sensor didn't respond in time":69,"Error getting monotonic clock time":72,"Error on analog read":59,"Error reading DS18B20 sensor":71,"Force shutdown command":43,"GPIO chip device not found":68,"Invalid DS18B20 serial id, could not open for reading":76,"Invalid DS18B20 serial id, must not contain '/'":77,"Invalid buttons retransmit count":36,"Invalid command":5,"Invalid count parameter":23,"Invalid move request size":14,"Invalid neopixel data_size":41,"Invalid neopixel update command":40,"Invalid oid type":12,"Invalid pca9685 channel or value":44,"Invalid pca9685 value":46,"Invalid spi config":27,"Invalid spi_angle chip type":35,"Invalid thermocouple chip type":30,"Max of 8 buttons":38,"Message encode error":6,"Missed scheduling of next digital out event":21,"Missed scheduling of next hard pwm event":33,"Missed scheduling of next pca9685 event":47,"Move queue overflow":15,"Rescheduled timer in the past":42,"Scheduled digital out event will exceed max_duration":19,"Scheduled pca9685 event will exceed max_duration":45,"Scheduled pwm event will exceed max_duration":32,"Set button past maximum button count":37,"Shutdown cleared when not shutdown":2,"Stepper too far in past":24,"Thermocouple ADC out of range":29,"Thermocouple reader fault":28,"Timer too close":3,"Too many i2c devices":49,"Too many spi devices":58,"Unable to config pwm device":61,"Unable to issue spi ioctl":53,"Unable to open GPIO chip device":67,"Unable to open adc device":60,"Unable to open and init PCA9685 device":48,"Unable to open i2c device":64,"Unable to open in GPIO chip line":65,"Unable to open out GPIO chip line":66,"Unable to open spi device":57,"Unable to read i2c device":62,"Unable to set SPI mode":54,"Unable to set SPI speed":55,"Unable to set non-blocking on spi device":56,"Unable to update PCA9685 value":51,"Unable to write to spi":52,"Unable write i2c device":63,"alloc_chunk failed":17,"alloc_chunks failed":16,"angle sensor requires cs pin":34,"config_reset only available when shutdown":9,"i2c_modify_bits: Odd number of bits!":31,"oids already allocated":10,"sentinel timer called":4,"tmcuart data too large":39,"update_digital_out not valid with active queue":18},"thermocouple_type":{"MAX31855":0,"MAX31856":1,"MAX31865":2,"MAX6675":3}},"responses":{"adxl345_data oid=%c sequence=%hu data=%*s":-30,"adxl345_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%c limit_count=%hu":-31,"analog_in_state oid=%c next_clock=%u value=%hu":93,"buttons_state oid=%c ack_count=%c state=%*s":-24,"clock clock=%u":86,"config is_config=%c crc=%u is_shutdown=%c move_count=%hu":87,"counter_state oid=%c next_clock=%u count=%u count_clock=%u":-21,"debug_result val=%u":89,"ds18b20_result oid=%c next_clock=%u value=%i fault=%u":-20,"endstop_state oid=%c homing=%c next_clock=%u pin_value=%c":91,"i2c_read_response oid=%c response=%*s":-32,"identify_response offset=%u data=%.*s":0,"is_shutdown static_string_id=%hu":82,"mpu9250_data oid=%c sequence=%hu data=%*s":-25,"mpu9250_status oid=%c clock=%u query_ticks=%u next_sequence=%hu buffered=%c fifo=%u limit_count=%hu":-26,"neopixel_result oid=%c success=%c":-22,"pong data=%*s":88,"shutdown clock=%u static_string_id=%hu":83,"spi_angle_data oid=%c sequence=%hu data=%*s":-27,"spi_angle_end oid=%c sequence=%hu":-28,"spi_angle_transfer_response oid=%c clock=%u response=%*s":-29,"spi_transfer_response oid=%c response=%*s":94,"starting":81,"stats count=%u sum=%u sumsq=%u":84,"stepper_position oid=%c pos=%i":90,"thermocouple_result oid=%c next_clock=%u value=%u fault=%c":95,"tmcuart_response oid=%c read=%*s":-23,"trsync_state oid=%c can_trigger=%c trigger_reason=%c clock=%u":92,"uptime high=%u clock=%u":85},"version":"v0.10.0-530-g3387a9c2"} \ No newline at end of file diff --git a/out/klipper.elf b/out/klipper.elf deleted file mode 100644 index 3729d16ccb45407c6e527faa6a090c3216f87e6c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 712216 zcmbTf4`5W)mH2<(%#Z|vn17HEkjw;BNUI|9Cu3D!5-b$jiXmF7+cJ|O3Jn7JgA$?5 zB%sx%+s#uHTf1e5|46pAY=z2bEdyBB)^3+VrFPq0hXfU+f2g7)D(3q+?@xF<$?pDs zwBvjCynD|*_ndRjIrrTAURtmH{AYcdrksC%^^B6zlxY@3w;w$GyHWO?Qo1TvBl+(| z>Oz$PG{8@{pL(zTHfraZW!Lj_m3HMm3*fy@u+I5#iqm8lUvu9q~wEEJ^t#J!}sXPCRH<$=S-kIi|^}K+4fywjp$G`r{ zYoGi4BPVl8G9G&T;4g3g@u~Nvt@E>+{hu#>m91`?{K@KmRiw86-5G)P{BIQVK3P>& zBe!$GA0MXve+>f{wF;gC|C(Xyzc>v1YUn9F2cCrhg+;h|y#-3|jPf_<=@b+Qw z-#SeF&SCIR9|r!zVc@R}ga2#8(6f6OJii$RzGN8uwZqhp4%6@4Vd`%m2LG&K>c2Ql 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a/out/src/adccmds.d b/out/src/adccmds.d deleted file mode 100644 index 77fe34d..0000000 --- a/out/src/adccmds.d +++ /dev/null @@ -1,17 +0,0 @@ -out/src/adccmds.o: src/adccmds.c /usr/include/stdc-predef.h src/basecmd.h \ - /usr/lib/gcc/aarch64-linux-gnu/8/include/stddef.h \ - /usr/lib/gcc/aarch64-linux-gnu/8/include/stdint.h /usr/include/stdint.h \ - /usr/include/aarch64-linux-gnu/bits/libc-header-start.h \ - /usr/include/features.h /usr/include/aarch64-linux-gnu/sys/cdefs.h \ - /usr/include/aarch64-linux-gnu/bits/wordsize.h \ - /usr/include/aarch64-linux-gnu/bits/long-double.h \ - /usr/include/aarch64-linux-gnu/gnu/stubs.h \ - /usr/include/aarch64-linux-gnu/gnu/stubs-lp64.h \ - /usr/include/aarch64-linux-gnu/bits/types.h \ - /usr/include/aarch64-linux-gnu/bits/typesizes.h \ - /usr/include/aarch64-linux-gnu/bits/wchar.h \ - /usr/include/aarch64-linux-gnu/bits/stdint-intn.h \ - /usr/include/aarch64-linux-gnu/bits/stdint-uintn.h out/board/gpio.h \ - out/board-generic/board/irq.h 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/usr/include/aarch64-linux-gnu/bits/stdlib-float.h /usr/include/string.h \ - /usr/include/aarch64-linux-gnu/bits/types/locale_t.h \ - /usr/include/aarch64-linux-gnu/bits/types/__locale_t.h \ - /usr/include/strings.h /usr/include/aarch64-linux-gnu/sys/ioctl.h \ - /usr/include/aarch64-linux-gnu/bits/ioctls.h \ - /usr/include/aarch64-linux-gnu/asm/ioctls.h \ - /usr/include/asm-generic/ioctls.h /usr/include/linux/ioctl.h \ - /usr/include/aarch64-linux-gnu/asm/ioctl.h \ - /usr/include/asm-generic/ioctl.h \ - /usr/include/aarch64-linux-gnu/bits/ioctl-types.h \ - /usr/include/aarch64-linux-gnu/sys/ttydefaults.h /usr/include/unistd.h \ - /usr/include/aarch64-linux-gnu/bits/posix_opt.h \ - /usr/include/aarch64-linux-gnu/bits/environments.h \ - /usr/include/aarch64-linux-gnu/bits/confname.h \ - /usr/include/aarch64-linux-gnu/bits/getopt_posix.h \ - /usr/include/aarch64-linux-gnu/bits/getopt_core.h \ - /usr/include/linux/gpio.h /usr/include/linux/const.h \ - /usr/include/linux/types.h /usr/include/aarch64-linux-gnu/asm/types.h \ - /usr/include/asm-generic/types.h /usr/include/asm-generic/int-ll64.h \ - /usr/include/aarch64-linux-gnu/asm/bitsperlong.h \ - /usr/include/asm-generic/bitsperlong.h /usr/include/linux/posix_types.h \ - /usr/include/linux/stddef.h \ - /usr/include/aarch64-linux-gnu/asm/posix_types.h \ - /usr/include/asm-generic/posix_types.h src/command.h \ - /usr/lib/gcc/aarch64-linux-gnu/8/include/stdint.h /usr/include/stdint.h \ - /usr/include/aarch64-linux-gnu/bits/wchar.h \ - /usr/include/aarch64-linux-gnu/bits/stdint-uintn.h src/ctr.h \ - src/compiler.h src/linux/gpio.h src/linux/internal.h \ - /usr/include/signal.h /usr/include/aarch64-linux-gnu/bits/signum.h \ - /usr/include/aarch64-linux-gnu/bits/signum-generic.h \ - /usr/include/aarch64-linux-gnu/bits/types/sig_atomic_t.h \ - /usr/include/aarch64-linux-gnu/bits/types/siginfo_t.h \ - /usr/include/aarch64-linux-gnu/bits/types/__sigval_t.h \ - /usr/include/aarch64-linux-gnu/bits/siginfo-arch.h \ - /usr/include/aarch64-linux-gnu/bits/siginfo-consts.h \ - /usr/include/aarch64-linux-gnu/bits/types/sigval_t.h \ - /usr/include/aarch64-linux-gnu/bits/types/sigevent_t.h \ - /usr/include/aarch64-linux-gnu/bits/sigevent-consts.h \ - /usr/include/aarch64-linux-gnu/bits/sigaction.h \ - /usr/include/aarch64-linux-gnu/bits/sigcontext.h \ - /usr/include/aarch64-linux-gnu/asm/sigcontext.h \ - /usr/include/aarch64-linux-gnu/asm/sve_context.h \ - /usr/include/aarch64-linux-gnu/bits/types/stack_t.h \ - /usr/include/aarch64-linux-gnu/sys/ucontext.h \ - /usr/include/aarch64-linux-gnu/sys/procfs.h \ - /usr/include/aarch64-linux-gnu/sys/time.h \ - /usr/include/aarch64-linux-gnu/sys/user.h \ - /usr/include/aarch64-linux-gnu/bits/sigstack.h \ - /usr/include/aarch64-linux-gnu/bits/ss_flags.h \ - /usr/include/aarch64-linux-gnu/bits/types/struct_sigstack.h \ - /usr/include/aarch64-linux-gnu/bits/sigthread.h out/autoconf.h \ - src/sched.h diff --git a/out/src/linux/gpio.o b/out/src/linux/gpio.o deleted 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JwSG8WeFJ?E$M66E diff --git a/test/klippy/printers.test b/test/klippy/printers.test index 647aeb7..4388fcb 100644 --- a/test/klippy/printers.test +++ b/test/klippy/printers.test @@ -161,6 +161,7 @@ CONFIG ../../config/printer-creality-cr6se-2020.cfg CONFIG ../../config/printer-creality-cr6se-2021.cfg CONFIG ../../config/printer-creality-ender2pro-2021.cfg CONFIG ../../config/printer-creality-ender3-s1-2021.cfg +CONFIG ../../config/printer-creality-ender3-s1pro-2022.cfg CONFIG ../../config/printer-creality-ender3-v2-2020.cfg CONFIG ../../config/printer-creality-ender3max-2021.cfg CONFIG ../../config/printer-creality-ender3pro-2020.cfg

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