/** ****************************************************************************** * @file stm32f072xb.h * @author MCD Application Team * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for STM32F0xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripherals registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2016 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS * @{ */ /** @addtogroup stm32f072xb * @{ */ #ifndef __STM32F072xB_H #define __STM32F072xB_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ #define __CM0_REV 0 /*!< Core Revision r0p0 */ #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32F0xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ typedef enum { /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ /****** STM32F0 specific Interrupt Numbers ******************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupt through EXTI Lines 16 and 31 */ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ FLASH_IRQn = 3, /*!< FLASH global Interrupt */ RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupt */ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */ TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4 to Channel 7 Interrupt */ ADC1_COMP_IRQn = 12, /*!< ADC1 and COMP interrupts (ADC interrupt combined with EXTI Lines 21 and 22 */ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupt */ TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_4_IRQn = 29, /*!< USART3 and USART4 global Interrupt */ CEC_CAN_IRQn = 30, /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ USB_IRQn = 31 /*!< USB global Interrupt & EXTI Line18 Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ #include "system_stm32f0xx.h" /* STM32F0xx System Header */ #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ uint32_t RESERVED3; /*!< Reserved, 0x24 */ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ } ADC_TypeDef; typedef struct { __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ }CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ }CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ }CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ }CAN_TypeDef; /** * @brief HDMI-CEC */ typedef struct { __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint16_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ } COMP_Common_TypeDef; /* Legacy defines */ typedef struct { __IO uint32_t CSR; /*!< Kept for legacy purpose. Use structure 'COMP_Common_TypeDef'. */ }COMP1_2_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ } CRC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ }CRS_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ } DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*!d+dZd?d,dZGd-d.d.eZGd/d d eZd0d1Zy0dd2lmZm Z m!Z!mZmZm"Z"e Z#e!Z$d3Z%Wn2e&k rngZd4Z#iZ$d*a'd5d6Z"dZ%YnXeej(e%se)ed7se d4e*d8d*d9e d:e*d*d;e d:e+d*d;e d:e,d*d;e d:e-d*d;[%dS)@z&Python part of the warnings subsystem.Nwarn warn_explicit showwarning formatwarningfilterwarnings simplefilter resetwarningscatch_warningscCst||||||}t|dS)z7Hook to write a warning to a file; replace if you like.N)WarningMessage_showwarnmsg_impl)messagecategoryfilenamelinenofilelinemsgr1/home/mks/moonraker-env/lib/python3.7/warnings.pyr scCst||||d|}t|S)z.Function to format a warning the standard way.N)r _formatwarnmsg_impl)r r rrrrrrrrscCsP|j}|dkr tj}|dkr dSt|}y||Wntk rJYnXdS)N)rsysstderr_formatwarnmsgwriteOSError)rrtextrrrr sr c Cs|jj}|jd|jd|d|jd}|jdkrpyddl}||j|j}Wqvtk rld}d}YqvXn|j}|r| }|d|7}|j dk ry ddl }Wntk rd}d}Yn4X| }y| |j }Wntk rd}YnX|dk r|d7}x|D]t}|d|j|jf7}y$|dk rD||j|j}nd}Wntk rdd}YnX|r| }|d |7}qWn|s||d 7}|S) N:z:  rz %s Tz-Object allocated at (most recent call last): z File "%s", lineno %s z %s z<: Enable tracemalloc to get the object allocation traceback )r __name__rrr r linecachegetline Exceptionstripsource tracemallocZ is_tracingZget_object_traceback) rr srrr$Ztracingtbframerrrr#sR"           rcCsdyt}Wntk rYn= 0N)append) AssertionError isinstancestrtype issubclassWarningintrecompileI _add_filter)actionr r r3rr5r=rrrrs"   cCsH|dkstd|ft|tr(|dks0tdt|d|d||ddS)aInsert a simple entry into the list of warnings filters (at the front). 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|jjS(N(RR/(R((sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyt_getDatascS`s||j_dS(N(RR/(RR(((sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyt_setDatas(RFRGRRJRKRHR=((R(sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyRIs  t DocumentTypec`sYeZfdZdZdZeeeZdZdZeeeZ RS(c`s2j|d||j_||_||_dS(Nu (RRR/tpublicIdtsystemId(RRRMRN(R (sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyRs  cS`s|jjddS(NupublicIdu(Rtget(R((sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyt _getPublicIdscS`s&|dk r"|jjd|ndS(NupublicId(RRtset(RR(((sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyt _setPublicIds cS`s|jjddS(NusystemIdu(RRO(R((sF/tmp/pip-install-SOs3my/pip/pip/_vendor/html5lib/treebuilders/etree.pyt _getSystemIdscS`s&|dk r"|jjd|ndS(NusystemId(RRRQ(RR(((sF/tmp/pip- /*!< 0x00000040 */ #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ #define SPI_SR_BSY_Pos (7U) #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ #define SPI_SR_FRE_Pos (8U) #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ #define SPI_SR_FRLVL_Pos (9U) #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ #define SPI_SR_FTLVL_Pos (11U) #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ /******************** Bit definition for SPI_DR register *******************/ #define SPI_DR_DR_Pos (0U) #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ /******************* Bit definition for SPI_CRCPR register *****************/ #define SPI_CRCPR_CRCPOLY_Pos (0U) #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */ #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ /****************** Bit definition for SPI_RXCRCR register *****************/ #define SPI_RXCRCR_RXCRC_Pos (0U) #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */ #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ /****************** Bit definition for SPI_TXCRCR register *****************/ #define SPI_TXCRCR_TXCRC_Pos (0U) #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */ #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ /****************** Bit definition for SPI_I2SCFGR register ****************/ #define SPI_I2SCFGR_CHLEN_Pos (0U) #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!