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plus4的klipper版本
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204
lib/hc32f460/driver/inc/hc32f460_timer4_cnt.h
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204
lib/hc32f460/driver/inc/hc32f460_timer4_cnt.h
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/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_timer4_cnt.h
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**
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** A detailed description is available at
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** @link Timer4CntGroup Timer4CNT description @endlink
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**
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** - 2018-11-02 CDT First version for Device Driver Library of Timer4CNT.
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**
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******************************************************************************/
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#ifndef __HC32F460_TIMER4_CNT_H__
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#define __HC32F460_TIMER4_CNT_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup Timer4CntGroup Timer4 Counter(Timer4CNT)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief Timer4 count mode enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_cnt_mode
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{
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Timer4CntSawtoothWave = 0u, ///< Timer4 count mode:sawtooth wave
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Timer4CntTriangularWave = 1u, ///< Timer4 count mode:triangular wave
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} en_timer4_cnt_mode_t;
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/**
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*******************************************************************************
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** \brief CNT Clock Setting
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief Timer4 CNT clock division enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_cnt_clk_div
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{
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Timer4CntPclkDiv1 = 0u, ///< Timer4 clock: PCLK
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Timer4CntPclkDiv2 = 1u, ///< Timer4 clock: PCLK/2
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Timer4CntPclkDiv4 = 2u, ///< Timer4 clock: PCLK/4
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Timer4CntPclkDiv8 = 3u, ///< Timer4 clock: PCLK/8
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Timer4CntPclkDiv16 = 4u, ///< Timer4 clock: PCLK/16
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Timer4CntPclkDiv32 = 5u, ///< Timer4 clock: PCLK/32
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Timer4CntPclkDiv64 = 6u, ///< Timer4 clock: PCLK/64
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Timer4CntPclkDiv128 = 7u, ///< Timer4 clock: PCLK/128
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Timer4CntPclkDiv256 = 8u, ///< Timer4 clock: PCLK/256
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Timer4CntPclkDiv512 = 9u, ///< Timer4 clock: PCLK/512
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Timer4CntPclkDiv1024 = 10u, ///< Timer4 clock: PCLK/1024
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} en_timer4_cnt_clk_div_t;
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/**
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*******************************************************************************
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** \brief Timer4 CNT clock soucre selection enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_cnt_clk
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{
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Timer4CntPclk = 0u, ///< Uses the internal clock (PCLK) as CNT's count clock.
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Timer4CntExtclk = 1u, ///< Uses an external input clock (EXCK) as CNT's count clock.
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} en_timer4_cnt_clk_t;
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/**
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*******************************************************************************
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** \brief Timer4 CNT interrupt selection enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_cnt_int
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{
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Timer4CntZeroMatchInt = (1ul << 8), ///< zero match interrupt
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Timer4CntPeakMatchInt = (1ul << 13), ///< peak match interrupt
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} en_timer4_cnt_int_t;
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/**
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*******************************************************************************
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** \brief Timer4 CNT interrupt mask times enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_cnt_int_mask
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{
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Timer4CntIntMask0 = 0u, ///< CNT interrupt flag is always set(not masked) for every CNT count at "0x0000" or peak.
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Timer4CntIntMask1 = 1u, ///< CNT interrupt flag is set once for 2 every CNT counts at "0x0000" or peak (skiping 1 count).
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Timer4CntIntMask2 = 2u, ///< CNT interrupt flag is set once for 3 every CNT counts at "0x0000" or peak (skiping 2 count).
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Timer4CntIntMask3 = 3u, ///< CNT interrupt flag is set once for 4 every CNT counts at "0x0000" or peak (skiping 3 count).
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Timer4CntIntMask4 = 4u, ///< CNT interrupt flag is set once for 5 every CNT counts at "0x0000" or peak (skiping 4 count).
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Timer4CntIntMask5 = 5u, ///< CNT interrupt flag is set once for 6 every CNT counts at "0x0000" or peak (skiping 5 count).
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Timer4CntIntMask6 = 6u, ///< CNT interrupt flag is set once for 7 every CNT counts at "0x0000" or peak (skiping 6 count).
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Timer4CntIntMask7 = 7u, ///< CNT interrupt flag is set once for 8 every CNT counts at "0x0000" or peak (skiping 7 count).
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Timer4CntIntMask8 = 8u, ///< CNT interrupt flag is set once for 9 every CNT counts at "0x0000" or peak (skiping 8 count).
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Timer4CntIntMask9 = 9u, ///< CNT interrupt flag is set once for 10 every CNT counts at "0x0000" or peak (skiping 9 count).
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Timer4CntIntMask10 = 10u, ///< CNT interrupt flag is set once for 11 every CNT counts at "0x0000" or peak (skiping 10 count).
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Timer4CntIntMask11 = 11u, ///< CNT interrupt flag is set once for 12 every CNT counts at "0x0000" or peak (skiping 11 count).
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Timer4CntIntMask12 = 12u, ///< CNT interrupt flag is set once for 13 every CNT counts at "0x0000" or peak (skiping 12 count).
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Timer4CntIntMask13 = 13u, ///< CNT interrupt flag is set once for 14 every CNT counts at "0x0000" or peak (skiping 13 count).
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Timer4CntIntMask14 = 14u, ///< CNT interrupt flag is set once for 15 every CNT counts at "0x0000" or peak (skiping 14 count).
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Timer4CntIntMask15 = 15u, ///< CNT interrupt flag is set once for 16 every CNT counts at "0x0000" or peak (skiping 15 count).
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} en_timer4_cnt_int_mask_t;
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/**
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*******************************************************************************
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** \brief Timer4 CNT initialization configuration
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**
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******************************************************************************/
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typedef struct stc_timer4_cnt_init
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{
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uint16_t u16Cycle; ///< CNT cycle
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en_timer4_cnt_mode_t enCntMode; ///< CNT count mode and this parameter can be a value of @ref en_timer4_cnt_mode_t
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en_timer4_cnt_clk_t enClk; ///< CNT Count clock and this parameter can be a value of @ref en_timer4_cnt_clk_t
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en_timer4_cnt_clk_div_t enClkDiv; ///< CNT clock divide and this parameter can be a value of @ref en_timer4_cnt_clk_div_t
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en_functional_state_t enBufferCmd; ///< Disable: Disable buffer function; Enable:Enable buffer function
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en_functional_state_t enZeroIntCmd; ///< Disable: Disable zero match interrupt; Enable:zero match interrupt
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en_functional_state_t enPeakIntCmd; ///< Disable: Disable peak match interrupt; Enable:peak match interrupt
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en_timer4_cnt_int_mask_t enZeroIntMsk; ///< CNT zero interrupt mask times and this parameter can be a value of @ref en_timer4_cnt_int_mask_t
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en_timer4_cnt_int_mask_t enPeakIntMsk; ///< CNT peak interrupt mask times and this parameter can be a value of @ref en_timer4_cnt_int_mask_t
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} stc_timer4_cnt_init_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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en_result_t TIMER4_CNT_Init(M4_TMR4_TypeDef *TMR4x,
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const stc_timer4_cnt_init_t *pstcInitCfg);
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en_result_t TIMER4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_clk_t enCntClk);
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en_timer4_cnt_clk_t TIMER4_CNT_GetClock(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_SetClockDiv(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_clk_div_t enClkDiv);
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en_timer4_cnt_clk_div_t TIMER4_CNT_GetClockDiv(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_mode_t enMode);
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en_timer4_cnt_mode_t TIMER4_CNT_GetMode(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_Start(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_Stop(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_IrqCmd(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_int_t enIntType,
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en_functional_state_t enCmd);
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en_flag_status_t TIMER4_CNT_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_int_t enIntType);
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en_result_t TIMER4_CNT_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_int_t enIntType);
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en_result_t TIMER4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Cycle);
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uint16_t TIMER4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16Count);
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uint16_t TIMER4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x);
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en_result_t TIMER4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_int_t enIntType,
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en_timer4_cnt_int_mask_t enMaskTimes);
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en_timer4_cnt_int_mask_t TIMER4_CNT_GetIntMaskTimes(M4_TMR4_TypeDef *TMR4x,
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en_timer4_cnt_int_t enIntType);
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//@} // Timer4CntGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F460_TIMER4_CNT_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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